# Power MOSFET, N Channel, 75 V, 120 A, 5800 µohm, TO-220AB, Through Hole

![Product image](https://novapart.co/image/farnell:1436952/)

**URL**: https://novapart.co/products/IRFB3307ZPBF/power-mosfet-n-channel-75-v-120-a-5800-ohm-to
**SKU**: IRFB3307ZPBF
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.7410
**Stock**: 200+
**Lead Time**: 64 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:120A; Drain Source Voltage Vds:75V; On Resistance Rds(on):0.0058ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Power Diss

## Specifications

| Parameter | Value |
|---|---|
| Msl | - |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 230W |
| Transistor Mounting | Through Hole |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-220AB |
| Drain Source Voltage Vds | 75V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 120A |
| Drain Source On State Resistance | 5800µohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1436952/)

## **Applications** 

- High Efficiency Synchronous Rectification in SMPS 

- Uninterruptible Power Supply 

High Speed Power Switching Hard Switched and High Frequency Circuits 

> **Benefits** . Improved  Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA 

Enhanced body diode dV/dt and dI/dt Capability 

## IRFB3307ZPbF IRFS3307ZPbF IRFSL3307ZPbF 

HEXFET ® Power MOSFET 

> D **VDSS** ~~eee~~ **75V RDS(on)   typ. 4.6m** Ω **max. 5.8m** Ω 

> G **ID (Silicon Limited)** ~~FD~~ **128A** S **ID (Package Limited)** ~~Po~~ **120A** 

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D<br>D D<br>S<br>S S D<br>D G G<br>G<br>TO-220AB D [2] Pak TO-262<br>IRFB3307ZPbF IRFS3307ZPbF IRFSL3307ZPbF<br>**----- End of picture text -----**<br>


||**G**<br>**D**<br>**S**||
|---|---|---|
||Gate<br>Drain<br>Source||
|**Absolute Maximum Ratings**|||
|**Symbol**|**Parameter**<br>**Units**<br>**Max.**||
|ID @ TC = 25°C<br>ID@ TC= 100°C<br>ID @ TC = 25°C<br>IDM<br>PD @TC = 25°C<br>VGS<br>dv/dt|Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>Continuous Drain Current,VGS @ 10V(Silicon Limited)<br>A<br>Continuous Drain Current,VGS@ 10V(Wire Bond Limited)<br>Pulsed Drain Current<br>Maximum Power Dissipation<br>W<br>Linear DeratingFactor<br>W/°C<br>Gate-to-Source Voltage<br>V<br>Peak Diode Recovery<br>V/ns<br>230<br>6.7<br>± 20<br>1.5<br>128<br>90<br>512<br>120<br>~~Pe~~<br>~~re~~<br>~~es nnn~~<br>~~Po~~<br>~~eee~~<br>~~nD~~<br>~~I~~<br>~~nD~~<br>~~nn~~<br>~~nnn~~<br>~~GE~~<br>~~PoOe~~||
|TJ|Operating Junction and<br>°C<br>-55  to + 175||
|TSTG|Storage Temperature Range||
||Soldering Temperature, for 10 seconds<br>300||
||(1.6mm from case)||
|Mountingtorque,6-32 or M3 screw<br>**Avalanche Characteristics**<br>10lbf in(1.1N m)<br>~~nD~~<br>~~nnn~~<br>~~nC~~<br>~~EE~~|||
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>See Fig. 14, 15, 22a, 22b<br>140<br>~~ee~~<br>~~ee~~|||
|**Thermal Resistance**|||
|**Symbol**|**Parameter**<br>**Typ.**<br>**Max.**<br>**Units**<br>~~fee~~||
|RθJC<br>RθCS|Junction-to-Case<br>–––<br>0.65<br>Case-to-Sink,Flat Greased Surface,TO-220<br>0.50<br>–––<br>°C/W<br>~~©~~<br>~~rs~~||
|RθJA<br>RθJA|Junction-to-Ambient,TO-220<br>–––<br>62<br>Junction-to-Ambient (PCB Mount) , D2Pak<br>–––<br>40<br>~~a~~<br>~~©Se~~<br>~~PF~~<br>~~eeewi~~||



www.irf.com 

1 

08/19/11 

**Static @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|---|---|
|V(BR)DSS<br>ΔV(BR)DSS/ΔTJ<br>RDS(on)<br>VGS(th)<br>RG(int)<br>IDSS<br>IGSS|Drain-to-Source Breakdown Voltage<br>75<br>–––<br>–––<br>V<br>Breakdown Voltage Temp. Coefficient<br>–––<br>0.094<br>–––<br>V/°C<br>Static Drain-to-Source On-Resistance<br>–––<br>4.6<br>5.8<br>mΩ<br>Gate Threshold Voltage<br>2.0<br>–––<br>4.0<br>V<br>InternalGate Resistance<br>–––<br>0.70<br>–––<br>Ω<br>Drain-to-Source Leakage Current<br>–––<br>–––<br>20<br>μA<br>–––<br>–––<br>250<br>Gate-to-Source Forward Leakage<br>–––<br>–––<br>100<br>nA<br>Gate-to-Source Reverse Leakage<br>–––<br>–––<br>-100<br>VGS= 20V<br>VGS= -20V<br>VGS= 0V, ID= 250μA<br>Reference to 25°C, ID= 5mA<br>VGS= 10V, ID= 75A<br>VDS= VGS, ID= 150μA<br>VDS= 75V, VGS= 0V<br>VDS= 75V, VGS= 0V, TJ= 125°C<br>~~GO~~<br>~~QO GO~~<br>~~eS~~<br>~~GO QD QO~~<br>~~QO~~<br>~~GO~~<br>~~©~~<br>~~RS~~<br>~~QO QO~~<br>~~eS~~<br>~~QO OsQO~~<br>~~ee EE]~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~a~~|
|**Dynamic @ TJ = 25°C (unless otherwise specified)**||
|**Symbol**|**Parameter**<br>**Min. Typ. Max. Units**<br>**Conditions**|
|gfs<br>Qg<br>Qgs<br>Qgd<br>Qsync|Forward Transconductance<br>320<br>–––<br>–––<br>S<br>Total Gate Charge<br>–––<br>79<br>110<br>nC<br>Gate-to-Source Charge<br>–––<br>19<br>–––<br>Gate-to-Drain("Miller")Charge<br>–––<br>24<br>–––<br>Total Gate Charge Sync.(Qg - Qgd)<br>–––<br>55<br>–––<br>VDS= 50V,ID= 75A<br>ID= 75A<br>VDS= 38V<br>VGS= 10V<br>ID= 75A, VDS=0V, VGS= 10V<br>~~RS~~<br>~~GO QOD~~<br>~~a~~<br>~~aRe~~<br>~~©~~<br>~~es~~|
|td(on)|Turn-On DelayTime<br>–––<br>15<br>–––<br>ns<br>VDD= 49V<br>~~a~~|
|tr<br>td(off)|Rise Time<br>–––<br>64<br>–––<br>Turn-Off DelayTime<br>–––<br>38<br>–––<br>ID= 75A<br>RG= 2.6Ω<br>~~a~~<br>~~es~~|
|tf|Fall Time<br>–––<br>65<br>–––<br>VGS= 10V<br>~~a©~~|
|Ciss|Input Capacitance<br>–––<br>4750<br>–––<br>pF<br>VGS= 0V<br>~~a~~|
|Coss|Output Capacitance<br>–––<br>420<br>–––<br>VDS= 50V<br>~~es~~|
|Crss<br>Cosseff. (ER)<br>Coss eff.(TR)|Reverse Transfer Capacitance<br>–––<br>190<br>–––<br>Effective Output Capacitance(EnergyRelated)<br>–––<br>440<br>–––<br>EffectiveOutputCapacitance(Time Related)<br>–––<br>410<br>–––<br>ƒ= 1.0MHz<br>VGS= 0V, VDS= 0V to 60V<br>VGS= 0V,VDS= 0V to 60V<br>~~es~~<br>~~a”~~<br>~~a~~<br>©|
|**Diode Characteristics**||
|**Symbol**<br>IS<br>ISM<br>VSD<br>trr<br>Qrr<br>IRRM|S<br>D<br>G<br>**Parameter**<br>**Min. Typ. Max. Units**<br>Continuous Source Current<br>–––<br>–––<br>128<br>A<br>(BodyDiode)<br>Pulsed Source Current<br>–––<br>–––<br>512<br>(BodyDiode)<br>Diode Forward Voltage<br>–––<br>–––<br>1.3<br>V<br>Reverse Recovery Time<br>–––<br>33<br>50<br>ns<br>TJ= 25°C<br>VR= 64V,<br>–––<br>39<br>59<br>TJ= 125°C<br>IF= 75A<br>Reverse Recovery Charge<br>–––<br>42<br>63<br>nC<br>TJ= 25°C<br>di/dt = 100A/μs<br>–––<br>56<br>84<br>TJ= 125°C<br>Reverse RecoveryCurrent<br>–––<br>2.2<br>–––<br>A<br>TJ= 25°C<br>MOSFET symbol<br>showing  the<br>**Conditions**<br>TJ= 25°C, IS= 75A, VGS= 0V<br>integral reverse<br>p-njunction diode.<br>~~DD~~<br>~~OO ON QO GO~~<br>~~Po~~<br>~~sooo~~<br>~~|~~<br>~~GO~~<br>~~GO (©~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**e**e ae~~<br>~~ee~~<br>~~s~~|
|ton|Forward Turn-On Time<br>Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)<br>~~GO~~|



Notes: ® Calculated continuous current based on maximum allowable junction ® ISD ≤ 75A, di/dt ≤ 1570A/μs, VDD ≤ V(BR)DSS, TJ , TJ ≤ 175°C. 

® Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 120A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. 

® ISD ≤ 75A, di/dt ≤ 1570A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. © Pulse width ≤ 400μs; duty cycle ≤ 2%. © Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

Repetitive rating;  pulse width limited by max. junction temperature. 

Coss eff. (ER) is a fixed capacitance that gives the same energy as 

Coss while VDS is rising from 0 to 80% VDSS. 

Limited by TJmax, starting TJ = 25°C, L = 0.050mH 

When mounted on 1" square PCB (FR-4 or G-10 Material).  For recom mended footprint and soldering techniques refer to application note #AN-994. R θ is measured at TJ approximately 90°C. 

RG = 25 Ω , IAS = 75A, VGS =10V. Part not recommended for use above this value. 

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1000<br>VGS<br>TOP           15V<br>10V<br>8.0V<br>6.0V<br>5.5V<br>5.0V<br>100 4.8V<br>BOTTOM 4.5V<br>| 7<br>| araaeo<br>4.5V<br>GT<br>10 | |i Till<br>≤ 60μs PULSE WIDTH<br>1 ieSS Tj = 25°C rn<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>100 a<br>aa aa<br>——— T J  = 175°C<br>T = 25°C<br>10 J<br>1<br>Afi | |<br>TP<br>1<br>py<br>VDS = 25V<br>SS<br>≤ 60μs PULSE WIDTH<br>PA<br>0.1<br>2 3 4 5 6 7 8<br>VGS, Gate-to-Source Voltage (V)<br>Fig 3.   Typical Transfer Characteristics<br>100000<br>VGS   = 0V,       f = 1 MHZ<br>Ciss   = C gs + Cgd,  C ds SHORTED<br>C  = C<br>rss   gd<br>C = C + C<br>| oss   ds  gd<br>10000 rr<br>C<br>iss<br>Coss<br>1000 Po<br>pe ett<br>C<br>rss<br>a e eSEe<br>100<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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1000<br>VGS<br>TOP           15V<br>10V<br>8.0V<br>6.0V<br>5.5V<br>5.0V<br>100 4.8V<br>BOTTOM 4.5V<br>Py su 4.5V enll|<br>|grt<br>th<br>10 Py 0ll<br>≤ 60μs PULSE WIDTH<br>1 aiepS Tj = 175°C ay maaill<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.5<br>I = 72A<br>D<br>V GS  = 10V<br>TEE<br>2.0<br>HA<br>PETE<br>1.5<br>LT EYL<br>SEEEREEYAEEn<br>TELA<br>1.0 A<br>TT<br>LALLA<br>at<br>0.5<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>12.0<br>I = 72A<br>D<br>10.0 V DS = 60V<br>Pe VDS= 38V<br>8.0 Sh VDS= 15V<br>6.04.0 anew<br>fT<br>2.0<br>Viti} yd<br>0.0<br>0 10 20 30 40 50 60 70 80 90<br> QG,  Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000<br>T = 175°C<br>100 J<br>TJ = 25°C<br>10<br>1<br>VGS = 0V<br>0.1<br>0.0 0.5 1.0 1.5 2.0<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Forward Voltage<br>140<br>120 | | | | |<br>100<br>APN TP<br>80<br>Rena<br>Limited By Package<br>60<br>po NN<br>40<br>ae<br>20<br>P|] | tN<br>0<br>|| | | | | \<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ISD, Reverse Drain Current (A)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 7.** Typical Source-Drain Diode Forward Voltage 

**Fig 9.** Maximum Drain Current vs. Case Temperature 

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1.2<br>1.0<br>0.8 PTTTf<br>0.6 PTA<br>0.4<br>AT<br>0.2<br>ATTAT<br>0.0<br>20 30 40 50 60 70 80<br>VDS, Drain-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 11.** Typical COSS Stored Energy 

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10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>1000<br>100 100μsec<br>1msec<br>10 1 0msec<br>DC<br>1 Tc = 25°C<br>Tj = 175°C<br>Single Pulse<br>0.1<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>100<br>Id = 5mA<br>95 PEE<br>90<br>Ti [LITT]<br>85<br>er<br>80<br>CeaBEREPZARREEE<br>75<br>EE<br>70<br>ALLE EEE<br>65<br>ELLT TEL TELE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

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600<br>ID<br>TOP         15A<br>500<br>26A<br>BOTTOM 75A<br>ACLST<br>400<br>300 ONT<br>200<br>NIN<br>100<br>PSSSOSAN CHHREE<br>0<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

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1<br>St D = 0.50 SE em |<br>0.20<br>0.1 se err|<br>0.10<br>a 0.05 R 1 R1 R 2 R2 R 3 R 3 SHES Ri ( ° C/W)  SETHE  τ i (sec)<br>0.01 en!)ee 0.01 0.02 46 τ J τ ee J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 τ C τ | 0.1164    0.0000880.3009 0.001312 il<br>Ci=  τ i / Ri 0.2313    0.009191<br>=aPT A EEce ee Ci i / Ri ee ee:<br>| 8|A SINGLE PULSE es ee ee eee Notes: et re ee ee<br>( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.001 Y oo EEEHE | LUTTERIP HEll<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>100<br>Allowed avalanche Current vs avalanche<br>0.01<br>pulsewidth, tav, assuming  Δ Tj = 150°C and<br>a ee ee Duty Cycle =  ee eee Tstart =25°C (Single Pulse) |<br>0.05 Single Pulse<br>10 A) RSS sth;<br>0.10<br>a<br>Poe<br>GEILEsss Er<br>1 fe<br>eee<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ΔΤ j = 25°C and<br>Tstart = 150°C.<br>0.1 BERSLeEE ET TTH<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>150 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>125 Nail BOTTOM   1.0% Duty Cycle I D  = 75A 1. Avalanche failures assumption:Purely a thermal phenomenon and failure occurs at a temperature far in<br>excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>100 N ONEWoEee 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>75 INN LEED 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>IN IN . during avalanche).<br>6. Iav = Allowable avalanche current.<br>50 7.  Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>HN tav = Average time in avalanche.<br>25 D = Duty cycle in avalanche =  tav ·f<br>ENA ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>0 EL LEELENN<br>PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = T/ ZthJCthJC<br>25 50 75 100 125 150 175<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>Thermal Response ( Z thJC )<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 

4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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4.5 pt | | tf tf ft ft ft ft ft<br>4.0 pote tT | EE TT<br>| | Po] ft ft yy<br>3.5 p eat | Pea} ft tt<br>|SSP<br>3.0 Pt TERA TT<br>Pot |] ASSAY<br>2.5 Pot} ft | |tT PPRAR et<br>AAZTS™N | |<br>2.0 ID = 150μA 4 A_X_ INANE<br>ID = 250μA Z2A@mNwNeZn<br>1.5 I D  = 1.0mA me eNe<br>I D  = 1.0A<br>1.0 PF | | | dT TN<br>t<br>0.5 po t Pt | ft ty ft<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


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20<br>IF = 48A<br>VR = 64VT  = 25°C ,<br>15 J ¢<br>TJ = 125°C as<br>10 Pea Z|<br>~<br>,<br>i<br>“Z|<br>5<br>~<br>y<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>IRR (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage vs. Temperature 

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20<br>IF = 72A<br>VR = 64V<br>T  = 25°C 4<br>15 J<br>TJ = 125°C<br>ao<br>jo? y<br>10<br>a 4<br>ie<br>5<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>IRR (A)<br>**----- End of picture text -----**<br>


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420<br>IF = 48A<br>340 VR = 64V vAcA<br>TJ = 25°C ,<br>TJ = 125°C<br>260 it kocA<br>VA<br>180<br>/ Ws<br>Je Pal Z|<br>be<br>100<br>20<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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420<br>IF = 72A<br>VR = 64V [|<br>340<br>TJ = 25°C 4<br>TJ = 125°C @ eA<br>Le Z|<br>260<br>eA<br>4<br>¢<br>180 ZI<br>aae +? ° ° ayO<br>100<br>Ean<br>20<br>0 200 400 600 800 1000<br>diF /dt (A/μs)<br>QRR (A)<br>**----- End of picture text -----**<br>


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**==> picture [415 x 664] intentionally omitted <==**

**----- Start of picture text -----**<br>
Driver Gate Drive<br>P.W.<br>D.U.T + { P.W. + Period ——— + D = —— Period<br>) [©)]    •  CircuitLow  LayoutS ConsiderationsInd | V t t GS=10<br> •<br>- •   CurrentLow LeakageTransformerInductance @ D.U.T. ISD Waveform<br>+<br>= ReverseRecovery Body Diode Forward \<br>- a - ® + Current r Current di/dt /<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 > VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re (A •   dv/dt controlled by Rg Vp p -<br>•<br>D.U.T. - Device Under Test SCO |<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @\ t<br>* Vg = 5V for Logic Level Devices<br>Fig 20.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V << tp ><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>AE / \<br>t 2V0VGS ae<br>tp 0.01 Ω IAS<br> Unclamped Inductive Test Circuit Fig 21b.   Unclamped Inductive Waveforms<br>LD<br>VDS VDS<br>90%<br>+<br>VDD -<br>D.U.T 10% x \<br>VGS VGS<br>Pulse Width < 1μs<br>Duty Factor < 0.1% td(on) tr td(off) tf<br>  Switching Time Test Circuit Fig 22b.   Switching Time Waveforms<br>Id<br>Vds<br>Vgs<br>L<br>VCC<br>DUT<br>Vgs(th)<br>1K<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 21b.** Unclamped Inductive Waveforms 

**Fig 21a.** Unclamped Inductive Test Circuit 

**Fig 22a.** Switching Time Test Circuit 

**==> picture [186 x 41] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>VCC<br>DUT<br>0<br>1K<br>**----- End of picture text -----**<br>


**Fig 23a.** Gate Charge Test Circuit 

**Fig 23b.** Gate Charge Waveform 

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7 

**Note:** "P" in assembly line position indicates "Lead-Free" 

TO-220AB packages are not recommended for Surface Mount Application. 

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## TO-262 Package Outline Dimensions are shown in millimeters (inches) 

## TO-262 Part Marking Information 

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Dimensions are shown in millimeters (inches) 

**==> picture [18 x 7] intentionally omitted <==**

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TRR<br>**----- End of picture text -----**<br>


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1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>1.50 (.059)<br>3.90 (.153) 0.368 (.0145)<br>2 _______* !0 0°0Hd 0 | i oOo OO 41S | @ T - e 0.342 (.0135)<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>10.70 (.421) 4.72 (.136)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>**----- End of picture text -----**<br>


**==> picture [74 x 8] intentionally omitted <==**

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FEED DIRECTION<br>**----- End of picture text -----**<br>


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13.50 (.532) 27.40 (1.079)<br>12.80 (.504) 23.90 (.941) 1<br>4<br>330.00(14.173) \ g 60.00 (2.362)      MIN.<br>  MAX.<br>g x<br>30.40 (1.197)<br>NOTES :       MAX.<br>1.   COMFORMS TO EIA-418.<br>2.   CONTROLLING DIMENSION: MILLIMETER. 26.40 (1.03924.40 (.961) I ) c 4<br>3.   DIMENSION MEASURED @ HUB.<br>3<br>**----- End of picture text -----**<br>


4.   INCLUDES FLANGE DISTORTION @ OUTER EDGE. 

Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. 

**IR WORLD HEADQUARTERS:** 101 N. Sepulveda Blvd., El Segundo, California 90245, USA Tel: (310) 252-7105 

TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 08/11 

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11 

## **IMPORTANT NOTICE** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”) . 

With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. 

In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. 

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. 

For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). 

## **WARNINGS** 

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. 

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 



## Links

- [View this product on Novapart](https://novapart.co/products/IRFB3307ZPBF/power-mosfet-n-channel-75-v-120-a-5800-ohm-to)
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- [Supplier page](https://es.farnell.com/infineon/irfb3307zpbf/mosfet-n-75v-to-220ab/dp/1436952)
---

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