# Power MOSFET, N Channel, 80 V, 180 A, 1100 µohm, TO-263 (D2PAK), Surface Mount

![Product image](https://novapart.co/image/farnell:2725833RL/)

**URL**: https://novapart.co/products/IPB015N08N5ATMA1/power-mosfet-n-channel-80-v-180-a-1100-ohm-to-263
**SKU**: IPB015N08N5ATMA1
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €2.8600
**Stock**: 1000+
**Lead Time**: 106 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:180A; Drain Source Voltage Vds:80V; On Resistance Rds(on):0.0011ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Pow

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 7Pins |
| Channel Type | N Channel |
| Product Range | OptiMOS 5 |
| Qualification | - |
| Power Dissipation | 375W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-263 (D2PAK) |
| Drain Source Voltage Vds | 80V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 180A |
| Drain Source On State Resistance | 1100µohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2725833RL/)

## MOSFET 

**OptiMOS[TM]** OptiMOS[™] 5 IPB015N08N5 

Final 

## **OptiMOS[ª]** 

## 5 Power-Transistor, IPB015N08N5 80 V 

## IPB015N08N5 

## **Features** 

* Optimized technology for DC/DC converters _R_ DS(on) ¢ Excellent gate charge x product DS(on) ¢ Very low on-resistance R 

|_R_DS(on)<br>DS(on)<br>* Ideal forhighfrequencyswitching<br>* Optimized technology for DC/DC<br>¢ Excellent gate charge x<br>¢ VeryVery low on-resistanceon-resistance R<br>¢ N-channel, normal level|switching and sync. rec.<br>DC/DC converters<br>product(FOM)|switching and sync. rec.<br>DC/DC converters<br>product(FOM)||1<br>J|—<br>o|—<br>o|=<br>—<br> So<br>Se|=<br>—<br> So<br>Se|=<br>a||tab<br>’|tab<br>’||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|* 100% avalanche tested||||||7||||||||
|¢ Pb-free plating; ROHS compliant||||||||||||||
|* Qualified according to JEDEC|for target applications|||||||||||||
|¢ Halogen-free according to IEC61249-2-21||||||||||||||
||||||||||||Drain|||
|Table<br>1<br>Key<br>Performance Parameters||||||||||Pin 4, tab||||
|**Parameter**<br>**Value**||**Unit**||||||||||||
|||||||||Gate||||||
|_V_DS<br>80||V||||||Pin 1||||||
|_R_DS(on),max<br>1.5||mΩ||||||||Source<br>Pin 2,3,5,6,7||||
|_I_D<br>180||A||||||||||||
|||||||||||||||
|_Q_oss<br>207||nC||||||||||||
|||||||(PB)|(PB)|(PB)|(PB)||C|C|C|
|_Q_G(0V..10V)<br>178||nC||||(PB)|(PB)|(PB)|(PB)||C|C|C|



||**Package**|**Marking**||
|---|---|---|---|
|IPB015N08N5|PG-TO263-7|015N08N5|-|



1) J-STD20 and JESD22 

Final Data Sheet 

2 

**OptiMOS[ª] ��5�Power-Transistor,�80�V** 

IPB015N08N5 

**==> picture [146 x 65] intentionally omitted <==**

## **Table�of�Contents** 

Description   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Maximum ratings   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Thermal characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics diagrams  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package Outlines  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision History  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimer   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 

Final Data Sheet 

3 

Rev.�2.1,��2015-10-15 

**OptiMOS[ª] ��5�Power-Transistor,�80�V** 

IPB015N08N5 

**==> picture [146 x 65] intentionally omitted <==**

**2�����Maximum�ratings** at� _T_ A=25�°C,�unless�otherwise�specified 

## **Table�2�����Maximum�ratings** 

|**Table2Maximumratings**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**||**Values**||**Unit**|**Note/TestCondition**|
|||**Min.**|**Typ.**|**Max.**|||
|Continuous drain current|_I_D|-<br>-|-<br>-|180<br>180|A|_T_C=25°C<br>_T_C=100°C|
|Pulsed drain current1)|_I_D,pulse|-|-|720|A|_T_C=25°C|
|Avalanche energy, single pulse2)|_E_AS|-|-|1230|mJ|_I_D=100A,_R_GS=25Ω|
|Gate source voltage|_V_GS|-20|-|20|V|-|
|Power dissipation|_P_tot|-|-|375|W|_T_C=25°C|
|Operating and storage temperature|_T_j,_T_stg|-55|-|175|°C|IEC climatic category;<br>DIN IEC 68-1: 55/175/56|



## **3�����Thermal�characteristics** 

## **Table�3�����Thermal�characteristics** 

|**Parameter**|**Symbol**||**Values**|**Values**|**Unit**|**Note/TestCondition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Thermal resistance,junction - case|_R_thJC|-|0.3|0.4|K/W|-|
|Thermal resistance, junction - ambient,<br>minimal footprint|_R_thJA|-|-|62|K/W|-|
|Thermal resistance, junction - ambient,<br>6 cm2cooling area3)|_R_thJA|-|-|40|K/W|-|
|Soldering temperature and reflow<br>soldering is allowed|_T_sold|-|-|260|°C|Reflow MSL1|



> 1) See Diagram 3 for more detailed information 

> 2) See Diagram 13 for more detailed information 

3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 

Final Data Sheet 

Rev.�2.1,��2015-10-15 

4 

**OptiMOS[ª] ��5�Power-Transistor,�80�V** 

IPB015N08N5 

**==> picture [146 x 65] intentionally omitted <==**

## **4�����Electrical�characteristics** 

## **Table�4�����Static�characteristics** 

|**Parameter**|**Symbol**||**Values**|**Values**|**Unit**|**Note/TestCondition**|
|---|---|---|---|---|---|---|
|||**Min.**|**Typ.**|**Max.**|||
|Drain-source breakdown voltage|_V_(BR)DSS|80|-|-|V|_V_GS=0V,_I_D=1mA|
|Gate threshold voltage|_V_GS(th)|2.2|3|3.8|V|_V_DS=_V_GS,_I_D=279µA|
|Zero gate voltage drain current|_I_DSS|-<br>-|0.1<br>10|1<br>100|µA|_V_DS=80V,_V_GS=0V,_T_j=25°C<br>_V_DS=80V,_V_GS=0V,_T_j=125°C|
|Gate-source leakage current|_I_GSS|-|1|100|nA|_V_GS=20V,_V_DS=0V|
|Drain-source on-state resistance|_R_DS(on)|-<br>-|1.1<br>1.5|1.5<br>1.8|mΩ|_V_GS=10V,_I_D=100A<br>_V_GS=6V,_I_D=50A|
|Gate resistance1)|_R_G|-|1.5|2.3|Ω|-|
|Transconductance|_g_fs|123|245|-|S||_V_DS|>2|_I_D|_R_DS(on)max,_I_D=100A|
|**Table5Dynamiccharacteristics1)**|||||||
|**Parameter**|**Symbol**||**Values**||**Unit**|**Note/TestCondition**|
|||**Min.**|**Typ.**|**Max.**|||
|Input capacitance|_C_iss|-|13000|16900|pF|_V_GS=0V,_V_DS=40V,_f_=1MHz|
|Output capacitance|_C_oss|-|2000|2600|pF|_V_GS=0V,_V_DS=40V,_f_=1MHz|
|Reverse transfer capacitance|_C_rss|-|86|150|pF|_V_GS=0V,_V_DS=40V,_f_=1MHz|
|Turn-on delay time|_t_d(on)|-|33|-|ns|_V_DD=40V,_V_GS=10V,_I_D=100A,<br>_R_G,ext=1.6Ω|
|Rise time|_t_r|-|32|-|ns|_V_DD=40V,_V_GS=10V,_I_D=100A,<br>_R_G,ext=1.6Ω|
|Turn-off delay time|_t_d(off)|-|83|-|ns|_V_DD=40V,_V_GS=10V,_I_D=100A,<br>_R_G,ext=1.6Ω|
|Fall time|_t_f|-|28|-|ns|_V_DD=40V,_V_GS=10V,_I_D=100A,<br>_R_G,ext=1.6Ω|
|**Table6Gatechargecharacteristics2)**|||||||
|**Parameter**|**Symbol**||**Values**||**Unit**|**Note/TestCondition**|
|||**Min.**|**Typ.**|**Max.**|||
|Gate to source charge|_Q_gs|-|56|-|nC|_V_DD=40V,_I_D=100A,_V_GS=0to10V|
|Gate to drain charge1)|_Q_gd|-|37|56|nC|_V_DD=40V,_I_D=100A,_V_GS=0to10V|
|Switchingcharge|_Q_sw|-|58|-|nC|_V_DD=40V,_I_D=100A,_V_GS=0to10V|
|Gate charge total1)|_Q_g|-|178|222|nC|_V_DD=40V,_I_D=100A,_V_GS=0to10V|
|Gate plateau voltage|_V_plateau|-|4.5|-|V|_V_DD=40V,_I_D=100A,_V_GS=0to10V|
|Gate charge total, sync. FET|_Q_g(sync)|-|153|-|nC|_V_DS=0.1V,_V_GS=0to10V|
|Output charge1)|_Q_oss|-|207|276|nC|_V_DD=40V,_V_GS=0V|



> 1) Defined by design. Not subject to production test. 

> 2) See ″ Gate charge waveforms ″ for parameter definition Final Data Sheet 

Rev.�2.1,��2015-10-15 

5 

**OptiMOS[ª] ��5�Power-Transistor,�80�V** 

IPB015N08N5 

**==> picture [146 x 65] intentionally omitted <==**

## **Table�7�����Reverse�diode** 

|**Table7Reversediode**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**||**Values**||**Unit**|**Note/TestCondition**|
|||**Min.**|**Typ.**|**Max.**|||
|Diode continous forward current|_I_S|-|-|180|A|_T_C=25°C|
|Diode pulse current|_I_S,pulse|-|-|720|A|_T_C=25°C|
|Diode forward voltage|_V_SD|-|0.86|1.2|V|_V_GS=0V,_I_F=100A,_T_j=25°C|
|Reverse recoverytime1)|_t_rr|-|94|188|ns|_V_R=40V,_I_F=100A,d_i_F/d_t_=100A/µs|
|Reverse recoverycharge1)|_Q_rr|-|246|492|nC|_V_R=40V,_I_F=100A,d_i_F/d_t_=100A/µs|



1) Defined by design. Not subject to production test. Final Data Sheet 

6 

Rev.�2.1,��2015-10-15 

5 Power-Transistor, IPB015N08N5 80 V 

**OptiMOS[ª]** 

**==> picture [539 x 599] intentionally omitted <==**

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Final Data Sheet 

7 

5 Power-Transistor, IPB015N08N5 80 V 

## **OptiMOS[ª]** 

**==> picture [528 x 599] intentionally omitted <==**

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720 5<br>680 10 V 7 V 6 V 4.5 V 5 V 5.5 V<br>ee aEELE ELE<br>640<br>600<br>— 4 ELE<br>560 ft ff ELE ELE<br>520 El EEE ELLE<br>480<br>5.5 V<br>440 SeAHRF CSS 3 ALLELE<br>400<br>= 360 SS| | O—— —— ALLE WLLL ELE.<br>320<br>280 SSee ee 2 |4EA)/ LL |<br>240 5 V 6 V<br>2 See<br>200 7 V<br>Oe oe 10 V<br>160<br>1<br>120 S| er<br>4.5 V<br>80 ———————— AL EELEEEL EEL E L E<br>40<br>0 _ASSSee ee es | 0 SL EELELEEL ELL EL ELL<br>0 1 2 3 4 5 0 50 100 150 200 250 300 350 400 450<br>V DS I D<br>[Vv] [A]<br>I D=f( V DS T j V GS R DS(on)=f( I D T j V GS<br>300 300<br>ee ee | | | | | pee<br>250 ee ee 250 {| | | | lee<br>|a| | | | fF | fT —[ | |pet|<br>200 200<br>a ee | | eA<br>Fa 150 | | eeee Po 150 —|tA tT ft tt<br>aeee ee lift| | | |<br>100 100<br>ee ie PA | | | ft<br>150 °C<br>ae 25 °C ee ‘f/f; | | | | | ff<br>50 50<br>| a ft | | | | ff<br>| | | fet; | | | ft ft ft<br>0 | LA |] | ff 0 P| | | | f ff<br>0 2 4 6 8 0 40 80 120 160<br>V GS I D<br>[Vv] [A]<br>I D=f( V GS V DS|>2| I D| R DS(on)max T j g fs=f( I D T j<br>] Ω<br>I D<br>DS(on)<br>R<br>I D fs g<br>**----- End of picture text -----**<br>


Final Data Sheet 

8 

5 Power-Transistor, IPB015N08N5 80 V 

## **OptiMOS[ª]** 

**==> picture [528 x 265] intentionally omitted <==**

**----- Start of picture text -----**<br>
4 4.0<br>CTT) 3.5 eee<br>3 PLETE 3.0 aeee 2790 µA<br>TT TELL) GRRE<br>279 µA<br>COCOA)ZO ASREFE R S<br>2.5 NN<br>- ELtttit NIA<br>2 ERA: [ra] ee 2.0 I<br>max<br>Pf] |aneopeet aLe) 1.5 Pteett ty | | rt tT |eeeUNE<br>typ<br>1 eee| — 1.0 FtFt |tT || || || dTdt dvcE tttT | TttT<br>0.5<br>PECEEECTC) |) ReERREERRFt EE<br>CCCCECCE)) tT | tt tr ET<br>0 0.0 PF ttt tt | ct dt dt ft<br>-60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180<br>| BeEEEEEE REE<br>T j [°C] T j [°C]<br>R DS(on)=f( T j I D V GS V GS(th)=f( T j V GS= V DS I D<br>] Ω<br> [m<br>GS(th)<br>DS(on) V<br>R<br>**----- End of picture text -----**<br>


**==> picture [527 x 266] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 [5] 10 [3]<br>a O 25 °C O<br>—— 175 °C SS SS<br>a ee eee eee 'i 25 °C, max eei)ee ee ea erred<br>175 °C, max<br>frre rr Ciss  rte rr EG | fAee ee2eee<br>10 [4]<br>10 [2]<br>aeeeeeeeeeaee | Li t<br>Coss<br>EEE ERASE EE EE ———————gl<br>10 [3]<br>pt==NT— ee eeI ee eeeee<br>10 [1]<br>SSNS UL<br>Crss<br>10 [2] | TAA =————<br>CECE Eee eis a<br>10 [1] 10 [0]<br>0 20 40 60 80 0.0 0.5 1.0 1.5 2.0<br>V DS V SD<br>[Vv] [Vv]<br>C =f( V DS V GS f I F=f( V SD T j<br>C I F<br>**----- End of picture text -----**<br>


Final Data Sheet 

9 

5 Power-Transistor, IPB015N08N5 80 V 

## **OptiMOS[ª]** 

**==> picture [528 x 266] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 [3] 10<br>a— ee eee ae<br>a ee V4<br>8<br>SoH | Le OZ<br>25 °C 40 V<br>10 [2] ||ee 6 $$} 4-4}ff/<br>100 °C<br>20 V 60 V<br>es ee ee) Ae<br>=x AAT) /<br>150 °C<br>eS Ban! 4 a eee<br>CAI CTT SI —<br>10 [1] a<br>ee<br>eePT ee el Ann<br>2<br>HEE | CZ<br>10 [0] 0<br>10 [0] 10 [1] 10 [2] 10 [3] 0 50 100 150 200<br>t AV [us] Q gate [nC]<br>I AS=f( t AV R GS Ω T j(start) V GS=f( Q gate I D V DD<br>I AV V GS<br>**----- End of picture text -----**<br>


OT Gate charge waveforms 

**==> picture [259 x 265] intentionally omitted <==**

**----- Start of picture text -----**<br>
90 | ft | | ct<br>| ft | | | cP<br>| ot | | ht hc<br>| ot | ht ct rE<br>85 P| | | | | |<br>|| ot | | hEree<br>| ot | || hE| hd htre<br>sns [|_| | | |) tw | |<br>80 | | | lupeET<br>| | det<br>paw | | | | hvd| hE ht TT<br>Tt | | tr<br>75 | ft | | hE hc<br>| | | | hE hc<br>| ot | ct ct<br>| ot | | ht hc<br>70<br>a<br>-60 -20 20 60 100 140 180<br>T j [°C]<br>V BR(DSS)=f( T j I D<br>BR(DSS)<br>V<br>**----- End of picture text -----**<br>


Final Data Sheet 

10 

**OptiMOS[ª]** 

5 Power-Transistor, IPB015N08N5 80 V 

Final Data Sheet 

11 

5 Power-Transistor, IPB015N08N5 80 V 

IPB015N08N5 

## **OptiMOS[ª]** 

IPB015N08N5 

|Previous Revision|Previous Revision||
|---|---|---|
|Revision|Date|Subjects (major changes since last revision)|
|2.0|2014-12-11|Release of final version|
|2.1|2015-10-15|Update package Outline|



## **erratum@infineon.com** 

## **Information** 

**www.infineon.com** ). 

## **Warnings** 

Final Data Sheet 

12 



## Links

- [View this product on Novapart](https://novapart.co/products/IPB015N08N5ATMA1/power-mosfet-n-channel-80-v-180-a-1100-ohm-to-263)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/infineon/ipb015n08n5atma1/mosfet-n-ch-80v-180a-to-263/dp/2725833RL)
---

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