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ICM-20648
MEMS Module, MotionTracking Series, 3-Axis Gyroscope/Accelerometer, ±16g, 1.71 V to 3.6 V, QFN-24
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: TDK INVENSENSE
- Product type: MEMS Modules
- MEMS Module Function:Tri-Axis Gyroscope, Tri-Axis Accelerometer; Supply Voltage Min:1.71V; Supply Voltage Max:3.6V; Sensor Case Style:QFN; N; Available until stocks are exhausted
- MSL: MSL 3 - 168 hours
- SVHC: No SVHC (15-Jun-2015)
- No. of Pins: 24Pins
- Sensor Type: Accelerometer, Gyroscope
- Sensing Axis: X, Y, Z
- Product Range: -
- Output Interface: I2C, SPI
- Sensor Case Style: QFN
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 1.71V
- MEMS Module Function: Tri-Axis Gyroscope, Tri-Axis Accelerometer
- Sensor Case / Package: QFN
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- Sensing Range - Gyroscope: ± 250°/s, ± 500°/s, ± 1000°/s, ± 2000°/s
- Temperature Sensing Range: -
- Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g, ± 16g
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 2.55 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
_**ICM-20648**_
## 6-Axis MEMS MotionTracking™ Device with Enhanced EIS Support and Sensor Fusion Processing
## **GENERAL DESCRIPTION**
The ICM-20648 is a 6-axis MotionTracking device that is ideally suited for Smartphones, Tablets, Wearable Sensors, and general IoT applications.
- 3-axis gyroscope, 3-axis accelerometer, and a Digital Motion Processor™ (DMP[TM] ) in a 3x3x0.9mm (24-pin QFN) package
- Step Count, Activity Classifier, and B2S (Bring-to-See) Gesture tuned for Wrist Worn Wearable Applications
- DMP offloads computation of motion processing algorithms from the host processor, improving system power performance
- Software drivers are fully compliant with Google’s latest Android release
- Enhanced FSYNC functionality to improve timing for applications like EIS
ICM-20648 supports an auxiliary I[2] C interface to external sensors, on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features an operating voltage range down to 1.71V. Communication ports include I[2] C and high speed SPI at 7 MHz.
## **APPLICATIONS**
- Wearable Devices
- Smartphones and Tablets
- IoT Applications
- Motion-based game controllers
- 3D remote controls for Internet connected DTVs and set top boxes, 3D mice
## **FEATURES**
- 3-Axis Gyroscope with Programmable FSR of ±250dps, ±500dps, ±1000dps and ±2000dps
- 3-Axis Accelerometer with Programmable FSR of
- ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_
- Onboard Digital Motion Processor (DMP)
- Android support
- SW features supported in DMP
- Bring to See
- Step Counter
- Step Detector
- Activity Classifier (walk, run, bike, still)
- Calibration: Accel Bias, Compass Cal, Gyro Cal
- Game Rotation Vector
- Significant Motion
- Pick up
- Rotation Vector (with Aux compass)
## **ORDERING INFORMATION**
|**PART**|**TEMP RANGE**|**PACKAGE**|
|---|---|---|
|ICM-20648†|−40°C to +85°C|24-Pin QFN|
†Denotes RoHS and Green-Compliant Package
- GeoMagnetic Rotation Vector (with Aux compass)
- Linear Acceleration
- Gravity
- Orientation
## **TYPICAL OPERATING CIRCUIT**
**==> picture [194 x 176] intentionally omitted <==**
**----- Start of picture text -----**<br>
nCS<br>SCLK<br>SDI<br>NC 1 18 GND<br>NC 2 17 NC<br>NC 3 ICM-20648 16 NC<br>NC 4 15 NC<br>NC 5 14 NC<br>NC 6 13 VDD 1.71 – 3.6VDC<br>C2, 0.1 µF<br>1.71 – 3.6VDC<br>C3, 0.1 µ F 1, C1, 0.1 µF<br>SDO<br>|<br>SDA / SDI SCL / SCLK nCS AUX_DA RESV INT2<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>AUX_CL VDDIO SDO / AD0 REGOUT FSYNC INT1<br>**----- End of picture text -----**<br>
- Tilt
- Auxiliary I[2] C interface for external sensors
- On-Chip 16-bit ADCs and Programmable Filters
- 7 MHz SPI or 400 kHz Fast Mode I²C
- Digital-output temperature sensor
- VDD operating range of 1.71V to 3.6V
- MEMS structure hermetically sealed and bonded at wafer level
- RoHS and Green compliant
## **BLOCK DIAGRAM**
**TDK Corporation** 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 www.invensense.com
InvenSense reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Document Number: DS-000179 Revision: 1.2 Revision Date: 10/23/2017
_**ICM-20648**_
## **TABLE OF CONTENTS**
||General Description ............................................................................................................................................. 1|General Description ............................................................................................................................................. 1|
|---|---|---|
||Ordering Information ........................................................................................................................................... 1||
||Typical Operating Circuit ...................................................................................................................................... 1||
||Applications ......................................................................................................................................................... 1||
||Features ............................................................................................................................................................... 1||
||Block Diagram ...................................................................................................................................................... 1|Block Diagram ...................................................................................................................................................... 1|
|1|Introduction ......................................................................................................................................................... 9||
||1.1|Purpose and Scope .................................................................................................................................... 9|
||1.2|Product Overview...................................................................................................................................... 9|
||1.3|Applications ............................................................................................................................................... 9|
|2|Features ............................................................................................................................................................. 10||
||2.1|Gyroscope Features ................................................................................................................................ 10|
||2.2|Accelerometer Features .......................................................................................................................... 10|
||2.3|DMP Features .......................................................................................................................................... 10|
||2.4|Additional Features ................................................................................................................................. 10|
|3|Electrical Characteristics .................................................................................................................................... 11||
||3.1|Gyroscope Specifications ........................................................................................................................ 11|
||3.2|Accelerometer Specifications .................................................................................................................. 12|
||3.3|Electrical Specifications ........................................................................................................................... 13|
||3.4|I2C Timing Characterization ..................................................................................................................... 16|
||3.5|SPI Timing Characterization .................................................................................................................... 17|
||3.6|Absolute Maximum Ratings .................................................................................................................... 17|
|4|Applications Information ................................................................................................................................... 19||
||4.1|Pin Out Diagram and Signal Description ................................................................................................. 19|
||4.2|Typical Operating Circuit ......................................................................................................................... 20|
||4.3|Bill of Materials for External Components .............................................................................................. 20|
||4.4|Block Diagram ......................................................................................................................................... 21|
||4.5|Overview ................................................................................................................................................. 21|
||4.6|Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 22|
||4.7|Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning ......................................... 22|
||4.8|Digital Motion Processor ......................................................................................................................... 22|
||4.9|Primary I2C and SPI Serial Communications Interfaces ........................................................................... 22|
||4.10|Auxiliary I2C Serial Interface ................................................................................................................ 24|
||4.11|Self-Test .............................................................................................................................................. 24|
||4.12|Clocking ............................................................................................................................................... 25|
||4.13|Sensor Data Registers ......................................................................................................................... 25|
||4.14|FIFO ..................................................................................................................................................... 25|
||4.15|FSYNC .................................................................................................................................................. 25|
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_**ICM-20648**_
|‘TDK|‘TDK|<br>**_ICM-20648_**<br>‘TDK InvenSense|
|---|---|---|
||4.16|Interrupts ............................................................................................................................................ 25|
||4.17|Digital-Output Temperature Sensor ................................................................................................... 25|
||4.18|Bias and LDOs ..................................................................................................................................... 25|
||4.19|Charge Pump ...................................................................................................................................... 25|
||4.20|Standard Power Modes ...................................................................................................................... 26|
|5|Programmable Interrupts .................................................................................................................................. 27||
|6|Digital Interface ................................................................................................................................................. 28||
||6.1|I2C and SPI Serial Interfaces .................................................................................................................... 28|
||6.2|I2C Interface ............................................................................................................................................. 28|
||6.3|I2C Communications Protocol ................................................................................................................. 28|
||6.4|I2C Terms ................................................................................................................................................. 31|
||6.5|SPI Interface ............................................................................................................................................ 31|
|7|Orientation of Axes ............................................................................................................................................ 33||
||7.1|ICM-20648 Supported Interfaces ............................................................................................................ 33|
|8|Package Dimensions .......................................................................................................................................... 34||
|9|Part Number Package Marking .......................................................................................................................... 36||
|10|Use Notes ........................................................................................................................................................... 37||
||10.1|Gyroscope Mode Transition ............................................................................................................... 37|
||10.2|Power Management 1 Register Setting .............................................................................................. 37|
||10.3|DMP Memory Access .......................................................................................................................... 37|
||10.4|Time Base Correction .......................................................................................................................... 37|
||10.5|I2C Master Clock Frequency ................................................................................................................ 37|
||10.6|Clocking ............................................................................................................................................... 37|
||10.7|LP_EN Bit-Field Usage ......................................................................................................................... 38|
||10.8|Register Access Using SPI Interface .................................................................................................... 38|
|11|Register Map ...................................................................................................................................................... 39||
||11.1|User Bank 0 Register Map................................................................................................................... 39|
||11.2|User Bank 1 Register Map................................................................................................................... 40|
||11.3|User Bank 2 Register Map................................................................................................................... 40|
||11.4|User Bank 3 Register Map................................................................................................................... 41|
|12|USR Bank 0 Register Map – Descriptions ........................................................................................................... 42||
||12.1|WHO_AM_I ......................................................................................................................................... 42|
||12.2|USER_CTRL .......................................................................................................................................... 42|
||12.3|LP_CONFIG .......................................................................................................................................... 43|
||12.4|PWR_MGMT_1 ................................................................................................................................... 43|
||12.5|PWR_MGMT_2 ................................................................................................................................... 44|
||12.6|INT_PIN_CFG....................................................................................................................................... 44|
||12.7|INT_ENABLE ........................................................................................................................................ 45|
||12.8|INT_ENABLE_1 .................................................................................................................................... 45|
||12.9|INT_ENABLE_2 .................................................................................................................................... 46|
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_**ICM-20648**_
|‘TDK|<br>**_ICM-20648_**<br>‘TDK InvenSense|
|---|---|
|12.10|INT_ENABLE_3 .................................................................................................................................... 46|
|12.11|I2C_MST_STATUS ............................................................................................................................... 46|
|12.12|INT_STATUS ........................................................................................................................................ 47|
|12.13|INT_STATUS_1 .................................................................................................................................... 47|
|12.14|INT_STATUS_2 .................................................................................................................................... 47|
|12.15|INT_STATUS_3 .................................................................................................................................... 47|
|12.16|DELAY_TIMEH ..................................................................................................................................... 48|
|12.17|DELAY_TIMEL ...................................................................................................................................... 48|
|12.18|ACCEL_XOUT_H .................................................................................................................................. 48|
|12.19|ACCEL_XOUT_L ................................................................................................................................... 48|
|12.20|ACCEL_YOUT_H .................................................................................................................................. 49|
|12.21|ACCEL_YOUT_L ................................................................................................................................... 49|
|12.22|ACCEL_ZOUT_H................................................................................................................................... 49|
|12.23|ACCEL_ZOUT_L ................................................................................................................................... 49|
|12.24|GYRO_XOUT_H ................................................................................................................................... 49|
|12.25|GYRO_XOUT_L .................................................................................................................................... 50|
|12.26|GYRO_YOUT_H ................................................................................................................................... 50|
|12.27|GYRO_YOUT_L .................................................................................................................................... 50|
|12.28|GYRO_ZOUT_H ................................................................................................................................... 50|
|12.29|GYRO_ZOUT_L .................................................................................................................................... 51|
|12.30|TEMP_OUT_H ..................................................................................................................................... 51|
|12.31|TEMP_OUT_L ...................................................................................................................................... 51|
|12.32|EXT_SLV_SENS_DATA_00 ................................................................................................................... 51|
|12.33|EXT_SLV_SENS_DATA_01 ................................................................................................................... 52|
|12.34|EXT_SLV_SENS_DATA_02 ................................................................................................................... 52|
|12.35|EXT_SLV_SENS_DATA_03 ................................................................................................................... 52|
|12.36|EXT_SLV_SENS_DATA_04 ................................................................................................................... 52|
|12.37|EXT_SLV_SENS_DATA_05 ................................................................................................................... 52|
|12.38|EXT_SLV_SENS_DATA_06 ................................................................................................................... 53|
|12.39|EXT_SLV_SENS_DATA_07 ................................................................................................................... 53|
|12.40|EXT_SLV_SENS_DATA_08 ................................................................................................................... 53|
|12.41|EXT_SLV_SENS_DATA_09 ................................................................................................................... 53|
|12.42|EXT_SLV_SENS_DATA_10 ................................................................................................................... 53|
|12.43|EXT_SLV_SENS_DATA_11 ................................................................................................................... 54|
|12.44|EXT_SLV_SENS_DATA_12 ................................................................................................................... 54|
|12.45|EXT_SLV_SENS_DATA_13 ................................................................................................................... 54|
|12.46|EXT_SLV_SENS_DATA_14 ................................................................................................................... 54|
|12.47|EXT_SLV_SENS_DATA_15 ................................................................................................................... 54|
|12.48|EXT_SLV_SENS_DATA_16 ................................................................................................................... 55|
|12.49|EXT_SLV_SENS_DATA_17 ................................................................................................................... 55|
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_**ICM-20648**_
|‘TDK|‘TDK|<br>**_ICM-20648_**<br>‘TDK InvenSense|
|---|---|---|
||12.50|EXT_SLV_SENS_DATA_18 ................................................................................................................... 55|
||12.51|EXT_SLV_SENS_DATA_19 ................................................................................................................... 55|
||12.52|EXT_SLV_SENS_DATA_20 ................................................................................................................... 56|
||12.53|EXT_SLV_SENS_DATA_21 ................................................................................................................... 56|
||12.54|EXT_SLV_SENS_DATA_22 ................................................................................................................... 56|
||12.55|EXT_SLV_SENS_DATA_23 ................................................................................................................... 56|
||12.56|FIFO_EN_1 .......................................................................................................................................... 57|
||12.57|FIFO_EN_2 .......................................................................................................................................... 57|
||12.58|FIFO_RST ............................................................................................................................................. 57|
||12.59|FIFO_MODE ........................................................................................................................................ 58|
||12.60|FIFO_COUNTH..................................................................................................................................... 58|
||12.61|FIFO_COUNTL ..................................................................................................................................... 58|
||12.62|FIFO_R_W ........................................................................................................................................... 58|
||12.63|DATA_RDY_STATUS ............................................................................................................................ 59|
||12.64|FIFO_CFG ............................................................................................................................................ 59|
||12.65|REG_BANK_SEL ................................................................................................................................... 59|
|13|USR Bank 1 Register Map – Descriptions ........................................................................................................... 60||
||13.1|SELF_TEST_X_GYRO ............................................................................................................................ 60|
||13.2|SELF_TEST_Y_GYRO ............................................................................................................................ 60|
||13.3|SELF_TEST_Z_GYRO ............................................................................................................................ 60|
||13.4|SELF_TEST_X_ACCEL ........................................................................................................................... 60|
||13.5|SELF_TEST_Y_ACCEL ........................................................................................................................... 61|
||13.6|SELF_TEST_Z_ACCEL ........................................................................................................................... 61|
||13.7|XA_OFFS_H ......................................................................................................................................... 61|
||13.8|XA_OFFS_L .......................................................................................................................................... 61|
||13.9|YA_OFFS_H ......................................................................................................................................... 61|
||13.10|YA_OFFS_L .......................................................................................................................................... 62|
||13.11|ZA_OFFS_H ......................................................................................................................................... 62|
||13.12|ZA_OFFS_L .......................................................................................................................................... 62|
||13.13|TIMEBASE_CORRECTION_PLL ............................................................................................................. 62|
||13.14|REG_BANK_SEL ................................................................................................................................... 62|
|14|USR Bank 2 Register Map – Descriptions ........................................................................................................... 63||
||14.1|GYRO_SMPLRT_DIV ............................................................................................................................ 63|
||14.2|GYRO_CONFIG_1 ................................................................................................................................ 63|
||14.3|GYRO_CONFIG_2 ................................................................................................................................ 64|
||14.4|XG_OFFS_USRH .................................................................................................................................. 65|
||14.5|XG_OFFS_USRL ................................................................................................................................... 65|
||14.6|YG_OFFS_USRH ................................................................................................................................... 65|
||14.7|YG_OFFS_USRL ................................................................................................................................... 65|
||14.8|ZG_OFFS_USRH ................................................................................................................................... 65|
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Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
|‘TDK|‘TDK|<br>**_ICM-20648_**<br>‘TDK InvenSense|
|---|---|---|
||14.9|ZG_OFFS_USRL ................................................................................................................................... 65|
||14.10|ODR_ALIGN_EN .................................................................................................................................. 66|
||14.11|ACCEL_SMPLRT_DIV_1 ....................................................................................................................... 66|
||14.12|ACCEL_SMPLRT_DIV_2 ....................................................................................................................... 66|
||14.13|ACCEL_INTEL_CTRL ............................................................................................................................. 67|
||14.14|ACCEL_WOM_THR .............................................................................................................................. 67|
||14.15|ACCEL_CONFIG ................................................................................................................................... 67|
||14.16|ACCEL_CONFIG_2 ............................................................................................................................... 68|
||14.17|FSYNC_CONFIG ................................................................................................................................... 69|
||14.18|TEMP_CONFIG .................................................................................................................................... 70|
||14.19|MOD_CTRL_USR ................................................................................................................................. 70|
||14.20|REG_BANK_SEL ................................................................................................................................... 70|
|15|USR Bank 3 Register Map – Descriptions ........................................................................................................... 71||
||15.1|I2C_MST_ODR_CONFIG ...................................................................................................................... 71|
||15.2|I2C_MST_CTRL .................................................................................................................................... 71|
||15.3|I2C_MST_DELAY_CTRL ........................................................................................................................ 72|
||15.4|I2C_SLV0_ADDR .................................................................................................................................. 72|
||15.5|I2C_SLV0_REG ..................................................................................................................................... 72|
||15.6|I2C_SLV0_CTRL ................................................................................................................................... 73|
||15.7|I2C_SLV0_DO ...................................................................................................................................... 73|
||15.8|I2C_SLV1_ADDR .................................................................................................................................. 73|
||15.9|I2C_SLV1_REG ..................................................................................................................................... 74|
||15.10|I2C_SLV1_CTRL ................................................................................................................................... 74|
||15.11|I2C_SLV1_DO ...................................................................................................................................... 75|
||15.12|I2C_SLV2_ADDR .................................................................................................................................. 75|
||15.13|I2C_SLV2_REG ..................................................................................................................................... 75|
||15.14|I2C_SLV2_CTRL ................................................................................................................................... 76|
||15.15|I2C_SLV2_DO ...................................................................................................................................... 76|
||15.16|I2C_SLV3_ADDR .................................................................................................................................. 76|
||15.17|I2C_SLV3_REG ..................................................................................................................................... 77|
||15.18|I2C_SLV3_CTRL ................................................................................................................................... 77|
||15.19|I2C_SLV3_DO ...................................................................................................................................... 77|
||15.20|I2C_SLV4_ADDR .................................................................................................................................. 78|
||15.21|I2C_SLV4_REG ..................................................................................................................................... 78|
||15.22|I2C_SLV4_CTRL ................................................................................................................................... 78|
||15.23|I2C_SLV4_DO ...................................................................................................................................... 78|
||15.24|I2C_SLV4_DI ........................................................................................................................................ 79|
||15.25|REG_BANK_SEL ................................................................................................................................... 79|
|16|Reference ........................................................................................................................................................... 80||
|17|Revision History ................................................................................................................................................. 81|Revision History ................................................................................................................................................. 81|
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Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## **LIST OF FIGURES**
**==> picture [540 x 181] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||
|---|---|---|
|Figure 1. I|[2]|C Bus Timing Diagram ............................................................................................................................................................. 17|
|Figure 2. SPI Bus Timing Diagram ............................................................................................................................................................. 17|
|Figure 3. Pin out Diagram for ICM-20648 3.0 mm x 3.0 mm x 9 mm QFN ............................................................................................... 19|
|Figure 4. ICM-20648 I|[2]|C Application Schematic ....................................................................................................................................... 20|
|Figure 5. ICM-20648 SPI Application Schematic ...................................................................................................................................... 20|
|Figure 6. ICM-20648 Block Diagram ......................................................................................................................................................... 21|
|Figure 7. ICM-20648 Solution Using I|[2]|C Interface .................................................................................................................................... 23|
|Figure 8. ICM-20648 Solution Using SPI Interface ................................................................................................................................... 24|
|Figure 9. START and STOP Conditions ...................................................................................................................................................... 28|
|Figure 10. Acknowledge on the I|[2]|C Bus ................................................................................................................................................... 29|
|Figure 11. Complete I|[2]|C Data Transfer ..................................................................................................................................................... 30|
|Figure. 12 Typical SPI Master / Slave Configuration ................................................................................................................................ 32|
|Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................................... 33|
|Figure 14. Package Dimensions................................................................................................................................................................ 34|
|Figure 15. Part Number Package Marking ............................................................................................................................................... 36|
**----- End of picture text -----**<br>
Page 7 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## **LIST OF TABLES**
|**LIST OF TABLES**|**LIST OF TABLES**|
|---|---|
|Table 1. Gyroscope Specifications ........................................................................................................................................................... 11|Table 1. Gyroscope Specifications ........................................................................................................................................................... 11|
|Table 2. Accelerometer Specifications ..................................................................................................................................................... 12|Table 2. Accelerometer Specifications ..................................................................................................................................................... 12|
|Table 3. D.C. Electrical Characteristics ..................................................................................................................................................... 13|Table 3. D.C. Electrical Characteristics ..................................................................................................................................................... 13|
|Table 4. Gyroscope Noise and Current Consumption .............................................................................................................................. 14|Table 4. Gyroscope Noise and Current Consumption .............................................................................................................................. 14|
|Table 5. Accelerometer Noise and Current Consumption ....................................................................................................................... 14|Table 5. Accelerometer Noise and Current Consumption ....................................................................................................................... 14|
|Table 6. A.C. Electrical Characteristics ..................................................................................................................................................... 16|Table 6. A.C. Electrical Characteristics ..................................................................................................................................................... 16|
|Table 7. Other Electrical Specifications .................................................................................................................................................... 16|Table 7. Other Electrical Specifications .................................................................................................................................................... 16|
|Table 8. I|Table 8. I2C Timing Characteristics ........................................................................................................................................................... 16|
|Table 9. SPI Timing Characteristics (7MHz) .............................................................................................................................................. 17|Table 9. SPI Timing Characteristics (7MHz) .............................................................................................................................................. 17|
|Table 10. Absolute Maximum Ratings ..................................................................................................................................................... 18|Table 10. Absolute Maximum Ratings ..................................................................................................................................................... 18|
|Table 11. Signal Descriptions ................................................................................................................................................................... 19|Table 11. Signal Descriptions ................................................................................................................................................................... 19|
|Table 12. Bill of Materials ........................................................................................................................................................................ 20|Table 12. Bill of Materials ........................................................................................................................................................................ 20|
|Table 13. Standard Power Modes for ICM-20648.................................................................................................................................... 26|Table 13. Standard Power Modes for ICM-20648.................................................................................................................................... 26|
|Table 14. Table of Interrupt Sources ........................................................................................................................................................ 27|Table 14. Table of Interrupt Sources ........................................................................................................................................................ 27|
|Table 15. Serial Interface ......................................................................................................................................................................... 28|Table 15. Serial Interface ......................................................................................................................................................................... 28|
|Table 16. I|Table 16. I2C Terms .................................................................................................................................................................................. 31|
|Table 17. Package Dimensions Table ....................................................................................................................................................... 35|Table 17. Package Dimensions Table ....................................................................................................................................................... 35|
|Table 18. I|Table 18. I2C Master Clock Frequency ..................................................................................................................................................... 37|
Page 8 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## _**1 INTRODUCTION**_
## **1.1 PURPOSE AND SCOPE**
This document is a preliminary product specification, providing a description, specifications, and design related information on the ICM-20648 MotionTracking device.
Specifications are subject to change without notice. Final specifications will be updated based upon characterization of production silicon. For references to register map and descriptions of individual registers, please refer to the ICM-20648 Register Map and Register Descriptions document.
## **1.2 PRODUCT OVERVIEW**
The ICM-20648 is a MotionTracking device that combines a 3-axis gyroscope, 3-axis accelerometer, and a Digital Motion Processor™ (DMP) all in a small 3.0 mm x 3.0 mm x 0.9 mm QFN package. The device supports the following features:
- Android Lollipop support
- FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set)
- Runtime Calibration
- Enhanced FSYNC functionality to improve timing for applications like EIS
ICM-20648 devices, with their 6-axis integration, on-chip DMP, and run-time calibration firmware, enable manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices, guaranteeing optimal motion performance for consumers.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The accelerometer has a userprogrammable accelerometer full-scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ , and ±16 _g_ . Factory-calibrated initial sensitivity of both sensors reduces production-line calibration requirements.
Other key features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I[2] C and SPI serial interfaces, a VDD operating range of 1.71 to 3.6V, and a separate digital IO supply, VDDIO from 1.71V to 3.6V.
Communication with all registers of the device is performed using I[2] C at up to 100 kHz (standard-mode) or up to 400 kHz (fastmode), or SPI at up to 7 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, TDK-InvenSense has driven the package size down to a footprint and thickness of 3.0 mm x 3.0 mm x 0.9 mm (24-pin QFN), to provide a very small yet high performance, low cost package. The device provides high robustness by supporting 10,000 _g_ shock reliability.
## **1.3 APPLICATIONS**
- Mobile phones and tablets
- Portable gaming
- Motion-based game controllers
- 3D remote controls for Internet connected DTVs and set top boxes, 3D mice
- Wearable sensors for health, fitness and sports
Page 9 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## _**2 FEATURES**_
## **2.1 GYROSCOPE FEATURES**
The triple-axis MEMS gyroscope in the ICM-20648 includes the following features:
- Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±250, ±500, ±1000, and ±2000°/sec and integrated 16-bit ADCs
- User-selectable ODR; User-selectable low pass filters
- Self-test
## **2.2 ACCELEROMETER FEATURES**
The triple-axis MEMS accelerometer in ICM-20648 includes the following features:
- Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ and ±16 _g_ and integrated 16-bit ADCs
- User-selectable ODR; User-selectable low pass filters
- Wake-on-motion interrupt for low power operation of applications processor
- Self-test
## **2.3 DMP FEATURES**
The DMP in ICM-20648 includes the following capabilities:
- Offloads computation of motion processing algorithms from the host processor. The DMP can be used to minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host processor for use in applications.
- Optimized for Android Lollipop for low power features (AP suspended) including SMD, Step Count, Step Detect, Activity Classification, Rotation Vector, and Gaming Rotation Vector
- Optimized for Android Lollipop batching, both while the AP is active and suspended. The DMP will also batch data from externally connected sensors such as a compass, or pressure sensor.
- The DMP enables ultra-low power run-time and background calibration of the accelerometer, gyroscope, and compass, maintaining optimal performance of the sensor data for both physical and virtual sensors generated through sensor fusion. This enables the best user experience for all sensor enabled applications for the lifetime of the device.
- DMP features simplify the software architecture resulting in quicker time to market.
- DMP features are OS, Platform, and Architecture independent, supporting virtually any AP, MCU, or other embedded architecture.
## **2.4 ADDITIONAL FEATURES**
The ICM-20648 includes the following additional features:
- I[2] C at up to 100 kHz (standard-mode) or up to 400 kHz (fast-mode) or SPI at up to 7 MHz for communication with registers
- Auxiliary master I[2] C bus for reading data from external sensors (e.g. magnetometer)
- Digital-output temperature sensor
- 10,000 _g_ shock tolerant
- MEMS structure hermetically sealed and bonded at wafer level
- RoHS and Green compliant
Page 10 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## _**3 ELECTRICAL CHARACTERISTICS**_
## **3.1 GYROSCOPE SPECIFICATIONS**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
All specifications apply to Low-Power and Low-Noise Mode, unless otherwise noted.
|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**GYROSCOPE SENSITIVITY**<br>~~GO~~|||||||
|Full-Scale Range<br>~~sn~~|GYRO_FS_SEL=0<br>~~sn~~|~~sn~~|±250<br>~~sn~~<br>~~GO~~<br>~~GO~~|~~sn~~<br>~~GO~~<br>~~Gs~~|dps<br>~~sn~~<br>~~(~~|1<br>~~sn~~|
|~~QO~~|GYRO_FS_SEL=1<br>~~QO~~|~~QO~~|±500<br>~~GO~~<br>~~QO~~<br>~~GO~~<br>~~GG~~|~~GO~~<br>~~QO~~<br>~~Gs~~<br>~~GG~~|dps<br>~~QO~~<br>~~(~~|1<br>~~QO~~|
|~~QO~~|GYRO_FS_SEL=2<br>~~QO~~<br>~~QO~~|~~QO~~<br>~~QO~~|±1000<br>~~GO ~~<br>~~QO~~<br>~~GG~~<br>~~GQ~~|~~Gs~~<br>~~QO~~<br>~~GG~~<br>~~GQ~~|dps<br>~~(~~<br>~~QO~~|1<br>~~QO~~|
|~~re~~|GYRO_FS_SEL=3<br>~~re~~<br>~~QO~~<br>~~nr~~|~~re~~<br>~~QO~~|±2000<br>~~GG~~<br>~~re~~<br>~~GQ~~|~~GG~~<br>~~re~~<br>~~GQ~~|dps<br>~~re~~|1<br>~~re~~|
|Gyroscope ADC Word Length<br>~~es~~|~~QO~~<br>~~es~~<br>~~nr~~<br>~~nr~~|~~QO ~~<br>~~es~~|16<br> ~~GQ~~<br>~~es~~|~~GQ~~<br>~~es~~|bits<br>~~es~~|1<br>~~es~~|
|SensitivityScale Factor<br>~~es~~|GYRO_FS_SEL=0<br>~~nr~~<br>~~es~~<br>~~nr~~|~~es~~|131<br>~~es~~<br>~~GO~~|~~es~~<br>~~GO~~|LSB/(dps)<br>~~es~~<br>~~(~~|1<br>~~es~~|
|~~OO~~|GYRO_FS_SEL=1<br>~~nr~~<br>~~OO~~|~~OO~~|65.5<br>~~OO~~<br>~~GO~~<br>~~GG~~|~~OO~~<br>~~GO~~<br>~~GG~~|LSB/(dps)<br>~~OO~~<br>~~(~~<br>~~GO~~|1<br>~~OO~~|
|~~QO~~|GYRO_FS_SEL=2<br>~~QO~~<br>~~QO~~|~~QO~~<br>~~QO~~|32.8<br>~~GO~~<br>~~QO~~<br>~~GG~~<br>~~GQ~~|~~GO ~~<br>~~QO~~<br>~~GG~~<br>~~GQ~~|LSB/(dps)<br> ~~(~~<br>~~QO~~<br>~~GO~~|1<br>~~QO~~|
|~~QO~~<br>~~ee~~|GYRO_FS_SEL=3<br>~~QO~~<br>~~ee~~<br>~~QO~~<br>~~nr~~|~~QO~~<br>~~ee~~<br>~~QO~~|16.4<br>~~QO~~<br>~~GG~~<br>~~ee~~<br>~~GQ~~|~~QO~~<br>~~GG~~<br>~~ee~~<br>~~GQ~~|LSB/(dps)<br>~~QO~~<br>~~GO~~<br>~~ee~~|1<br>~~QO~~<br>~~ee~~|
|SensitivityScale Factor Tolerance<br>~~es~~|25°C<br>~~QO~~<br>~~es~~<br>~~nr~~<br>~~ee~~|~~QO ~~<br>~~es~~<br>~~ee~~|±1.5<br> ~~GQ~~<br>~~es~~<br>~~ee~~|~~GQ~~<br>~~es~~<br>~~ee~~|%<br>~~es~~<br>~~ee~~|2<br>~~es~~|
|Sensitivity Scale Factor Variation Over<br>Temperature<br>~~a~~|-40°C to +85°C<br>~~nr~~<br>~~a~~<br>~~ee~~<br>~~nr~~|~~a~~<br>~~ee~~|±3<br>~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|%<br>~~a~~<br>~~ee~~|2<br>~~a~~|
|Nonlinearity<br>~~es~~|Best fit straight line; 25°C<br>~~ee ~~<br>~~es~~<br>~~nr~~<br>~~QO~~|~~ee ~~<br>~~es~~<br>~~QO~~|±0.1<br> ~~ee ~~<br>~~es~~<br>~~Qs~~|~~ee ~~<br>~~es~~<br>~~(ees OR~~|%<br> ~~ee~~<br>~~es~~<br>~~OR~~|2, 3<br>~~es~~|
|Cross-Axis Sensitivity<br>~~re~~|~~nr~~<br>~~re~~<br>~~QO~~|~~re~~<br>~~QO~~|±2<br>~~re~~<br>~~Qs~~|~~re~~<br>~~(ees OR~~|%<br>~~re~~<br>~~OR~~|2, 3<br>~~re~~|
|**ZERO-RATE OUTPUT(ZRO)**<br>~~re~~<br>~~QO Qs(ees OR~~<br>~~QO(GO~~|||||||
|Initial ZRO Tolerance<br>~~QO~~|25°C(Component-level)<br>~~QO~~<br>~~rr~~|~~QO~~<br>~~QO~~|±5<br>~~QO~~<br>~~QO~~<br>~~Gees~~|~~QO~~<br>~~(GO~~<br>~~(ees~~|dps<br>~~QO~~<br>~~(GO~~<br>~~OU~~|2<br>~~QO~~|
|ZRO Variation Over Temperature<br>~~QO~~<br>~~re~~|-40°C to +85°C<br>~~QO~~<br>~~re~~<br>~~rr~~|~~QO~~<br>~~re~~<br>~~QO~~|±0.05<br>~~QO~~<br>~~QO ~~<br>~~re~~<br>~~Gees~~|~~QO~~<br> ~~(GO~~<br>~~re~~<br>~~(ees~~|dps/°C<br>~~QO~~<br>~~(GO~~<br>~~re~~<br>~~OU~~|2<br>~~QO~~<br>~~re~~|
|**GYROSCOPE NOISE PERFORMANCE(FS_SEL=0)**<br>~~re~~<br>~~rr~~<br>~~QO~~<br>~~Gees(eesOU~~<br>~~QOGG~~|||||||
|Noise Spectral Density<br>~~OO~~|Based on Noise Bandwidth = 10Hz<br>~~OO~~<br>~~DQ~~|~~OO~~<br>~~DQ~~|0.015<br>~~OO~~<br>~~QO~~<br>~~GG~~|~~OO~~<br>~~GG~~<br>~~GG~~|dps/√Hz<br>~~OO~~<br>~~GG~~<br>~~(~~|2<br>~~OO~~|
|Gyroscope Mechanical Frequencies<br>~~OO~~<br>~~re~~|~~OO~~<br>~~re~~<br>~~DQ~~<br>~~nr~~|25<br>~~OO~~<br>~~re~~<br>~~DQ~~|27<br>~~OO~~<br>~~QO ~~<br>~~re~~<br>~~GG~~|29<br>~~OO~~<br> ~~GG~~<br>~~re~~<br>~~GG~~|kHz<br>~~OO~~<br>~~GG~~<br>~~re~~<br>~~(~~|2<br>~~OO~~<br>~~re~~|
|Low Pass Filter Response<br>~~es~~<br>~~Oo~~|Programmable Range<br>~~DQ~~<br>~~es~~<br>~~nr~~|5.7<br>~~DQ ~~<br>~~es~~|~~GG~~<br>~~es~~|197<br>~~GG ~~<br>~~es~~<br>~~QO~~|Hz<br> ~~(~~<br>~~es~~<br>~~QO~~|1, 3<br>~~es~~<br>~~_~~|
|Gyroscope Start-UpTime<br>~~GG~~<br>~~Oo~~|From Full-ChipSleepmode<br>~~nr~~<br>~~GG~~|~~GG~~|35<br>~~GG~~|~~GG~~<br>~~QO~~|ms<br>~~GG~~<br>~~QO~~|2,3<br>~~GG~~<br>~~_~~|
|Output Data Rate<br>~~Oo~~|Low-Power Mode|4.4||562.5<br>~~QO~~|Hz<br>~~QO~~|1<br>~~_~~|
||Low-Noise Mode<br>GYRO_FCHOICE=1;GYRO_DLPFCFG=x|4.4<br>~~ee~~|~~ee~~|1.125k<br>~~QO~~|Hz<br>~~QO~~||
||Low-Noise Mode<br>GYRO_FCHOICE=0;GYRO_DLPFCFG=x<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|9k<br>~~QO~~<br>~~ee~~|Hz<br>~~QO~~<br>~~ee~~||
**Notes** :
1. Guaranteed by design 2. Derived from validation or characterization of parts, not guaranteed in production 3. Low-noise mode specification
Page 11 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## **3.2 ACCELEROMETER SPECIFICATIONS**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
All specifications apply to Low-Power and Low-Noise Mode, unless otherwise noted.
|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**ACCELEROMETER SENSITIVITY**<br>~~rs~~<br>~~es es~~|||||||
|Full-Scale Range<br>~~i~~<br>~~I~~|ACCEL_FS=0<br>~~rs~~|~~rs~~<br>~~rs~~<br>~~r~~~~**s** rs~~|±2<br>~~rs~~<br>~~es es~~<br>~~rs es~~|~~rs~~<br>~~es~~<br>~~es~~|_g_<br>~~rs~~|1<br>~~rs~~|
||ACCEL_FS=1<br>~~re~~|~~rs~~<br>~~re~~<br>~~r~~~~**s** rs~~|±4<br>~~es es~~<br>~~re~~<br>~~rs es~~|~~es~~<br>~~re~~<br>~~es~~|_g_<br>~~re~~|1<br>~~re~~|
||ACCEL_FS=2<br>~~eee~~<br>|~~r~~~~**s** rs~~<br>~~eee~~<br>~~rr~~|±8<br>~~rs es~~<br>~~eee~~<br>~~rs~~|~~es~~<br>~~eee~~|_g_<br>~~eee~~|1<br>~~eee~~|
||ACCEL_FS=3<br>~~eee~~<br>~~r~~|~~r~~~~**s** rs~~<br>~~eee~~<br>~~rrr~~|±16<br>~~rs es~~<br>~~eee~~<br>~~rs~~|~~es~~<br>~~eee~~|_g_<br>~~eee~~|1<br>~~eee~~|
|ADC Word Length<br>~~I~~<br>~~Oo~~|Output in two’s complement format<br><br>~~**r**~~|~~rr~~<br>~~**r**e~~|16<br>~~rs~~<br>~~e~~|~~e~~|bits<br>~~e~~|1<br>~~e~~|
|Sensitivity Scale Factor<br>~~I~~<br>~~Oo~~|ACCEL_FS=0<br><br>~~**r**~~|~~rr ~~<br>~~**r**e~~<br>~~rs~~|16,384<br> ~~rs~~<br>~~e~~<br>~~rs~~|~~e~~<br>~~es~~|LSB/_g_<br>~~e~~|1<br>~~e~~|
||ACCEL_FS=1<br>~~**r**~~|~~**r**e~~<br>~~rs~~<br>~~ee~~|8,192<br>~~e~~<br>~~rs~~<br>~~rs~~|~~e~~<br>~~es~~<br>|LSB/_g_<br>~~e~~<br>|1<br>~~e~~<br>|
||ACCEL_FS=2<br>~~**r**~~<br>~~rs~~|~~**r**e~~<br>~~rs ~~<br>~~rs~~<br>~~ee~~<br>~~rs~~|4,096<br>~~e~~<br> ~~rs ~~<br>~~rs~~<br>~~rs~~<br>~~rs~~|~~e~~<br> ~~es~~<br>~~rs~~<br>|LSB/_g_<br>~~e~~<br>~~rs~~<br>|1<br>~~e~~<br>~~rs~~<br>|
||ACCEL_FS=3<br>~~**r**~~|~~**r**e~~<br>~~ee s~~<br>~~rs~~|2,048<br>~~e~~<br> ~~rss~~<br>~~rs~~|~~e~~<br>~~s~~|LSB/_g_<br>~~e~~<br>~~s~~|1<br>~~e~~<br>~~s~~|
|Initial Tolerance<br>~~Oo~~<br>~~sO~~<br>~~ee~~|Component-level<br>~~**r**~~<br>~~sO~~<br>~~es~~|~~**r**e~~<br>~~s~~<br>~~rs ~~<br>~~sO~~|±0.5<br>~~e~~<br>~~s~~<br> ~~rs~~<br>~~sO~~|~~e~~<br>~~s~~<br>~~sO~~|%<br>~~e~~<br>~~s~~<br>~~sO~~|2<br>~~e~~<br>~~s~~<br>~~sO~~|
|Sensitivity Change vs. Temperature<br>~~ee~~<br>~~rr~~|-40°C to +85°C ACCEL_FS=0<br>~~es~~<br>~~Qs~~|~~Qs~~|±0.026<br>~~Qs~~|~~Qs~~|%/ºC|2|
|Nonlinearity<br>~~ee ~~<br>~~rr~~<br>~~es~~|Best Fit Straight Line<br> ~~es~~<br>~~Qs~~<br>~~Genres~~|~~Qs~~<br>~~errs~~|±0.5<br>~~Qs~~<br>~~rr~~|~~Qs~~<br>~~rte~~|%<br>~~es~~|2, 3|
|Cross-Axis Sensitivity<br>~~rr~~<br>~~es~~|~~Qs~~<br>~~Genres~~|~~Qs~~<br>~~errs~~|±2<br>~~Qs~~<br>~~rr~~|~~Qs~~<br>~~rte~~|%<br>~~es~~|2, 3|
|**ZERO-G OUTPUT**<br>~~esGenres errs rr~~<br>~~rte~~<br>~~es~~<br>~~rs~~<br>~~GO(~~|||||||
|Initial Tolerance<br>~~rs~~|Component-level, all axes<br>~~GO~~|~~GO~~|±25<br>~~GO~~|~~(~~|m_g_|2|
|~~rs~~<br>~~Os~~<br>~~es errr~~|Board-level, all axes<br>~~GO~~<br>~~Os~~<br>~~errr~~|~~GO~~<br>~~Os~~<br>~~rd~~|±50<br>~~GO ~~<br>~~Os~~<br>~~ee~~|~~(~~<br>~~Os~~<br>~~es~~|m_g_<br>~~Os~~|2<br>~~Os~~|
|Zero-G Level Change vs. Temperature<br>~~Os~~<br>~~es errr~~|0°C to +85°C<br>~~Os~~<br>~~errr~~|~~Os~~<br>~~rd~~|±0.80<br>~~Os~~<br>~~ee~~|~~Os~~<br>~~es~~|m_g_/°C<br>~~Os~~|2<br>~~Os~~|
|**NOISE PERFORMANCE**<br>~~es errr~~<br>~~rd ee~~<br>~~es~~<br>~~en~~|||||||
|Noise Spectral Density<br>~~rs~~|Based on Noise Bandwidth = 10Hz<br>~~rs~~<br>~~en~~|~~rs~~|230<br>~~rs~~|~~rs~~|µ_g_/√Hz<br>~~rs~~|2<br>~~rs~~|
|Low Pass Filter Response<br>~~fe~~|Programmable Range<br>~~en~~<br>~~fe~~|5.7<br>~~fe~~|~~fe~~|246<br>~~fe~~|Hz<br>~~fe~~|1, 3<br>~~fe~~|
|Intelligence Function Increment<br>~~Os~~|~~Os~~|~~Os~~|32<br>~~Os~~|~~Os~~|m_g_/LSB<br>~~Os~~|1<br>~~Os~~|
|Accelerometer Startup Time<br>~~Os~~<br>~~|~~<br>~~oe~~|From Sleepmode<br>~~Os~~<br>~~|~~|~~Os~~<br>~~|~~|~~Os~~<br>~~|~~|20<br>~~Os~~|ms<br>~~Os~~|2,3<br>~~Os~~|
||From Cold Start,1ms VDDramp<br>~~|~~|~~|~~|~~|~~|30|ms|2,3<br>~~-~~|
|Output Data Rate<br>~~oe~~|Low-Power Mode|0.27||562.5|Hz|1<br>~~-~~|
||Low-Noise Mode<br>ACCEL_FCHOICE=1;<br>ACCEL_DLPFCFG=x|4.5||1.125k|Hz||
||Low-Noise Mode<br>ACCEL_FCHOICE=0;<br>ACCEL_DLPFCFG=x|||4.5k|Hz||
**Table 2. Accelerometer Specifications**
**Notes** :
1. Guaranteed by design 2. Derived from validation or characterization of parts, not guaranteed in production
3. Low-noise mode specification
Page 12 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
## **3.3 ELECTRICAL SPECIFICATIONS**
## **D.C. Electrical Characteristics**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
**==> picture [518 x 278] intentionally omitted <==**
**----- Start of picture text -----**<br>
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES<br> SUPPLY VOLTAGES<br>VDD 1.71 1.8 3.6 V 1<br>a GG<br>VDDIO 1.71 1.8 3.6 V 1<br>esee<br> SUPPLY CURRENTS & BOOT TIME<br>6-Axis Gyroscope + Accelerometer 3.2 mA 1<br>es<br>Low-Noise Mode 3-Axis Accelerometer 0.75 µA 1<br>3-Axis Gyroscope 2.6 mA 1<br>SSSes<br>Gyroscope Only Low-Power Mode, 102.3 Hz update rate, 1x<br>1.23 mA 2, 3<br>(DMP & Accelerometer disabled) averaging filter<br>ee Accelerometer Only Low-Power Mode, 102.3 Hz update rate, 1x ee ee<br>68.9 µA 2, 3<br>ae (DMP & Gyroscope disabled) averaging filter ee<br>Gyroscope + Accelerometer Low-Power Mode, 102.3 Hz update rate, 1x<br>1.27 mA 2, 3<br>ae (DMP disabled) averaging filter<br>Full-Chip Sleep Mode Se 8 µA 2<br>es ee<br> TEMPERATURE RANGE<br>Specified Temperature Range Performance parameters are not applicable<br>-40 +85 °C 1<br>beyond Specified Temperature Range<br>a ee ee<br>Table 3. D.C. Electrical Characteristics<br>**----- End of picture text -----**<br>
## **Notes:**
1. Guaranteed by design
2. Derived from validation or characterization of parts, not guaranteed in production
3. The 102.3 Hz ODR value shown here is an example, please see the section below for the full list of ODRs supported and corresponding current values
## **Low-Power Mode Noise and Power Performance**
Table 4 and Table 5 contain Gyroscope and Accelerometer noise and current consumption values for low-power mode, for various ODRs and averaging filter settings. Please refer to the ICM-20648 Register Map for further information about the registers referenced in the tables below.
|~~Rs~~<br>~~po~~<br>~~Ps~~<br>~~ee~~||**Averages**|**1x**|**2x**|**4x**|**8x**|**16x**|**32x**|**64x**|**128x**|~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
|||**GYRO_FCHOICE**<br>:|1<br>~~ee~~<br>~~pt~~|1<br>~~ee~~<br>~~pt~~<br>~~|~~|1<br>~~ee~~<br>~~|~~|1<br>~~ee~~<br>~~|~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~||
|||**GYRO_AVGCFG**<br>:<br>:|0<br>~~pt~~<br>~~a~~|1<br>~~pt~~<br>~~|~~<br>~~ee~~|2<br>~~|~~<br>~~ee~~|3<br>~~|~~<br>~~ee~~|4<br>~~ee~~|5<br>~~ee~~|6<br>~~ee~~|7<br>~~ee~~||
|||**Ton [ms]**<br>:<br>:|1.15<br>~~pt~~<br>~~a~~|1.59<br>~~pt~~<br>~~|~~<br>~~ee~~|2.48<br>~~|~~<br>~~ee~~|4.26<br>~~|~~<br>~~ee~~|7.82<br>~~ee~~|14.93<br>~~ee~~|29.15<br>~~ee~~|57.59<br>~~ee~~||
|||**NBW [Hz]**<br>:|773.5<br>~~a~~<br>~~caaccon~~|469.8<br>~~ee~~<br>~~caaccon~~|257.8<br>~~ee~~<br>~~caaccon~~|134.8<br>~~ee~~<br>~~caaccon~~|68.9<br>~~ee~~<br>~~caaccon~~|34.8<br>~~ee~~<br>~~caaccon~~|17.5<br>~~ee~~<br>~~caaccon~~|8.8<br>~~ee~~<br>~~caaccon~~||
|||**RMS Noise**<br>**[dps-rms] TYP**<br>**(based on gyroscope**<br>**noise: 0.015 dps/√Hz)**|0.42<br>~~caaccon~~|0.33<br>~~caaccon~~|0.24<br>~~caaccon~~|0.17<br>~~caaccon~~|0.12<br>~~caaccon~~|0.09<br>~~caaccon~~|0.06<br>~~caaccon~~|0.04<br>~~caaccon~~||
||**GYRO_SMPLRT_DIV**|**ODR [Hz]**|**Current Consumption [mA] TYP**<br>~~caaccon~~|||||||||
||255<br>~~Rs~~<br>~~po~~|4.4<br>~~Rs~~|1.04<br>~~Rs~~|1.05<br>~~Rs~~|1.05<br>~~Rs~~|1.06<br>~~Rs~~|1.09<br>~~Rs~~|1.14|1.24|1.45||
||64<br>~~Rs~~<br>~~po~~|17.3<br>~~Rs~~<br>~~Ge~~|1.07<br>~~Rs~~|1.08<br>~~Rs~~|1.10<br>~~Rs~~|1.15<br>~~Rs~~|1.25<br>~~Rs~~|1.45|1.85|N/A<br>~~Ps~~||
||63<br>~~po~~<br>~~Ps~~|17.6<br>~~Ps~~<br>~~Ge~~<br>~~es~~|1.07<br>~~Ps~~<br>~~ee~~|1.08<br>~~Ps~~<br>~~ee~~|1.11<br>~~Ps~~<br>~~ee~~|1.16<br>~~Ps~~|1.26<br>~~Ps~~|1.46<br>~~Ps~~|1.87<br>~~Ps~~|||
||32<br>~~Ps~~<br>~~ee~~|34.1<br>~~Ps~~<br>~~Ge~~<br>~~ee~~<br>~~es~~|1.10<br>~~Ps~~<br>~~ee~~<br>~~ee~~|1.12<br>~~Ps~~<br>~~ee~~<br>~~ee~~|1.17<br>~~Ps~~<br>~~ee~~<br>~~ee~~|1.27<br>~~Ps~~<br>~~ee~~|1.47<br>~~Ps~~<br>~~ee~~|1.86<br>~~Ps~~<br>~~ee~~|N/A<br>~~Ps~~|||
Page 13 of 82
Document Number: DS-000179 Revision: 1.2
TDK InvenSense
_**ICM-20648**_
|~~Pp~~<br>~~Pe~~|**Averages**<br>~~ee~~|**1x**<br>~~ee~~<br>~~ee~~|**4x**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**8x**<br>~~ee~~<br>~~ee~~<br>~~eee~~|**16x**<br>~~ee~~<br>~~eee~~|**32x**<br>~~ee~~<br>~~ee~~|
|---|---|---|---|---|---|---|
||**ACCEL_FCHOICE**<br>~~ee~~<br>~~Pp~~|0<br>~~ee ~~<br>~~ee~~<br>~~a~~|1<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|1<br>~~ee~~<br>~~eee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~<br>~~ee~~|
||**ACCEL_DLPFCFG**<br>~~a~~<br>~~Pp~~|x<br>~~a~~<br>~~a~~|7<br>~~ee ~~<br>~~a~~<br>~~ee~~|7<br> ~~eee~~<br>~~a~~<br>~~ee~~<br>~~SRN~~|7<br>~~eee ~~<br>~~a~~<br>~~ee~~<br>~~a~~|7<br> ~~ee~~<br>~~a~~<br>~~ee~~<br>~~a~~|
||**DEC3_CFG**<br>~~Pp~~<br>rt—“CSCSsrSCi‘“‘($ESL|0<br>~~a~~<br>rt—“CSCSsrSCi‘“‘($ESL<br>~~ee~~|0<br>~~ee~~<br>rt—“CSCSsrSCi‘“‘($ESL<br>~~ee~~|1<br>~~ee~~<br>rt—“CSCSsrSCi‘“‘($ESL**S**<br>~~SRN~~<br>~~ee~~|2<br>~~ee~~<br>**S**C“‘(RSHC<br>~~a~~<br>~~ee~~|3<br>~~ee~~<br>C“‘(RSHC<br>~~a~~<br>~~eee~~|
||**Ton (ms)**<br>~~Pp~~<br>~~ee~~|0.821<br>~~a~~<br>~~ee~~<br>~~ee~~|1.488<br>~~ee ~~<br>~~ee~~<br>~~ee~~|2.377<br> ~~ee ~~<br>~~SRN~~<br>~~ee~~<br>~~ee~~|4.154<br> ~~ee ~~<br>~~a~~<br>~~ee~~<br>~~ee~~|7.71<br> ~~ee~~<br>~~a~~<br>~~ee~~<br>~~eee~~|
||**NBW (Hz)**|1237.5<br>~~ee~~|496.8<br>~~ee ~~|264.8<br> ~~ee ~~|136.5<br> ~~ee~~|69.2<br>~~eee~~|
||**RMS Noise**<br>**[mg-rms] TYP**<br>**(based on accelerometer**<br>**noise: 230µg/√Hz)**<br>~~tt~~<br>|8.1<br>~~tt~~<br>|5.1<br>~~tt~~|3.7<br>~~tt~~|2.7<br>~~tt~~|1.9<br>~~tt~~|
|**ACCEL_SMPLRT_DIV**<br>~~Pees~~|**ODR [Hz]**<br>~~tt~~<br>~~eG~~|**Current Consumption [µA] TYP**<br>~~tt~~<br>~~eG~~|||||
|4095<br>~~Pees~~<br>~~es~~|0.27<br>~~tt~~<br>~~eG~~<br>~~GG~~|6.2<br>~~tt~~<br>~~eG~~<br>~~GG~~|6.3<br>~~tt~~<br>~~GG~~|6.5<br>~~tt~~|6.9<br>~~tt~~|7.6<br>~~tt~~|
|2044<br>~~es~~<br>~~es~~<br>~~es~~|0.55<br>~~eG~~<br>~~GG~~<br>~~ee~~<br>|6.3<br>~~eG~~<br>~~GG~~<br>|6.6<br>~~GG~~|7.0|7.7|9.2|
|1022<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|1.1<br>~~GG~~<br>~~es~~<br>~~ee~~<br>~~eG~~|6.7<br>~~GG~~<br>~~es~~<br>~~eG~~|7.2<br>~~GG~~<br>~~es~~|8.0<br>~~es~~|9.4<br>~~es~~|12.3<br>~~es~~|
|513<br>~~es~~<br>~~es~~|2.2<br>~~ee~~<br>~~eG~~<br>~~GG~~|7.3<br>~~eG~~<br>~~GG~~|8.4<br>~~GG~~|9.9|12.8|18.6|
|255<br>~~es~~<br>~~es~~<br>~~es~~|4.4<br>~~ee~~<br>~~eG~~<br>~~GG~~<br>~~eG~~<br>|8.7<br>~~eG~~<br>~~GG~~<br>~~eG~~<br>|10.9<br>~~GG~~|13.8|19.7|31.4|
|127<br><br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|8.8<br>~~eG~~<br>~~GG~~<br>~~es~~<br>~~eG~~<br>~~eG~~|11.4<br>~~eG~~<br>~~GG~~<br>~~es~~<br>~~eG~~<br>~~eG~~|15.8<br>~~GG~~<br>~~es~~|21.6<br>~~es~~|33.3<br>~~es~~|56.7<br>~~es~~|
|63<br>~~es~~<br>~~es~~|17.6<br>~~eG~~<br>~~eG~~<br>~~GG~~|16.8<br>~~eG~~<br>~~eG~~<br>~~GG~~|25.6<br>~~GG~~|37.3|60.7|107.5|
|31<br>~~es~~<br>~~es~~<br>~~es~~|35.2<br>~~eG~~<br>~~eG~~<br>~~GG~~<br>~~Se~~<br>|27.6<br>~~eG~~<br>~~eG~~<br>~~GG~~<br>|45.2<br>~~GG~~|68.6|115.3|208.9|
|22<br><br>~~es~~<br>~~es~~<br>~~es~~|48.9<br>~~eG~~<br>~~GG~~<br>~~es~~<br>~~Se~~<br>~~eG~~|36.1<br>~~eG~~<br>~~GG~~<br>~~es~~<br>~~eG~~|60.5<br>~~GG~~<br>~~es~~|93.0<br>~~es~~|158.1<br>~~es~~|288.3<br>~~es~~|
|15<br>~~es~~|70.3<br>~~Se~~<br>~~eG~~|49.2<br>~~eG~~|84.3|131.1|224.7|411.9|
|10<br>~~es~~<br>~~es~~|102.3<br>~~Se~~<br>~~eG~~<br>~~es~~|68.9<br>~~eG~~<br>~~es~~|119.9<br>~~es~~|188.0<br>~~es~~|324.1<br>~~es~~|596.3<br>~~es~~|
|7<br>~~es~~<br>~~es~~|140.6<br>~~es~~<br>~~ee~~|92.4<br>~~es~~|162.7<br>~~es~~|256.3<br>~~es~~|443.3<br>~~es~~|N/A|
|5<br>~~es~~<br>~~es ee~~|187.5<br>~~ee~~<br>~~ee~~|121.2<br>~~ee~~|214.9||||
|3<br>~~es~~<br>~~es ee~~|281.3<br>~~ee~~<br>~~ee~~|178.9<br>~~ee~~|319.3|N/A|||
|1<br>~~es ee~~<br>~~es~~|562.5<br>~~ee~~<br>~~es~~|351.7<br>~~ee~~<br>~~es~~|N/A||||
**Table 5. Accelerometer Noise and Current Consumption**
## **A.C. Electrical Characteristics**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
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|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTE**<br>**S**|
|---|---|---|---|---|---|---|
|**SUPPLIES**<br>||||||||
|Supply Ramp Time (TRAMP)|Monotonic ramp. Ramp<br>rate is 10% to 90% of the<br>final value.|0.01|20|100|ms|1|
|**TEMPERATURE SENSOR**<br>|<br>~~ae~~|||||||
|OperatingRange<br>~~————————~~|Ambient<br>~~————————~~|-40<br>~~————————~~|~~————————~~|85<br>~~————————~~|°C<br>~~————————~~<br>~~ae~~|1<br>~~————————~~<br>~~ae~~|
|Sensitivity<br>~~————————~~|Untrimmed<br>~~————————~~|~~————————~~|333.87<br>~~————————~~|~~————————~~|LSB/°C<br>~~————————~~<br>~~ae~~||
|Room TempOffset<br>~~————————~~|21°C<br>~~————————~~|~~————————~~|0<br>~~————————~~|~~————————~~|LSB<br>~~————————~~<br>~~ae~~||
|**POWER-ON RESET**<br>~~ae~~|||||||
|SupplyRampTime(TRAMP)<br>~~a~~|Validpower-on RESET<br>~~a~~|0.01<br>~~a~~|20<br>~~a~~|100<br>~~a~~|ms<br>~~a~~|1<br>~~a~~|
|Start-uptime for register read/write<br>~~a~~|Frompower-up<br>~~a~~<br>~~ee~~|~~a~~<br>~~es~~|11<br>~~a~~<br>~~es~~|100<br>~~a~~<br>~~ee~~|ms<br>~~a~~<br>~~ee~~|1<br>~~a~~|
|**I2C ADDRESS**<br>~~ee~~|AD0 = 0<br>AD0 = 1<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~es~~|1101000<br>1101001<br>~~ee~~<br>~~es~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|
|**DIGITAL INPUTS(FSYNC, AD0, SCLK, SDI, CS)**<br>~~ee~~<br>~~es es~~<br>~~ee~~<br>~~———~~<br>~~eeeeee~~|||||||
|VIH, High Level Input Voltage<br>~~———~~|~~ee~~|0.7*VDDIO<br>~~ee~~|~~ee~~||V|1|
|VIL, Low Level Input Voltage<br>~~———~~|~~ee~~|~~ee~~|~~ee~~|0.3*VDDIO|V||
|CI, Input Capacitance<br>~~———~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|< 10<br>~~ee~~<br>~~ee~~|~~ee~~|pF<br>~~ee~~||
|**DIGITAL OUTPUT(SDO, INT)**<br>~~———~~<br>~~ee ee ee~~<br>~~———~~|||||||
|VOH, High Level Output Voltage<br>~~GG~~<br>~~Re———~~|RLOAD=1 MΩ;<br>~~GG~~<br>~~———~~|0.9*VDDIO<br>~~GG~~|~~GG~~|~~GG~~|V<br>~~GG~~|1|
|VOL1, LOW-Level Output Voltage<br>~~Re———~~|RLOAD=1 MΩ;<br>~~———~~|||0.1*VDDIO|V||
|VOL.INT1, INT Low-Level Output Voltage<br>~~Re———~~<br>~~Pe~~|OPEN=1, 0.3 mA sink<br>Current<br>~~———~~<br>|||0.1<br>|V<br>||
|Output Leakage Current<br>~~———~~<br>~~Pe~~|OPEN=1<br>~~———~~<br><br>~~eG~~|~~eG~~|100<br>||nA<br>||
|tINT, INT Pulse Width<br>~~———~~<br>~~Peee~~|LATCH_INT_EN=0<br>~~———~~<br>~~ee~~<br>~~eG~~|~~ee~~<br>~~eG~~|50<br>~~ee~~|~~ee~~|µs<br>~~ee~~||
|**I2C I/O (SCL, SDA)**<br>~~———~~<br>~~ee~~<br>~~eG~~|||||||
|VIL, LOW Level Input Voltage<br>~~GG~~|~~GG~~|-0.5V<br>~~GG~~|~~GG~~|0.3*VDDIO<br>~~GG~~|V<br>~~GG~~|1|
|VIH, HIGH-Level Input Voltage<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|0.7*VDDIO<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|VDDIO + 0.5V<br>~~GG~~<br>~~GG~~|V<br>~~GG~~<br>~~GG~~||
|Vhys, Hysteresis<br>~~PG~~<br>~~Re~~|~~PG~~<br>|~~PG~~|0.1*VDDIO<br>~~PG~~|~~PG~~|V<br>~~PG~~||
|VOL, LOW-Level Output Voltage<br>~~Re~~|3mA sink current<br>|0||0.4|V||
|IOL, LOW-Level Output Current<br>~~ReSS~~<br>~~Re~~|VOL=0.4V<br>VOL=0.6V<br>~~SS~~<br>|~~SSSe~~<br>|3<br>6<br>~~SSSe~~<br>|~~SSSe~~<br>|mA<br>mA<br>~~SSSe~~<br>||
|Output Leakage Current<br>~~Re~~|~~ee~~|~~ee~~|100<br>||nA<br>||
|tof, Output Fall Time from VIHmaxto<br>VILmax<br>~~Rees~~|Cbbus capacitance in pf<br>~~es~~<br>~~ee~~|20+0.1Cb<br>~~es~~<br>~~ee~~|~~es~~|250<br>~~es~~|ns<br>~~es~~||
|**AUXILLIARY I/O (AUX_CL, AUX_DA)**<br>~~ee ee~~|||||||
|VIL, LOW-Level Input Voltage<br>~~GG~~<br>~~Re~~|~~GG~~|-0.5V<br>~~GG~~|~~GG~~|0.3*VDDIO<br>~~GG~~|V<br>~~GG~~|1<br>~~ee~~|
|VIH, HIGH-Level Input Voltage<br>~~Re~~<br>~~Pe~~||0.7* VDDIO||VDDIO + 0.5V|V||
|Vhys, Hysteresis<br>~~Re~~<br>~~Pees~~|~~ss~~|~~ss~~|0.1* VDDIO<br>~~ss~~||V||
|VOL1, LOW-Level Output Voltage<br>~~Pees~~|VDDIO > 2V; 1mA sink<br>current<br>~~ss~~<br>~~ee~~|0<br>~~ss~~<br>~~ee~~|~~ss~~|0.4|V||
|VOL3, LOW-Level Output Voltage<br>~~es~~<br>~~ee~~|VDDIO < 2V; 1mA sink<br>current<br>~~ss~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ss~~<br>~~ee~~<br>~~ee~~|~~ss~~<br>~~ee~~|0.2* VDDIO<br>~~ee~~|V<br>~~ee~~||
|IOL, LOW-Level Output Current<br>~~ee~~|VOL= 0.4V<br>VOL= 0.6V<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|3<br>6<br>~~ee~~|~~ee~~|mA<br>mA<br>~~ee~~||
|Output Leakage Current<br>~~PG~~|~~ee~~<br>~~PG~~<br>~~ee~~|~~PG~~<br>~~ee~~|100<br>~~PG~~<br>~~es ee~~|~~PG~~<br>~~ee~~|nA<br>~~PG~~<br>~~ee~~||
|tof, Output Fall Time from VIHmaxto<br>VILmax<br>~~es~~|Cbbus capacitance in pF<br>~~es~~<br>~~ee~~|20+0.1Cb<br>~~es~~<br>~~ee~~|~~es~~<br>~~es ee~~|250<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ee~~||
|**INTERNAL CLOCK SOURCE**<br>~~ee ee~~<br>~~es ee~~<br>~~ee~~<br>~~eeGG~~|||||||
|Clock FrequencyInitial Tolerance<br>~~ee~~|Accelerometer OnlyMode<br>~~GG~~|-5<br>~~GG~~||+5|%|1|
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|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTE**<br>**S**|
|---|---|---|---|---|---|---|
||Gyroscope or 6-Axis Mode<br>WITHOUT Timebase<br>Correction|-9||+9|%|1|
||Gyroscope or 6-Axis Mode<br>WITH Timebase Correction|-1||+1|||
|Frequency Variation over<br>Temperature|Accelerometer OnlyMode|-10||+10|%|1|
||Gyroscope or 6-Axis Mode||±1||%|1|
**Table 6. A.C. Electrical Characteristics**
## **Notes:**
1. Guaranteed by design
## **Other Electrical Specifications**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**SERIAL INTERFACE**|||||||
|SPI Operating Frequency, All Registers<br>Read/Write|Low Speed Characterization||100 ±10%||kHz||
||High Speed Characterization||7 ±10%||MHz||
|I2C Operating Frequency|All registers, Fast-mode|||400|kHz||
||All registers, Standard-mode|||100|kHz||
**Table 7. Other Electrical Specifications**
## **Notes** :
1. Derived from validation or characterization of parts, not guaranteed in production.
## **3.4 I[2] C TIMING CHARACTERIZATION**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**PARAMETERS**<br>||**CONDITIONS**|**MIN**<br>||**TYP**|**MAX**|**UNITS**|**NOTES**<br>||
|---|---|---|---|---|---|---|
|**I2C TIMING**<br>~~GC~~|**I2C FAST-MODE**<br>~~GC~~|~~GC~~|~~GC~~|~~GC~~|~~GC~~|~~GC~~|
|fSCL, SCL Clock Frequency<br>~~GC~~<br>~~Gf~~<br>~~es~~|~~GC~~<br>~~Gf~~<br>~~Gs~~<br>|~~GC~~<br>~~Gf~~<br>|~~GC~~<br>~~Gf~~<br>|400<br>~~GC~~<br>~~Gf~~<br>|kHz<br>~~GC~~<br>~~Gf~~|1, 2<br>~~GC~~<br>~~Gf~~|
|tHD.STA, (Repeated) START Condition Hold Time<br>~~Gf~~<br>~~rs~~<br>~~es~~|~~Gf~~<br>~~rs~~<br>~~Gs~~<br>|0.6<br>~~Gf~~<br>~~rs~~<br>|~~Gf~~<br>~~rs~~<br>|~~Gf~~<br>~~rs~~<br>|µs<br>~~Gf~~<br>~~rs~~|1, 2<br>~~Gf~~<br>~~rs~~|
|tLOW, SCL Low Period<br>~~es~~<br>~~es~~|~~Gs~~<br>~~**QQ**~~|1.3<br>~~**QQ**~~|~~**Gs**~~|~~**Gs**~~|µs|1, 2|
|tHIGH, SCL High Period<br>~~es~~<br>~~es~~|~~Gs~~<br>~~**QQ**~~|0.6<br>~~**QQ**~~|~~**Gs**~~|~~**Gs**~~|µs|1, 2|
|tSU.STA, Repeated START Condition Setup Time<br><br>~~es~~<br>~~re~~|~~**QQ**~~<br>~~re~~|0.6<br>~~**QQ** ~~<br>~~re~~|~~**Gs**~~<br>~~re~~|~~**Gs**~~<br>~~re~~|µs<br>~~re~~|1, 2<br>~~re~~|
|tHD.DAT, SDA Data Hold Time<br>~~Gf~~|~~Gf~~|0<br>~~Gf~~|~~Gf~~|~~Gf~~|µs<br>~~Gf~~|1, 2<br>~~Gf~~|
|tSU.DAT, SDA Data SetupTime<br>~~Gf~~<br>~~eG~~<br>~~rs~~|~~Gf~~<br>~~eG~~<br>~~GD~~|100<br>~~Gf~~<br>~~eG~~|~~Gf~~<br>~~eG~~|~~Gf~~<br>~~eG~~|ns<br>~~Gf~~<br>~~eG~~|1, 2<br>~~Gf~~<br>~~eG~~|
|tr, SDA and SCL Rise Time<br>~~eG~~<br>~~rs~~<br>~~es~~|Cbbus cap. from 10 to 400pF<br>~~eG~~<br>~~GD~~<br>~~QQ~~|20+0.1Cb<br>~~eG~~<br>~~QQ~~|~~eG~~<br>~~Gs~~|300<br>~~eG~~<br>~~Gs~~|ns<br>~~eG~~|1, 2<br>~~eG~~|
|tf, SDA and SCL Fall Time<br>~~rs~~<br>~~es~~|Cbbus cap. from 10 to 400pF<br>~~GD~~<br>~~QQ~~<br>~~GQ~~|20+0.1Cb<br>~~QQ~~<br>~~GQ~~|~~Gs~~<br>~~GQ~~|300<br>~~Gs~~|ns|1, 2|
|tSU.STO, STOP Condition Setup Time<br>~~es~~<br>~~rs~~<br>~~es~~|~~QQ~~<br>~~rs~~<br>~~GQ~~<br>~~ee~~<br>|0.6<br>~~QQ ~~<br>~~rs~~<br>~~GQ~~<br>~~ee~~<br>|~~Gs~~<br>~~rs~~<br>~~GQ~~<br>~~ee~~<br>|~~Gs~~<br>~~rs~~<br>~~ee~~<br>|µs<br>~~rs~~<br>~~ee~~|1, 2<br>~~rs~~<br>~~ee~~|
|tBUF, Bus Free Time Between STOP and START<br>Condition<br>~~ee~~<br>~~es~~|~~GQ~~<br>~~ee~~<br>~~ee~~<br>|1.3<br>~~GQ~~<br>~~ee~~<br>~~ee~~<br>|~~GQ~~<br>~~ee~~<br>~~ee~~<br>|~~ee~~<br>~~ee~~<br>|µs<br>~~ee~~<br>~~ee~~|1, 2<br>~~ee~~<br>~~ee~~|
|Cb, Capacitive Load for each Bus Line<br>~~es~~<br>~~es~~|~~ee~~<br>~~**QQ**~~|~~ee~~<br>~~**QQ**~~|< 400<br>~~ee~~<br>~~**Gs**~~|~~ee~~<br>~~**Gs**~~|pF<br>~~ee~~|1, 2<br>~~ee~~|
|tVD.DAT, Data Valid Time<br>~~es~~<br>~~es~~|~~ee ~~<br>~~**QQ**~~<br>~~sf~~|~~ee ~~<br>~~**QQ**~~<br>~~sf~~|~~ee ~~<br>~~**Gs**~~|0.9<br> ~~ee ~~<br>~~**Gs**~~|µs<br> ~~ee~~|1, 2<br>~~ee~~|
|tVD.ACK, Data Valid Acknowledge Time<br><br>~~es~~<br>~~rs~~|~~**QQ**~~<br>~~rs~~<br>~~sf~~|~~**QQ** ~~<br>~~rs~~<br>~~sf~~|~~**Gs**~~<br>~~rs~~|0.9<br>~~**Gs**~~<br>~~rs~~|µs<br>~~rs~~|1, 2<br>~~rs~~|
**Notes** :
1. Timing Characteristics apply to both Primary and Auxiliary I2C Bus
2. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
Page 16 of 82
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## ~~ASTDIKsimenser~~ ~~**s** e~~
## _**ICM-20648**_ ~~s~~
**==> picture [470 x 143] intentionally omitted <==**
**----- Start of picture text -----**<br>
tf tr tSU.DAT<br>SDA 70% 70%<br>30% 30%<br>tf continued below at A<br>tr tVD.DAT<br>SCL 70% tHD.DAT 70%<br>30% 30%<br>tHD.STA 1/fSCL tLOW 9 [th] clock cycle<br>S 1 [st] clock cycle tHIGH<br>tBUF<br>SDA 70%<br>A 30%<br>tSU.STA tHD.STA tVD.ACK tSU.STO<br>SCL 70%<br>30%<br>Sr 9 [th] clock cycle P S<br>**----- End of picture text -----**<br>
**Figure 1. I[2] C Bus Timing Diagram**
## **3.5 SPI TIMING CHARACTERIZATION**
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
|**Parameters**<br>~~ID~~<br>~~a~~|**Conditions**<br>~~ID~~|**Min**<br>~~ID~~<br>~~I~~|**Typical**<br>~~ID~~<br>~~nD~~<br>~~(O~~|**Max**<br>~~ID~~<br>~~I~~<br>~~(O~~|**Units**<br>~~ID~~<br>~~I~~|**Notes**<br>~~ID~~|
|---|---|---|---|---|---|---|
|**SPI TIMING**<br>~~ID~~<br>~~a~~|~~ID~~<br>~~nn~~|~~ID~~<br>~~I~~<br>~~(OOD~~|~~ID~~<br>~~nD ~~<br>~~(O~~<br>~~I~~|~~ID~~<br> ~~I~~<br>~~(O~~<br>~~I~~|~~ID~~<br>~~I~~<br>~~I~~|~~ID~~|
|fSCLK, SCLK Clock Frequency<br>~~rs~~|~~rs~~<br>~~nn~~|~~rs~~<br>~~(OOD~~|~~(O~~<br>~~rs~~<br>~~I~~|7<br>~~(O~~<br>~~rs~~<br>~~I~~<br>~~I~~|MHz<br>~~rs~~<br>~~I~~|~~rs~~|
|tLOW, SCLK Low Period<br>~~rs~~<br>~~(RO~~|~~rs~~<br>~~nn~~<br>~~(RO~~|64<br>~~rs~~<br>~~(OOD~~<br>~~(RO~~|~~rs~~<br>~~I~~<br>~~(RO~~|~~rs~~<br>~~I ~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~rs~~<br> ~~I~~<br>~~(RO~~|~~rs~~<br>~~(RO~~|
|tHIGH, SCLK High Period<br>~~(RO~~|~~(RO~~|64<br>~~(RO~~|~~(RO~~|~~I~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~(RO~~|~~(RO~~|
|tSU.CS, CS Setup Time<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|8<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~I~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|
|tHD.CS, CS Hold Time<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|500<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~I~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|
|tSU.SDI, SDI Setup Time<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|5<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~I~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|
|tHD.SDI, SDI Hold Time<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|7<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~I~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|
|tVD.SDO, SDO Valid Time<br>~~(RO~~<br>~~(RO~~|Cload= 20 pF<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|59<br>~~(RO~~<br>~~I~~<br>~~(RO~~<br>~~I~~<br>~~I~~|ns<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|
|tHD.SDO, SDO Hold Time<br>~~(RO~~<br>~~(RO~~|Cload= 20 pF<br>~~(RO~~<br>~~(RO~~|6<br>~~(RO~~<br>~~(RO~~<br>~~I~~|~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~I~~<br>~~(RO~~<br>~~I~~|ns<br>~~(RO~~<br>~~(RO~~|~~(RO~~<br>~~(RO~~|
|tDIS.SDO, SDO Output Disable Time<br>~~nD~~|~~nD~~|~~nD~~<br>~~I~~|~~nD~~|50<br>~~I~~<br>~~nD~~|ns<br>~~nD~~|~~nD~~|
**Table 9. SPI Timing Characteristics (7MHz)**
## **Notes:**
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
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CS 70%<br>30%<br>tHD;CS<br>| tSU;CS tHIGH 1/fCLK > |<br>SCLK 70%<br>30%<br>tSU;SDI tHD;SDI tLOW<br>SDI 70% MSB IN LSB IN<br>30%<br>tVD;SDO tHD;SDO tDIS;SDO<br>SDO 70%<br>MSB OUT LSB OUT<br>30%<br>**----- End of picture text -----**<br>
**Figure 2. SPI Bus Timing Diagram**
## **3.6 ABSOLUTE MAXIMUM RATINGS**
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability.
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|**PARAMETER**|**RATING**|
|---|---|
|Supply Voltage, VDD|-0.5V to 4V|
|Supply Voltage, VDDIO|-0.5V to 4V|
|REGOUT|-0.5V to 2V|
|Input Voltage Level (AUX_DA, AD0, FSYNC, INT, SCL, SDA)|-0.5V to VDD + 0.5V|
|Acceleration (Any Axis, unpowered)|10,000g for 0.2 ms|
|Operating Temperature Range|-40°C to +105°C|
|Storage Temperature Range|-40°C to +125°C|
|Electrostatic Discharge (ESD) Protection|2 kV (HBM);<br>200V (MM)|
|Latch-up|JEDEC Class II (2),125°C<br>±100 mA|
**Table 10. Absolute Maximum Ratings**
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## _**4 APPLICATIONS INFORMATION**_
## **4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION**
**PIN NUMBER PIN NAME PIN DESCRIPTION** ~~|~~ 7 AUX_CL I[2] C Master serial clock, for connecting to external sensors. ~~rs es~~ 8 VDDIO Digital I/O supply voltage. ~~es ee~~ 9 AD0 / SDO I[2] C Slave Address LSB (AD0); SPI serial data output (SDO). ~~es ee~~ 10 REGOUT Regulator filter capacitor connection. ~~rs rs~~ 11 FSYNC Frame synchronization digital input. Connect to GND if unused. ~~es ee~~ 12 INT1 Interrupt 1. ~~es eee~~ 13 VDD Power supply voltage. ~~rs ee~~ 18 GND Power supply ground. ~~es ee~~ 19 INT2 Interrupt 2. ~~es eee~~ 20 RESV Reserved. Connect to GND. ~~rs ee~~ 21 AUX_DA I[2] C master serial data, for connecting to external sensors. ~~es ee~~ 22 nCS Chip select (SPI mode only). ~~es ee~~ 23 SCL / SCLK I[2] C serial clock (SCL); SPI serial clock (SCLK). ~~rs rs~~ 24 SDA / SDI I[2] C serial data (SDA); SPI serial data input (SDI). ~~rs ee~~ 1 – 6, 14 - 17 NC No Connect pins. Do not connect. ~~es es~~
**Table 11. Signal Descriptions**
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NC 1 18 GND<br>NC 2 17 NC<br>NC 3 16 NC<br>ICM-20648<br>NC 4 15 NC<br>NC 5 14 NC<br>NC 6 13 VDD<br>SDA / SDI SCL / SCLK nCS AUX_DA RESV INT2<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>AUX_CL VDDIO SDO / AD0 REGOUT FSYNC INT1<br>**----- End of picture text -----**<br>
**Figure 3. Pin out Diagram for ICM-20648 3.0 mm x 3.0 mm x 9 mm QFN**
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## **4.2 TYPICAL OPERATING CIRCUIT**
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VDDIO<br>SCL<br>SDA<br>I<br>NC 1 18 GND<br>NC 2 17 NC<br>NC 3 ICM-20648 16 NC<br>NC 4 15 NC<br>NC 5 14 NC<br>NC 6 13 VDD 1.8 – 3.3VDC<br>A C2, 0.1 µF<br>1.8 – 3.3VDC<br>C3, 0.1 µ F A | A C1, 0.1 µF<br>AD0<br>SDA / SDI SCL / SCLK nCS AUX_DA RESV INT2<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>AUX_CL VDDIO SDO / AD0 REGOUT FSYNC INT1<br>**----- End of picture text -----**<br>
**Figure 4. ICM-20648 I[2] C Application Schematic**
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nCS<br>SCLK<br>SDI<br>l<br>NC 1 18 GND<br>NC 2 17 NC<br>NC 3 ICM-20648 16 NC<br>NC 4 15 NC<br>NC 5 14 NC<br>NC 6 13 VDD 1.8 – 3.3VDC<br>A C2, 0.1 µF<br>1.8 – 3.3VDC<br>C3, 0.1 µ F A | A C1, 0.1 µF<br>SDO<br>SDA / SDI SCL / SCLK nCS AUX_DA RESV INT2<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>AUX_CL VDDIO SDO / AD0 REGOUT FSYNC INT1<br>**----- End of picture text -----**<br>
**Figure 5. ICM-20648 SPI Application Schematic**
## **4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS**
|**COMPONENT**|**LABEL**|**SPECIFICATION**|**QUANTITY**|
|---|---|---|---|
|Regulator Filter Capacitor|C1|Ceramic, X7R, 0.1 µF ±10%, 2V|1|
|VDD Bypass Capacitor|C2|Ceramic, X7R, 0.1 µF ±10%, 4V|1|
|VDDIO Bypass Capacitor|C3|Ceramic, X7R, 0.1 µF ±10%, 4V|1|
**Table 12. Bill of Materials**
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## **4.4 BLOCK DIAGRAM**
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ICM-20648<br>INT1<br>Self<br>test X Accel ADC Interrupt INT2<br>e+ Status a [|]<br>Register<br>nCS<br>Self test Y Accel ADC Slave I2C and AD0 / SDO<br>SPI Serial<br>FIFO<br>Interface SCL / SCLK<br>25) Self test Z Accel ADC User & Config == SDA / SDI<br>Registers<br>US| Self == i Master I2C Serial s Interface Serial AUX_CL<br>test X Gyro AD C Sensor Interface Bypass Mux AUX_DA<br>Registers<br>p O ] S = es FSYNC<br>Self<br>test Y Gyro ADC<br>nL) 1<br>Digital Motion<br>Processor<br>Self test Z Gyro AD C (DMP)<br>oH JIH o _<br>Temp Sensor ADC<br>+<br>Charge Bias & LDOs<br>Pump<br>VDD GND REGOUT<br>Signal Conditioning<br>**----- End of picture text -----**<br>
**Figure 6. ICM-20648 Block Diagram**
## **4.5 OVERVIEW**
The ICM-20648 is comprised of the following key blocks and functions:
- Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
- Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
- Digital Motion Processor (DMP) engine
- Primary I[2] C and SPI serial communications interfaces
- Auxiliary I[2] C serial interface
- Self-Test
- Clocking
- Sensor Data Registers
- FIFO
- FSYNC
- Interrupts
- Digital-Output Temperature Sensor
- Bias and LDOs
- Charge Pump
- Power Modes
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## **4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING**
The ICM-20648 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps).
## **4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING**
The ICM-20648’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The ICM-20648’s architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0 _g_ on the X- and Y-axes and +1 _g_ on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted to ±2 _g_ , ±4 _g_ , ±8 _g_ , or ±16 _g_ .
## **4.8 DIGITAL MOTION PROCESSOR**
The embedded Digital Motion Processor (DMP) within the ICM-20648 offloads computation of motion processing algorithms from the host processor. The DMP acquires data from accelerometers, gyroscopes, and additional 3[rd] party sensors such as magnetometers, and processes the data. The resulting data can be read from the FIFO. The DMP has access to the external pins, which can be used for generating interrupts.
The purpose of the DMP is to offload both timing requirements and processing power from the host processor. Typically, motion processing algorithms should be run at a high rate, often around 200 Hz, in order to provide accurate results with low latency. This is required even if the application updates at a much lower rate; for example, a low power user interface may update as slowly as 5 Hz, but the motion processing should still run at 200 Hz. The DMP can be used to minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host processor for use in applications.
The DMP is optimized for Android Lollipop support.
## **4.9 PRIMARY I[2] C AND SPI SERIAL COMMUNICATIONS INTERFACES**
The ICM-20648 communicates to a system processor using either a SPI or an I[2] C serial interface. The ICM-20648 always acts as a slave when communicating to the system processor. The LSB of the of the I[2] C slave address is set by pin 1 (AD0).
## **ICM-20648 Solution Using I[2] C Interface**
In Figure 7, the system processor is an I[2] C master to the ICM-20648. In addition, the ICM-20648 is an I[2] C master to the optional external compass sensor. The ICM-20648 has limited capabilities as an I[2] C Master, and depends on the system processor to manage the initial configuration of any auxiliary sensors. The ICM-20648 has an interface bypass multiplexer, which connects the system processor I[2] C bus pins 23 and 24 (SCL and SDA) directly to the auxiliary sensor I[2] C bus pins 7 and 21 (AUX_CL and AUX_DA).
Once the auxiliary sensors have been configured by the system processor, the interface bypass multiplexer should be disabled so that the ICM-20648 auxiliary I[2] C master can take control of the sensor I[2] C bus and gather data from the auxiliary sensors.
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I [2] C Processor Bus: for reading all<br>Interrupt INT1 sensor data from MPU and for<br>Status<br>INT2 configuring external sensors (i.e.<br>Register compass in this example)<br>ICM-20648 AD0<br>VDD or GND<br>Slave I [2] C<br>or SPI SCL | SCL<br>Serial System<br>Interface SDA/SDI SDA Processor<br>FIFO<br>Sensor I [2] C Bus: for<br>configuring and reading<br>User & Config from external sensors<br>Registers<br>Optional<br>Sensor Master ISensor [2] C Interface AUX_CL ! SCL<br>Register InterfaceSerial Bypass Mux AUX_DA SDA Compass<br>Factory<br>Calibration<br>Digital<br>Motion<br>Processor<br>(DMP)<br>Interface bypass mux allows<br>direct configuration of<br>compass by system processor<br>Bias & LDOs<br>VDD GND REGOUT<br>**----- End of picture text -----**<br>
**Figure 7. ICM-20648 Solution Using I[2] C Interface**
## **ICM-20648 Solution Using SPI Interface**
In Figure 8, the system processor is an SPI master to the ICM-20648. Pins 9, 22, 23, and 24 are used to support the SDO, nCS, SCLK, and SDI signals for SPI communications. Because these SPI pins are shared with the I[2] C slave pins (9, 23 and 24), the system processor cannot access the auxiliary I[2] C bus through the interface bypass multiplexer, which connects the processor I[2] C interface pins to the sensor I[2] C interface pins. Since the ICM-20648 has limited capabilities as an I[2] C Master, and depends on the system processor to manage the initial configuration of any auxiliary sensors, another method must be used for programming the sensors on the auxiliary sensor I[2] C bus pins 7 and 21 (AUX_CL and AUX_DA).
When using SPI communications between the ICM-20648 and the system processor, configuration of devices on the auxiliary I[2] C sensor bus can be achieved by using I[2] C Slaves 0-4 to perform read and write transactions on any device and register on the auxiliary I[2] C bus. The I[2] C Slave 4 interface can be used to perform only single byte read and write transactions. Once the external sensors have been configured, the ICM-20648 can perform single or multi-byte reads using the sensor I[2] C bus. The read results from the Slave 0-3 controllers can be written to the FIFO buffer as well as to the external sensor registers.
For further information regarding the control of the ICM-20648’s auxiliary I[2] C interface, please refer to the ICM-20648 Register Map and Register Descriptions document.
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Processor SPI Bus: for reading all<br>data from MPU and for configuring<br>MPU and external sensors<br>Interrupt INT1<br>Status<br>Register INT2<br>nCS nCS<br>ICM-20648<br>SDO SDI<br>Slave I [2] C System<br>or SPI SCLK SCLK Processor<br>Serial<br>Interface SDI SDO<br>FIFO<br>Sensor I [2] C Bus: for<br>configuring and<br>Config reading data from<br>Register external sensors<br>Optional<br>Sensor Master ISensor [2] C Interface AUX_CL SCL<br>Register InterfaceSerial Bypass Mux AUX_DA SDA Compass<br>Factory<br>Calibration<br>Digital<br>Motion<br>Processor<br>(DMP) I [2] C Master performs<br>read and write<br>transactions on<br>Sensor I [2] C bus.<br>Bias & LDOs<br># '<br>VDD GND REGOUT<br>Figure 8. ICM-20648 Solution Using SPI Interface<br>AUXILIARY I [[2]] C SERIAL INTERFACE<br>The ICM-20648 has an auxiliary I [[2]] C bus for communicating to an off-chip 3-Axis digital output magnetometer or other sensors. This<br>bus has two operating modes:<br>• I [2] C Master Mode: The ICM-20648 acts as a master to any external sensors connected to the auxiliary I [2] C bus<br>**----- End of picture text -----**<br>
## **4.10 AUXILIARY I[[2]] C SERIAL INTERFACE**
The ICM-20648 has an auxiliary I[[2]] C bus for communicating to an off-chip 3-Axis digital output magnetometer or other sensors. This bus has two operating modes:
- Pass-Through Mode: The ICM-20648 directly connects the primary and auxiliary I[2] C buses together, allowing the system processor to directly communicate with any external sensors.
## **Auxiliary I[2] C Bus Modes of Operation:**
- I[2] C Master Mode: Allows the ICM-20648 to directly access the data registers of external digital sensors, such as a magnetometer. In this mode, the ICM-20648 directly obtains data from auxiliary sensors without intervention from the system applications processor.
For example, in I[2] C Master mode, the ICM-20648 can be configured to perform burst reads, returning the following data from a magnetometer:
- X magnetometer data (2 bytes)
- Y magnetometer data (2 bytes)
- Z magnetometer data (2 bytes)
- The I[2] C Master can be configured to read up to 24 bytes from up to 4 auxiliary sensors. A fifth sensor can be configured to work single byte read/write mode.
- Pass-Through Mode: Allows an external system processor to act as master and directly communicate to the external sensors connected to the auxiliary I[2] C bus pins (AUX_DA and AUX_CL). In this mode, the auxiliary I[2] C bus control logic (3[rd] party sensor interface block) of the ICM-20648 is disabled, and the auxiliary I[2] C pins AUX_CL and AUX_DA (pins 7 and 21) are connected to the main I[2] C bus (Pins 23 and 24) through analog switches internally. Pass-Through mode is useful for configuring the external sensors.
## **4.11 SELF-TEST**
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response.
The self-test response is defined as follows:
- SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITHOUT SELF-TEST ENABLED
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When the value of the self-test response is within the specified min/max limits, the part has passed self-test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test. It is recommended to use TDK-InvenSense MotionApps software for executing self-test.
## **4.12 CLOCKING**
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for optimum sensor performance and power consumption will be automatically selected based on the power mode. Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted that the internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register TIMEBASE_CORRECTION_PLL (detailed in section 12.5), and users can factor it in during distance and angle calculations to not sacrifice accuracy. Other than that, PLL has better frequency stability and lower frequency variation over temperature than the internal relaxation oscillator.
## **4.13 SENSOR DATA REGISTERS**
The sensor data registers contain the latest gyro, accelerometer, auxiliary sensor, and temperature measurement data. They are read-only registers, and are accessed via the serial interface. Data from these registers may be read anytime.
## **4.14 FIFO**
The ICM-20648 contains a FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set) that is accessible via the Serial Interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, auxiliary sensor readings, and FSYNC input.
A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads. The interrupt function may be used to determine when new data is available.
For further information regarding the FIFO, please refer to the ICM-20648 Register Map and Register Descriptions document.
## **4.15 FSYNC**
The FSYNC pin can be used from an external interrupt source to wake up the device from sleep. It is particularly useful in EIS applications to synchronize the gyroscope ODR with external inputs from an imaging sensor. Connecting the VSYNC or HSYNC pin of the image sensor subsystem to FSYNC on ICM-20648 allows timing synchronization between the two otherwise unconnected subsystems.
An FSYNC_ODR delay time register is used to capture the delay between an FSYNC pulse and the very next gyroscope data ready pulse.
## **4.16 INTERRUPTS**
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Section 5 provides a summary of interrupt sources. The ICM-20648 includes two interrupt pins, INT1 and INT2. Certain DMP based interrupts are mapped to INT2 while all other interrupts are mapped to INT1. The interrupt status can be read from the Interrupt Status register.
For further information regarding interrupts, please refer to the ICM-20648 Register Map and Register Descriptions document.
## **4.17 DIGITAL-OUTPUT TEMPERATURE SENSOR**
An on-chip temperature sensor and ADC are used to measure the ICM-20648 die temperature. The readings from the ADC can be read from the FIFO or the Sensor Data registers.
## **4.18 BIAS AND LDOS**
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-20648. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of Materials for External Components.
## **4.19 CHARGE PUMP**
An on-chip charge pump generates the high voltage required for the MEMS oscillators.
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## **4.20 STANDARD POWER MODES**
The following table lists the user-accessible power modes for ICM-20648.
|**MODE**|**NAME**|**GYRO**|**ACCEL**|**DMP**|
|---|---|---|---|---|
|1|SleepMode|Off|Off|Off|
|2|Accelerometer Mode|Off|Low-Noise or Low-Power|Duty-Cycled or Off|
|3|Gyroscope Mode|Low-Noise or Low-Power|Off|Duty-Cycled or Off|
|4|6-Axis Mode|Low-Noise or Low-Power|Low-Noise or Low-Power|Duty-Cycled or Off|
|5|DMP onlymode|Off|Off|Duty-Cycled|
**Table 13. Standard Power Modes for ICM-20648**
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## _**5 PROGRAMMABLE INTERRUPTS**_
The ICM-20648 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually.
|**INTERRUPT NAME**|**MODULE**|
|---|---|
|Motion Detection|Motion|
|FIFO Overflow|FIFO|
|Data Ready|Sensor Registers|
|DMP|DMP|
**Table 14. Table of Interrupt Sources**
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## _**6 DIGITAL INTERFACE**_
## **6.1 I[2] C AND SPI SERIAL INTERFACES**
The internal registers and memory of the ICM-20648 can be accessed using either I[2] C at 400 kHz or SPI at 7 MHz. SPI operates in four-wire mode.
|**PIN NUMBER**|**PIN NAME**|**PIN DESCRIPTION**|
|---|---|---|
|9|AD0 / SDO|I2C Slave Address LSB (AD0); SPI serial data output (SDO)|
|22|nCS|Chip select (SPI mode only)|
|23|SCL / SCLK|I2C serial clock (SCL); SPI serial clock (SCLK)|
|24|SDA / SDI|I2C serial data (SDA); SPI serial data input (SDI)|
## **Table 15. Serial Interface**
## **Note:**
To prevent switching into I[2] C mode when using SPI, the I[2] C interface should be disabled by setting the _I2C_IF_DIS_ configuration bit. Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in Section 6.3.
For further information regarding the _I2C_IF_DIS_ bit, please refer to the ICM-20648 Register Map and Register Descriptions document.
## **6.2 I[2] C INTERFACE**
I[2] C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bidirectional. In a generalized I[2] C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-20648 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20648 is b110100X which is 7 bits long. The LSB bit of the 7 bit address is determined by the logic level on pin AD0. This allows two ICM-20648s to be connected to the same I[2] C bus. When used in this configuration, the address of the one of the devices should be b1101000 (pin AD0 is logic low) and the address of the other should be b1101001 (pin AD0 is logic high).
## **6.3 I[2] C COMMUNICATIONS PROTOCOL**
## _START (S) and STOP (P) Conditions_
Communication on the I[2] C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below). Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
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**----- Start of picture text -----**<br>
SDA<br>SCL<br>S P<br>START condition STOP condition<br>**----- End of picture text -----**<br>
**Figure 9. START and STOP Conditions**
_Data Format / Acknowledge_
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I[2] C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line (refer to the following figure).
**==> picture [411 x 160] intentionally omitted <==**
**----- Start of picture text -----**<br>
DATA OUTPUT BY<br>TRANSMITTER (SDA)<br>NLC<br>not acknowledge<br>DATA OUTPUT BY<br>ee X<br>RECEIVER (SDA)<br>acknowledge<br>7 —<br>SCL FROM<br>1 2 8 9<br>MASTER<br>clock pulse for<br>START acknowledgement<br>condition<br>**----- End of picture text -----**<br>
**Figure 10. Acknowledge on the I[2] C Bus**
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## _Communications_
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8[th] bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the exception of start and stop conditions.
**==> picture [400 x 112] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL 1 – 7 8 9 1 – 7 8 9 1 – 7 8 9<br>S P<br>START ADDRESS R/W ACK DATA ACK DATA ACK STOP<br>condition condition<br>**----- End of picture text -----**<br>
**Figure 11. Complete I[2] C Data Transfer**
To write the internal ICM-20648 registers, the master transmits the start condition (S), followed by the I[2] C address and the write bit (0). At the 9[th] clock cycle (when the clock is high), the ICM-20648 acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the ICM-20648 acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM20648 automatically increments the register address and loads the data to the appropriate register. The following figures show single and two-byte write sequences.
_Single-Byte Write Sequence_
**==> picture [347 x 85] intentionally omitted <==**
_Burst Write Sequence_
To read the internal ICM-20648 registers, the master sends a start condition, followed by the I[2] C address and a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM-20648, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-20648 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9[th] clock cycle. The following figures show single and two-byte read sequences.
_Single-Byte Read Sequence_
Master S AD+W RA S AD+R NACK P Slave ACK ACK ACK DATA ~~AEE~~ _Burst Read Sequence_ Master S AD+W RA S AD+R ACK NACK P Slave ACK ACK ACK DATA DATA ~~ee~~
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## **6.4 I[2] C TERMS**
|**SIGNAL**|**DESCRIPTION**|
|---|---|
|S|Start Condition: SDAgoes from high to low while SCL is high|
|AD|Slave I2C address|
|W|Write bit(0)|
|R|Read bit(1)|
|ACK|Acknowledge: SDA line is low while the SCL line is high at the 9thclock cycle|
|NACK|Not-Acknowledge: SDA line stays high at the 9thclock cycle|
|RA|ICM-20648 internal register address|
|DATA|Transmit or received data|
|P|Stopcondition: SDAgoingfrom low to high while SCL is high|
**Table 16. I[2] C Terms**
## **6.5 SPI INTERFACE**
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20648 always operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
_SPI Operational Features_
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 7MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiplebyte Read/Writes, data is two or more bytes:
**==> picture [333 x 113] intentionally omitted <==**
**----- Start of picture text -----**<br>
SPI Address format<br>MSB LSB<br>a R/W A6 A5 A4 A3 A2 A1 A0<br>SPI Data format<br>MSB LSB<br>D7 D6 D5 D4 D3 D2 D1 D0<br>a<br>6. Supports Single or Burst Read/Writes.<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
SCLK<br>SDI<br>SPI Master SDO SPI Slave 1<br>/CS1 /CS<br>/CS2<br>SCLK<br>SDI<br>SDO<br>SPI Slave 2<br>/CS<br>**----- End of picture text -----**<br>
**Figure. 12 Typical SPI Master / Slave Configuration**
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## _**7 ORIENTATION OF AXES**_
## **7.1 ICM-20648 SUPPORTED INTERFACES**
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure.
**==> picture [91 x 108] intentionally omitted <==**
**----- Start of picture text -----**<br>
+Z<br>+Z +Y<br>+Y<br>+X +X<br>ICM-20648<br>**----- End of picture text -----**<br>
**Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation**
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## _**8 PACKAGE DIMENSIONS**_
This section provides package dimensions for the device. Information for the 24 Lead QFN 3.0x3.0x0.9 package is below.
**Figure 14. Package Dimensions**
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|~~**a**~~|**Symbol**|**MIN.**<br>~~(~~|**NOM.**<br>~~(~~|**MAX.**|
|---|---|---|---|---|
|Total Thickness<br>~~**a**~~|A|0.85<br>~~(~~|0.90<br>~~(~~|0.95|
|Stand Off<br>~~a~~<br>~~a~~|A1<br>~~a~~<br>|0.00<br>~~a~~<br>|0.02<br>~~a~~<br>|0.05<br>~~a~~<br>|
|Mold Thickness<br>~~a~~<br>~~a~~|A2<br>~~a~~<br>|---<br>~~a~~<br>|0.70<br>~~a~~<br>|---<br>~~a~~<br>|
|L/F Thickness<br>~~aee~~|A3<br>~~ee~~|0.203 REF<br>~~ee~~|||
|Lead Width<br>~~ee~~|b<br>~~ee~~|0.15<br>~~ee~~<br>~~ee~~|0.20<br>~~ee~~<br>~~ee~~|0.25<br>~~ee~~<br>~~ee~~|
|Body Size<br>~~ee~~|D<br>~~ee~~|2.90<br>~~ee~~<br>~~ee~~|3.00<br>~~ee~~<br>~~ee~~|3.10<br>~~ee~~<br>~~ee~~|
||E<br>~~ee~~|2.90<br>~~ee~~<br>~~ee~~|3.00<br>~~ee~~<br>~~ee~~|3.10<br>~~ee~~<br>~~ee~~|
|Lead Pitch<br>~~SS~~|e<br>~~SS~~|0.40 BSC<br>~~ee ee~~<br>~~SS~~|||
|EP Size<br>~~SS~~<br>~~ee~~|J<br>~~SS~~|1.65<br>~~SS~~|1.70<br>~~SS~~|1.75<br>~~SS~~|
||K<br>~~SS~~<br>~~ee~~|1.49<br>~~SS~~<br>~~ee~~|1.54<br>~~SS~~<br>~~ee~~|1.59<br>~~SS~~<br>~~ee~~|
|Lead Length<br>~~ee~~|L<br>~~ee~~|0.25<br>~~ee~~|0.30<br>~~ee~~|0.35<br>~~ee~~|
|~~ee~~|S<br>~~ee~~|0.25 REF<br>~~ee~~|||
|~~ee~~|R<br>~~ee~~|0.075<br>~~ee~~|---<br>~~ee~~|---<br>~~ee~~|
|~~a~~|H|0.12 REF|||
|~~aa~~|P|0.22 REF|||
|Mold Flatness<br>~~aa~~|bbb|0.10|||
|Coplanarity<br>~~aa~~|ccc|0.075|||
|Lead Offset<br>~~a~~<br>~~a~~<br>~~a~~|ddd|0.10|||
|Exposed Pad Offset<br>~~a~~<br>~~a~~|eee|0.10|||
**Table 17. Package Dimensions Table**
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## _**9 PART NUMBER PACKAGE MARKING**_
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**----- Start of picture text -----**<br>
The part number part markings for ICM-20648 devices are summarized below:<br>PART NUMBER PART NUMBER PACKAGE MARKING<br>ICM-20648 IC2648<br>eG!<br>TOP VIEW<br>Part Number IC2648<br>Lot Traceability Code X X X X X X<br> YYWW<br>Y Y = Year Code<br>W W = Work Week<br>**----- End of picture text -----**<br>
**Figure 15. Part Number Package Marking**
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## _**10 USE NOTES**_
## **10.1 GYROSCOPE MODE TRANSITION**
When gyroscope is transitioning from low-power to low-noise mode, several unsettled output samples will be observed at the gyroscope output due to filter switching and settling. The number of unsettled gyroscope output samples depends on the filter and ODR settings.
## **10.2 POWER MANAGEMENT 1 REGISTER SETTING**
CLKSEL[2:0] has to be set to 001 to achieve the datasheet performance.
## **10.3 DMP MEMORY ACCESS**
Reading/writing DMP memory and FIFO through I[2] C in a multithreaded environment can cause wrong data being read. To avoid the issue, one may use SPI instead of I[2] C, or use I[2] C with mutexes.
## **10.4 TIME BASE CORRECTION**
The system clock frequency at room temperature in gyroscope mode and 6-Axis mode varies from part to part, and the clock rates specified in datasheet are the nominal values. The percentage of frequency deviation from the nominal values for each part is logged in register TIMEBASE_CORRECTION_PLL, and the range of the code is ±10% with each LSB representing a step of 0.079%. For example, if on one part TIMEBASE_CORRECTION_PLL = 0x0C = d’12, it means the clock frequency in gyroscope mode and 6-Axis mode is ~0.94% faster than the nominal value.
When operating in accelerometer-only mode, the system clock frequency at room temperature is the nominal frequency over parts, and it is independent of the value stored in TIMEBASE_CORRECTION_PLL register.
## **10.5 I[2] C MASTER CLOCK FREQUENCY**
I[2] C master clock frequency can be set by register I2C_MST_CLK as shown in the table below. Due to temperature variation and part to part variation of system clock frequency in different power modes, I2C_MST_CLK should be set such that in all conditions the clock frequency will not exceed what a slave device can support. To achieve a targeted clock frequency of 400 kHz, MAX, it is recommended to set I2C_MST_CLK = 7 (345.6 kHz / 46.67% duty cycle).
|**I2C_MST_CLK**|**Nominal CLK**<br>**Frequency [kHz]**<br>~~ee~~|**Duty Cycle**<br>~~a~~|
|---|---|---|
|0<br>~~ee~~<br>~~ee~~|370.29<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|50.00%<br>~~ee~~|
|1<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|
|2<br>~~ee~~|370.29<br>~~ee~~<br>~~ee~~<br>~~ee~~|50.00%|
|3<br>~~ee ~~<br>~~ee~~|432.00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|50.00%<br>~~ee~~|
|4<br>~~ee~~<br>~~ee~~|370.29<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|42.86%<br>~~ee~~|
|5<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|370.29<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|50.00%<br>~~ee~~<br>~~ee~~|
|6<br>~~ee~~<br>~~ee~~|345.60<br>~~ee~~<br>~~**ee**~~|40.00%|
|7<br>~~ee ~~<br>~~ee~~<br>~~ee~~|345.60<br>~~ee~~<br> ~~**ee**~~<br>~~ee~~<br>|46.67%|
|8<br> <br>~~ee~~<br>~~ee~~<br>~~ee~~|304.94<br> ~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|47.06%<br>~~ee~~|
|9<br>~~ee~~<br>~~ee~~|432.00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|50.00%|
|10<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|432.00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|41.67%<br>~~ee~~|
|11<br>~~ee~~<br>~~ee~~|432.00<br>~~ee~~<br>~~**ee**~~|41.67%|
|12<br>~~ee ~~<br>~~ee~~<br>~~ee~~|471.27<br>~~ee~~<br> ~~**ee**~~<br>~~ee~~<br>|45.45%|
|13<br> <br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|432.00<br> ~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|50.00%<br>~~ee~~|
|14<br>~~ee~~<br>~~ee~~|345.60<br>~~ee~~<br>~~**ee**~~|46.67%|
|15<br>~~ee ~~<br>~~ee~~|345.60<br>~~ee~~<br> ~~**ee**~~|46.67%|
## **Table 18. I[2] C Master Clock Frequency**
## **10.6 CLOCKING**
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for optimum sensor performance
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and power consumption will be automatically selected based on the power mode. Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted that the internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register TIMEBASE_CORRECTION_PLL, and users can factor it in during distance and angle calculations to not sacrifice accuracy. Other than that, PLL has better frequency stability and lower frequency variation over temperature than the internal relaxation oscillator.
## **10.7 LP_EN BIT-FIELD USAGE**
The LP_EN bit-field (User Bank 0, PWR_MGMT_1 register, bit [5] helps to reduce the digital current. The recommended setting for this bit-field is 1 to achieve the lowest possible current. However when LP_EN is set to 1, user may not be able to write to the following registers. If it is desired to write to registers in this list, it is recommended to first set LP_EN=0, write the desired register(s), then set LP_EN=1 again:
- USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE, FIFO_COUNTH, FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
- USER BANK 1: All registers except REG_BANK_SEL
- USER BANK 2: All registers except REG_BANK_SEL
- USER BANK 3: All registers except REG_BANK_SEL
## **10.8 REGISTER ACCESS USING SPI INTERFACE**
Using the SPI interface, when the AP/user disables the gyroscope sensor (User Bank 0, PWR_MGMT_2 register, bits [2:0]=111) as part of a sequence of register read or write commands, the AP/user will be required to subsequently wait 22µs prior to any of the following operations:
- (1) Writing to any of the following registers:
- USER BANK 0: All registers except LP_CONFIG, PWR_MGMT_1, PWR_MGMT_2, INT_PIN_CFG, INT_ENABLE, FIFO_COUNTH, FIFO_COUNTL, FIFO_R_W, FIFO_CFG, REG_BANK_SEL
- USER BANK 1: All registers except REG_BANK_SEL
- USER BANK 2: All registers except REG_BANK_SEL
- USER BANK 3: All registers except REG_BANK_SEL
- (2) Reading data from FIFO
- (3) Reading from memory
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## _**11 REGISTER MAP**_
The following table lists the register map for the ICM-20648, for user banks 0, 1, 2, 3.
## **11.1 USER BANK 0 REGISTER MAP**
|**Addr**<br>**(Hex)**<br>~~PP~~|**Addr**<br>**(Dec.)**<br>~~PP~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~PP~~<br>~~a~~<br>~~a~~|0<br>~~PP~~<br>~~a~~<br>~~a~~|WHO_AM_I<br>~~a~~<br>~~es~~|R<br>~~ee~~<br>~~es~~|WHO_AM_I[7:0]<br>~~rs~~<br>~~rsrs~~||||||||
|03<br>~~a ~~<br>~~a~~<br>~~ee~~|3<br> ~~a ~~<br>~~a~~<br>~~ee~~|USER_CTRL<br> ~~a~~<br>~~es~~|R/W<br>~~ee~~<br>~~es~~<br>~~ee ee~~|DMP_EN<br>~~rs~~<br>~~ee~~|FIFO_EN<br>~~rs~~<br>~~ee~~|I2C_MST_EN<br>~~rs~~<br>~~es~~|I2C_IF_DIS<br>~~es~~|DMP_RST|SRAM_RST|I2C_MST_RST|-|
|05<br>~~a ~~<br>~~es~~<br>~~ee~~<br>~~a~~|5<br> ~~a~~<br>~~es~~<br>~~ee~~<br>|LP_CONFIG<br>~~es~~<br>~~es~~<br>~~se~~<br>|R/W<br>~~es ~~<br>~~es~~<br>~~ee ee~~<br>~~se~~<br>|~~rs~~<br>~~es~~<br>~~ee~~<br>~~es~~<br>|I2C_MST_CY<br>CLE<br>~~rs ~~<br>~~es~~<br>~~ee~~<br>~~ee es~~<br>|ACCEL_CYCLE<br> ~~rs~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|GYRO_CYCLE<br>~~es~~<br>~~es~~<br>|-<br>~~es~~<br>||||
|06<br>~~ee~~<br>~~a~~|6<br>~~ee~~<br>|PWR_MGMT_1<br>~~se~~<br>|R/W<br>~~ee ee~~<br>~~se~~<br>|DEVICE_RESE<br>T<br>~~ee ~~<br>~~es~~<br>|SLEEP<br> ~~ee ~~<br>~~ee es~~<br>|LP_EN<br> ~~es~~<br>~~es~~<br>|-<br>~~es~~<br>|TEMP_DIS<br>|CLKSEL[2:0]<br>|||
|07<br>~~a~~<br>~~a~~|7<br>~~a GQ~~|PWR_MGMT_2<br>~~se~~<br>~~GQ~~<br>~~ee~~|R/W<br>~~se~~<br>~~GQ~~<br>~~ee es~~|-<br>~~esee es~~<br>~~GQ~~<br>~~es ee~~||DISABLE_ACCEL<br>~~es~~<br>~~GQ~~<br>~~ee esee~~|||DISABLE_GYRO<br>~~GQ~~|||
|0F<br>~~a~~<br>~~a~~|15<br>~~a~~|INT_PIN_CFG<br>~~ee~~<br>~~es~~|R/W<br>~~ee es~~<br>~~es~~|INT1_ACTL<br>~~es ee~~<br>~~ee~~|INT1_OPEN<br>~~ee~~<br>~~es~~|INT1_LATCH_<br>INT_EN<br>~~ee es~~<br>~~es es~~|INT_ANYRD_<br>2CLEAR<br>~~es~~<br>~~es~~|ACTL_FSYNC<br>~~ee~~<br>~~ee~~|FSYNC_INT_<br>MODE_EN|BYPASS_EN|-|
|10<br>~~a~~<br>~~a~~<br>~~a~~|16<br>~~a~~<br>~~a~~|INT_ENABLE<br>~~ee~~<br>~~es~~<br>~~ee~~|R/W<br>~~ee es~~<br>~~es~~<br>~~ee~~|REG_WOF_E<br>N<br>~~es ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee ee es~~<br>~~es es~~<br>~~ee~~||DMP_INT2_E<br>N<br>~~es ~~<br>~~es~~|WOM_INT_E<br>N<br> ~~ee~~<br>~~ee~~|PLL_RDY_EN|DMP_INT1_E<br>N|I2C_MST_INT<br>_EN|
|11<br>~~a ~~<br>~~a~~<br>~~a~~|17<br> ~~a~~<br>~~a~~<br>~~a~~|INT_ENABLE_1<br>~~es~~<br>~~ee~~<br>~~a~~|R/W<br>~~es ~~<br>~~ee~~<br>~~es~~|INT2_ACTL<br> ~~ee~~<br>~~ee~~<br>~~ee~~|INT2_OPEN<br>~~es~~<br>~~ee~~<br>~~ee~~|INT2_LATCH_<br>EN<br>~~es es~~|-<br>~~es ee~~||||RAW_DATA_<br>0_RDY_EN|
|12<br>~~a ~~<br>~~a~~|18<br> ~~a~~<br>~~a~~|INT_ENABLE_2<br>~~ee~~<br>~~a~~|R/W<br>~~ee ~~<br>~~es~~|-<br> ~~ee ee~~<br>~~ee~~|||FIFO_OVERFLOW_EN[4:0]|||||
|13<br>~~a ~~<br>~~a~~<br><br>~~a~~|19<br> ~~a ~~<br>~~a~~<br>~~a~~<br><br>|INT_ENABLE_3<br> ~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~<br>|R/W<br>~~es ~~<br>~~a~~<br>~~ee er~~|-<br> ~~ee~~<br>~~a~~<br>~~ereeee~~|||FIFO_WM_EN[4:0]<br>~~ee~~|||||
|17<br>~~a~~<br>~~a~~|23<br>~~a~~<br>|I2C_MST_STATUS<br>~~aee~~<br>|R/C<br>~~ee er~~|PASS_THROU<br>GH<br>~~er~~|I2C_SLV4_DO<br>NE<br>~~ee~~|I2C_LOST_AR<br>B<br>~~ee~~|I2C_SLV4_NA<br>CK<br>~~ee~~|I2C_SLV3_NA<br>CK|I2C_SLV2_NA<br>CK|I2C_SLV1_NA<br>CK|I2C_SLV0_NA<br>CK|
|19<br><br>~~a ~~<br>~~ee~~|25<br><br> ~~a ~~<br>~~ee~~|INT_STATUS<br>~~ee~~<br> ~~a~~<br>~~i~~|R/C<br>~~ee er~~<br>~~ee~~|-<br>~~er ee ee~~||||WOM_INT|PLL_RDY_INT|DMP_INT1|I2C_MST_INT|
|1A<br>~~ee~~<br>~~a~~|26<br>~~ee~~<br>~~a~~|INT_STATUS_1<br>~~i~~<br>~~ee~~|R/C<br>~~ee~~<br>~~ee~~|-|||||||RAW_DATA_<br>0_RDY_INT|
|1B<br>~~ee~~<br>~~a~~<br>~~a~~|27<br>~~ee~~<br>~~a~~<br>~~a a~~|INT_STATUS_2<br>~~i~~<br>~~ee~~<br>~~a~~|R/C<br>~~ee~~<br>~~ee~~<br>~~er~~|-|||FIFO_OVERFLOW_INT[4:0]|||||
|1C<br>~~a ~~<br>~~a~~<br>~~a~~|28<br> ~~a~~<br>~~a a~~<br>~~a~~|INT_STATUS_3<br>~~ee~~<br>~~a~~<br>~~a~~|R/C<br>~~ee~~<br>~~er~~<br>~~es~~|-|||FIFO_WM_INT[4:0]|||||
|28<br>~~a ~~<br>~~a~~|40<br> ~~a a~~<br>~~a~~|DELAY_TIMEH<br>~~a~~<br>~~a~~|R<br>~~er~~<br>~~es~~|DELAY_TIMEH[7:0]||||||||
|29<br>~~a ~~<br>~~a~~<br>~~a~~|41<br> ~~a ~~<br>~~a~~<br>~~a~~<br>~~**a**~~<br>|DELAY_TIMEL<br> ~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br>~~**a**~~<br>|R<br>~~es~~<br>~~a~~<br>~~es~~|DELAY_TIMEL[7:0]||||||||
|2D<br>~~a~~<br>~~a~~|45<br>~~a~~<br>~~**a**~~<br>|ACCEL_XOUT_H<br>~~a~~<br>~~**a**~~<br>|R<br>~~es~~|ACCEL_XOUT_H[7:0]||||||||
|2E<br>~~a~~|46<br>~~**a** ~~<br>|ACCEL_XOUT_L<br> ~~**a**~~<br>|R<br>~~es~~|ACCEL_XOUT_L[7:0]||||||||
|2F<br>~~a~~|47<br>~~a~~<br>~~a~~|ACCEL_YOUT_H<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|ACCEL_YOUT_H[7:0]||||||||
|30<br>~~a~~|48<br>~~a~~<br>~~a~~|ACCEL_YOUT_L<br>~~a~~<br>~~a~~|R|ACCEL_YOUT_L[7:0]||||||||
|31<br>~~a~~<br>~~a~~|49<br>~~a~~<br>~~a ~~<br>~~a~~<br>~~a~~|ACCEL_ZOUT_H<br>~~a~~<br> ~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|ACCEL_ZOUT_H[7:0]||||||||
|32<br>~~a~~|50<br>~~a~~<br>~~a~~|ACCEL_ZOUT_L<br>~~a~~<br>~~a~~|R|ACCEL_ZOUT_L[7:0]||||||||
|33<br>~~a~~<br>~~a~~|51<br>~~a~~<br>~~a ~~<br>~~a~~<br>~~a~~|GYRO_XOUT_H<br>~~a~~<br> ~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|GYRO_XOUT_H[7:0]||||||||
|34<br>~~a~~<br>~~a~~|52<br>~~a~~<br>~~a ~~<br>~~a~~|GYRO_XOUT_L<br>~~a~~<br> ~~a~~<br>~~ee~~|R<br>~~rs~~|GYRO_XOUT_L[7:0]||||||||
|35<br>~~a~~|53<br>~~a~~|GYRO_YOUT_H<br>~~ee~~|R<br>~~rs~~|GYRO_YOUT_H[7:0]||||||||
|36<br>~~a ~~<br>~~a~~|54<br> ~~a~~<br>~~a~~<br>~~a~~|GYRO_YOUT_L<br>~~ee ~~<br>~~a~~<br>~~a~~<br>~~a~~|R<br> ~~rs~~<br>~~a~~|GYRO_YOUT_L[7:0]||||||||
|37<br>~~a~~<br>~~a~~|55<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a ~~|GYRO_ZOUT_H<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br> ~~a~~|R<br>~~a~~|GYRO_ZOUT_H[7:0]||||||||
|38<br>~~a~~|56<br>~~a~~<br>~~a~~|GYRO_ZOUT_L<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|GYRO_ZOUT_L[7:0]||||||||
|39<br>~~a~~|57<br>~~a~~<br>~~a ~~|TEMP_OUT_H<br>~~a~~<br> ~~a~~|R|TEMP_OUT_H[7:0]||||||||
|3A<br>~~a~~|58<br>~~a~~<br>~~a~~|TEMP_OUT_L<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|TEMP_OUT_L[7:0]||||||||
|3B<br>~~a~~|59<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_00<br>~~a~~<br> ~~a~~|R|EXT_SLV_SENS_DATA_00[7:0]||||||||
|3C<br>~~a~~|60<br>~~a~~<br>~~a~~|EXT_SLV_SENS_DATA_01<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_01[7:0]||||||||
|3D<br>~~a~~<br>~~a~~|61<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_02<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br> ~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_02[7:0]||||||||
|3E<br>~~a~~|62<br>~~a~~<br>~~a~~|EXT_SLV_SENS_DATA_03<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_03[7:0]||||||||
|3F<br>~~a~~|63<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_04<br>~~a~~<br> ~~a~~|R|EXT_SLV_SENS_DATA_04[7:0]||||||||
|40<br>~~a~~|64<br>~~a~~<br>~~a~~|EXT_SLV_SENS_DATA_05<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_05[7:0]||||||||
|41<br>~~a~~|65<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_06<br>~~a~~<br> ~~a~~|R|EXT_SLV_SENS_DATA_06[7:0]||||||||
|42<br>~~a~~|66<br>~~a~~<br>~~a~~|EXT_SLV_SENS_DATA_07<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_07[7:0]||||||||
|43<br>~~a~~<br>~~a~~|67<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_08<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~<br> ~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_08[7:0]||||||||
|44<br>~~a~~|68<br>~~a~~<br>~~a~~|EXT_SLV_SENS_DATA_09<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_09[7:0]||||||||
|45<br>~~a~~|69<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_10<br>~~a~~<br> ~~a~~|R|EXT_SLV_SENS_DATA_10[7:0]||||||||
|46<br>~~a~~|70<br>~~a~~<br>~~a~~|EXT_SLV_SENS_DATA_11<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~a~~|EXT_SLV_SENS_DATA_11[7:0]||||||||
|47<br>~~a~~|71<br>~~a~~<br>~~a ~~|EXT_SLV_SENS_DATA_12<br>~~a~~<br> ~~a~~|R|EXT_SLV_SENS_DATA_12[7:0]||||||||
|48<br>~~a ~~|72<br> ~~a ~~|EXT_SLV_SENS_DATA_13<br> ~~a~~|R|EXT_SLV_SENS_DATA_13[7:0]||||||||
Page 39 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|49<br>~~a~~ <br>~~a~~<br>~~a~~|73<br> ~~es~~<br>|EXT_SLV_SENS_DATA_14<br>~~es~~<br>~~es rs~~<br>|R<br>~~es~~<br>~~rs~~<br>|EXT_SLV_SENS_DATA_14[7:0]||||||||
|4A<br> <br>~~a~~<br>~~a~~<br>~~a~~|74<br> ~~es~~<br>~~ss~~|EXT_SLV_SENS_DATA_15<br>~~es~~<br>~~es rs~~<br>~~ss~~|R<br>~~es~~<br>~~rs~~<br>~~es~~|EXT_SLV_SENS_DATA_15[7:0]||||||||
|4B<br>~~a ~~<br>~~a~~<br>~~a~~|75<br> ~~ss~~<br>|EXT_SLV_SENS_DATA_16<br>~~es rs~~<br>~~ss~~<br>~~es~~|R<br>~~rs~~<br>~~es~~<br>~~es~~|EXT_SLV_SENS_DATA_16[7:0]||||||||
|4C<br> <br>~~a~~<br>~~a~~<br>~~a~~|76<br> ~~ss~~<br>~~a~~<br>|EXT_SLV_SENS_DATA_17<br>~~ss~~<br>~~es~~<br>~~es~~<br>|R<br>~~es~~<br>~~es~~<br>~~es~~<br>|EXT_SLV_SENS_DATA_17[7:0]||||||||
|4D<br>~~a ~~<br>~~a~~<br>~~a~~|77<br> ~~a~~<br>~~a~~<br>|EXT_SLV_SENS_DATA_18<br>~~es~~<br>~~es~~<br>~~es ee~~|R<br>~~es~~<br>~~es~~<br>~~ee~~|EXT_SLV_SENS_DATA_18[7:0]||||||||
|4E<br> <br>~~a~~<br>~~a~~<br>~~a~~|78<br> ~~a~~<br>~~a~~<br>~~a~~<br>|EXT_SLV_SENS_DATA_19<br>~~es~~<br>~~es ee~~<br>~~es~~<br>|R<br>~~es~~<br>~~ee~~<br>~~es~~<br>|EXT_SLV_SENS_DATA_19[7:0]||||||||
|4F<br> <br>~~a ~~<br>~~a ~~<br>~~a~~<br>~~a~~|79<br> ~~a~~<br> ~~a ~~<br> ~~a~~<br>~~**a**~~|EXT_SLV_SENS_DATA_20<br>~~es~~<br> ~~es ee~~<br>~~es~~<br>~~es ee~~|R<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|EXT_SLV_SENS_DATA_20[7:0]||||||||
|50<br> <br>~~a~~<br>~~a~~|80<br> ~~a~~<br>~~**a**~~|EXT_SLV_SENS_DATA_21<br>~~es~~<br>~~es ee~~|R<br>~~es~~<br>~~ee~~|EXT_SLV_SENS_DATA_21[7:0]||||||||
|51<br> <br>~~a~~|81<br> ~~**a** ~~|EXT_SLV_SENS_DATA_22<br> ~~es ee~~<br>~~ss~~|R<br>~~ee~~<br>~~ss~~|EXT_SLV_SENS_DATA_22[7:0]||||||||
|52<br>~~a~~|82<br>~~a~~|EXT_SLV_SENS_DATA_23<br>~~se~~|R<br>~~se~~|EXT_SLV_SENS_DATA_23[7:0]||||||||
|66<br>~~a~~ <br>~~ee~~|102<br> a<br>~~ee~~|FIFO_EN_1<br>~~es~~<br>~~i~~|R/W<br>~~es~~<br>~~ee~~|-<br>~~es~~<br>~~ee~~||||SLV_3_FIFO_<br>EN<br>~~es~~<br>~~ee~~|SLV_2_FIFO_<br>EN<br>~~es~~<br>~~ee~~|SLV_1_FIFO_<br>EN<br>~~es~~<br>~~ee~~|SLV_0_FIFO_<br>EN<br>~~es~~<br>~~ee~~|
|67<br>~~ee~~|103<br>~~ee~~|FIFO_EN_2<br>~~i~~|R/W<br>~~ee~~|-<br>~~ee~~|||ACCEL_FIFO_<br>EN<br>~~ee~~|GYRO_Z_FIF<br>O_EN<br>~~ee~~|GYRO_Y_FIF<br>O_EN<br>~~ee~~|GYRO_X_FIF<br>O_EN<br>~~ee~~|TEMP_FIFO_<br>EN<br>~~ee~~|
|68<br>~~ee~~<br>~~a~~<br>~~a~~|104<br>~~ee~~<br>~~ss~~|FIFO_RST<br>~~i~~<br>~~se~~<br>~~ss~~|R/W<br>~~ee~~<br>~~se~~<br>~~rs~~|-<br>~~ee~~<br>~~fe~~|||FIFO_RESET[4:0]<br>~~ee~~<br>~~fe~~|||||
|69<br>~~a~~<br>~~a~~|105<br>~~ss~~<br>~~a~~|FIFO_MODE<br>~~ss~~<br>~~es rs~~|R/W<br>~~rs~~<br>~~rs~~|-|||FIFO_MODE[4:0]|||||
|70<br>~~a ~~<br>~~a~~|112<br> ~~ss~~<br>~~a~~|FIFO_COUNTH<br>~~ss ~~<br>~~es rs~~|R<br> ~~rs~~<br>~~rs~~|-|||FIFO_CNT[12:8]|||||
|71<br>~~a ~~<br>~~a ~~<br>~~a~~|113<br> ~~a~~<br> ~~a~~<br>~~a~~|FIFO_COUNTL<br>~~es rs~~<br>~~ss~~<br>~~es es~~|R<br>~~rs~~<br>~~ss~~<br>~~es~~|FIFO_CNT[7:0]||||||||
|72<br>~~a~~<br>~~a~~|114<br>~~a~~|FIFO_R_W<br>~~es es~~<br>~~ee~~|R/W<br>~~es~~<br>~~ee~~|FIFO_R_W[7:0]<br>~~eeee~~||||||||
|74<br>~~a ~~<br>~~a~~|116<br> ~~a~~|DATA_RDY_STATUS<br>~~es es~~<br>~~ee~~|R/C<br>~~es~~<br>~~ee~~|WOF_STATU<br>S<br>~~ee~~|-<br>~~ee~~|||RAW_DATA_RDY[3:0]||||
|76<br>~~a~~<br>~~a ~~|118<br> ~~a~~|FIFO_CFG<br>~~ee~~<br>~~ss~~|R/W<br>~~ee ~~<br>~~ss~~|-<br> ~~ee ee~~|||||||FIFO_CFG|
|7F<br>~~a~~|127<br>~~a~~|REG_BANK_SEL<br>~~es~~|R/W<br>~~es~~|-||USER_BANK[1:0]||-||||
## **11.2 USER BANK 1 REGISTER MAP**
|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|02<br>~~a ~~<br>~~a~~<br>~~a~~|2<br> ~~ss~~<br>~~**a**~~|SELF_TEST_X_GYRO<br>~~ss~~<br>~~es ee~~|R/W<br>~~es~~<br>~~ee~~|XG_ST_DATA[7:0]||||||||
|03<br> <br>~~a~~<br>~~a~~|3<br> ~~ss~~<br>~~**a**~~|SELF_TEST_Y_GYRO<br>~~ss~~<br>~~es ee~~|R/W<br>~~es~~<br>~~ee~~|YG_ST_DATA[7:0]||||||||
|04<br> <br>~~a ~~<br>~~a~~<br>~~a~~|4<br> ~~ss~~<br> ~~**a** ~~<br>~~a~~|SELF_TEST_Z_GYRO<br>~~ss~~<br> ~~es ee~~<br>~~ss~~<br>~~es ee~~|R/W<br>~~es~~<br>~~ee~~<br>~~ss~~<br>~~ee~~|ZG_ST_DATA[7:0]||||||||
|0E<br>~~a~~|14<br>~~a~~|SELF_TEST_X_ACCEL<br>~~es ee~~|R/W<br>~~ee~~|XA_ST_DATA[7:0]||||||||
|0F<br>~~a ~~<br>~~a ~~<br>~~a~~|15<br> ~~a ~~<br> ~~a~~<br>~~a~~|SELF_TEST_Y_ACCEL<br> ~~es ee~~<br>~~ss~~<br>~~es ee~~|R/W<br>~~ee~~<br>~~ss~~<br>~~ee~~|YA_ST_DATA[7:0]||||||||
|10<br>~~a~~<br>~~a~~|16<br>~~a~~<br>~~a~~|SELF_TEST_Z_ACCEL<br>~~es ee~~<br>~~es es~~|R/W<br>~~ee~~<br>~~es~~|ZA_ST_DATA[7:0]||||||||
|14<br>~~a ~~<br>~~a~~<br>~~a~~|20<br> ~~a ~~<br>~~a~~<br>~~a~~|XA_OFFS_H<br> ~~es ee~~<br>~~es es~~<br>~~es rs~~|R/W<br>~~ee~~<br>~~es~~<br>~~rs~~|XA_OFFS[14:7]||||||||
|15<br>~~a~~<br>~~a~~<br>~~a~~|21<br>~~a~~<br>~~a~~<br>~~a~~|XA_OFFS_L<br>~~es es~~<br>~~es rs~~<br>~~es~~|R/W<br>~~es~~<br>~~rs~~<br>~~es~~|XA_OFFS[6:0]|||||||-|
|17<br>~~a ~~<br>~~a~~<br>~~a~~|23<br> ~~a~~<br>~~a~~<br>~~a~~|YA_OFFS_H<br>~~es rs~~<br>~~es~~<br>~~es es~~|R/W<br>~~rs~~<br>~~es~~<br>~~es~~|YA_OFFS[14:7]||||||||
|18<br>~~a ~~<br>~~a~~<br>~~a~~|24<br> ~~a ~~<br>~~a~~<br>~~a~~|YA_OFFS_L<br> ~~es ~~<br>~~es es~~<br>~~es es~~|R/W<br> ~~es~~<br>~~es~~<br>~~es~~|YA_OFFS[6:0]|||||||-|
|1A<br>~~a ~~<br>~~a~~<br>~~a~~|26<br> ~~a~~<br>~~a~~<br>~~a~~|ZA_OFFS_H<br>~~es es~~<br>~~es es~~<br>~~es rs~~|R/W<br>~~es~~<br>~~es~~<br>~~rs~~|ZA_OFFS[14:7]<br>~~rr~~||||||||
|1B<br>~~a~~<br>~~a~~|27<br>~~a~~<br>~~a~~|ZA_OFFS_L<br>~~es es~~<br>~~es rs~~|R/W<br>~~es~~<br>~~rs~~|ZA_OFFS[6:0]<br>~~rr~~|||||||-<br>~~rr~~|
|28<br>~~a ~~<br>~~se~~<br>~~a~~|40<br> ~~a~~<br>~~se~~<br>~~a~~|TIMEBASE_CORRECTION_PL<br>L<br>~~es rs~~<br>~~se~~<br>~~es ee~~|R/W<br>~~rs~~<br>~~se~~<br>~~ee~~|TBC_PLL[7:0]<br>~~rr~~<br>~~se~~||||||||
|7F<br>~~a~~|127<br>~~a~~|REG_BANK_SEL<br>~~es ee~~|R/W<br>~~ee~~|-||USER_BANK[1:0]||-||||
## **11.3 USER BANK 2 REGISTER MAP**
|**Addr**<br>**(Hex)**<br>~~||~~|**Addr**<br>**(Dec.)**<br>~~||~~|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~a ~~<br>~~a~~|0<br> ~~ss~~|GYRO_SMPLRT_DIV<br>~~ss es~~|R/W<br>~~es~~|GYRO_SMPLRT_DIV[7:0]<br>~~es~~||||||||
|01<br> <br>~~se~~<br>~~a~~|1<br> ~~ss~~<br>~~se~~|GYRO_CONFIG_1<br>~~ss es~~<br>~~se~~|R/W<br>~~es~~<br>~~se~~|-<br>~~se~~<br>~~es~~||GYRO_DLPFCFG[2:0]<br>~~se~~|||GYRO_FS_SEL[1:0]<br>~~se~~||GYRO_FCHOI<br>CE<br>~~se~~|
|02<br>~~a~~<br>~~a~~|2<br>~~a~~|GYRO_CONFIG_2<br>~~se~~<br>~~es es~~|R/W<br>~~se~~<br>~~es~~|-<br>~~es~~||XGYRO_CTEN|YGYRO_CTEN|ZGYRO_CTEN|GYRO_AVGCFG[2:0]|||
|03<br>~~a~~<br>~~a~~|3<br>~~a~~<br>~~a~~|XG_OFFS_USRH<br>~~es es~~<br>~~es ee~~|R/W<br>~~es~~<br>~~ee~~|X_OFFS_USER[15:8]||||||||
|04<br>~~a ~~<br>~~a~~|4<br> ~~a~~<br>~~a~~|XG_OFFS_USRL<br>~~es es~~<br>~~es ee~~|R/W<br>~~es~~<br>~~ee~~|X_OFFS_USER[7:0]||||||||
|05<br>~~a ~~<br>~~a ~~<br>~~a~~|5<br> ~~a ~~<br> ~~a~~<br>~~a~~|YG_OFFS_USRH<br> ~~es ee~~<br>~~ss~~<br>~~es ee~~|R/W<br>~~ee~~<br>~~ss~~<br>~~ee~~|Y_OFFS_USER[15:8]||||||||
|06<br>~~a~~|6<br>~~a~~|YG_OFFS_USRL<br>~~es ee~~|R/W<br>~~ee~~|Y_OFFS_USER[7:0]||||||||
|07<br>~~a ~~<br>~~a ~~|7<br> ~~a ~~<br> ~~a~~|ZG_OFFS_USRH<br> ~~es ee~~<br>~~ss~~|R/W<br>~~ee~~<br>~~ss~~|Z_OFFS_USER[15:8]||||||||
|08<br>~~a~~|8<br>~~a~~|ZG_OFFS_USRL<br>~~se~~|R/W<br>~~se~~|Z_OFFS_USER[7:0]||||||||
|09<br>~~a ~~<br>~~a~~|9<br> ~~a~~<br> a|ODR_ALIGN_EN<br>~~se~~|R/W<br>~~se~~|-|||||||ODR_ALIGN_<br>EN|
Page 40 of 82
Document Number: DS-000179 Revision: 1.2
_**ICM-20648**_
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|10|16|ACCEL_SMPLRT_DIV_1|R/W|-||||ACCEL_SMPLRT_DIV[11:8]||||
|11|17|ACCEL_SMPLRT_DIV_2|R/W|ACCEL_SMPLRT_DIV[7:0]||||||||
|12<br>~~Pe~~|18<br>~~Pe~~|ACCEL_INTEL_CTRL|R/W|-||||||ACCEL_INTEL<br>_EN|ACCEL_INTEL<br>_MODE_INT|
|13<br>~~a~~|19<br>~~a~~|ACCEL_WOM_THR|R/W|WOM_THRESHOLD[7:0]||||||||
|14<br>~~a~~|20<br>~~aee~~|ACCEL_CONFIG<br>~~ee~~|R/W<br>~~ee~~|-<br>~~ee~~||ACCEL_DLPFCFG[2:0]<br>~~ee~~|||ACCEL_FS_SEL[1:0]<br>~~ee~~||ACCEL_FCHOI<br>CE<br>~~ee~~|
|15<br>~~a~~|21<br>~~a~~|ACCEL_CONFIG_2<br>~~ee~~|R/W<br>~~ee~~<br>~~Oe~~|-<br>~~ee~~|||AX_ST_EN_R<br>EG<br>~~ee~~|AY_ST_EN_R<br>EG<br>~~ee~~|AZ_ST_EN_R<br>EG<br>~~ee~~|DEC3_CFG[1:0]<br>~~ee~~||
|52<br>~~ee~~|82<br>~~ee~~|FSYNC_CONFIG<br>~~ee~~|R/W<br>~~ee~~<br>~~Oe~~|DELAY_TIME<br>_EN<br>~~ee~~|-<br>~~ee~~|WOF_DEGLIT<br>CH_EN<br>~~ee~~|WOF_EDGE_I<br>NT<br>~~ee~~|EXT_SYNC_SET[3:0]<br>~~ee~~||||
|53<br>~~a~~|83<br>~~a~~|TEMP_CONFIG<br>~~a~~|R/W<br>~~Oe~~<br>~~a~~|-<br>~~a~~|||||TEMP_DLPFCFG[2:0]<br>~~a~~<br>~~ee~~|||
|54<br>~~a~~|84<br>~~a~~<br>~~ee~~|MOD_CTRL_USR<br>~~a~~<br>~~ee~~|R/W<br>~~a~~<br>~~ee~~|-<br>~~a~~<br>~~ee~~|||||||REG_LP_DMP<br>_EN<br>~~a~~<br>~~ee~~<br>~~ee~~|
|7F<br>~~a~~|127<br>~~a~~|REG_BANK_SEL<br>~~a~~|R/W<br>~~a~~|-<br>~~a~~||USER_BANK[1:0]<br>~~a~~||-<br>~~ee~~<br>~~a~~||||
## **11.4 USER BANK 3 REGISTER MAP**
|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~—f~~|0<br>~~—f~~|I2C_MST_ODR_CONFIG<br>|R/W<br>~~Oe~~|-||||I2C_MST_ODR_CONFIG[3:0]||||
|01<br>~~Pe~~<br>~~—f~~|1<br>~~Pe~~<br>~~—f~~|I2C_MST_CTRL<br>~~Pe~~<br>|R/W<br>~~Pe~~<br>~~Oe~~|MULT_MST_<br>EN<br>~~Pe~~|-<br>~~Pe~~||I2C_MST_P_<br>NSR<br>~~Pe~~|I2C_MST_CLK[3:0]<br>~~Pe~~||||
|02<br>~~—f~~|2<br>~~—f |~~|I2C_MST_DELAY_CTRL<br>~~|~~|R/W<br>~~Oe~~|DELAY_ES_S<br>HADOW|-||I2C_SLV4_DE<br>LAY_EN|I2C_SLV3_DE<br>LAY_EN|I2C_SLV2_DE<br>LAY_EN|I2C_SLV1_DE<br>LAY_EN|I2C_SLV0_DE<br>LAY_EN|
|03<br>~~—f~~<br>~~Pe~~|3<br>~~—f ~~<br>~~Pe~~|I2C_SLV0_ADDR<br><br>~~ee~~|R/W<br>~~Oe~~<br>~~ee~~|I2C_SLV0_RN<br>W|I2C_ID_0[6:0]|||||||
|04<br>~~a~~|4<br>~~a~~|I2C_SLV0_REG<br>~~a~~|R/W|I2C_SLV0_REG[7:0]||||||||
|05<br>~~a~~<br>~~Pe~~|5<br>~~a ~~<br>~~Pe~~|I2C_SLV0_CTRL<br> ~~a~~|R/W|I2C_SLV0_EN|I2C_SLV0_BY<br>TE_SW|I2C_SLV0_RE<br>G_DIS|I2C_SLV0_GR<br>P|I2C_SLV0_LENG[3:0]||||
|06<br>~~Pe~~<br>~~a~~|6<br>~~Pe~~<br>~~a~~|I2C_SLV0_DO<br>~~a~~|R/W|I2C_SLV0_DO[7:0]||||||||
|07<br>~~a~~|7<br>~~a~~|I2C_SLV1_ADDR<br>~~aee~~|R/W<br>~~ee~~|I2C_SLV1_RN<br>W|I2C_ID_1[6:0]|||||||
|08<br>~~a~~|8<br>~~a~~|I2C_SLV1_REG<br>~~a~~|R/W|I2C_SLV1_REG[7:0]||||||||
|09<br>~~a~~<br>~~Pe~~|9<br>~~a ~~<br>~~Pe~~|I2C_SLV1_CTRL<br> ~~a~~<br>~~ee~~|R/W<br>~~ee~~|I2C_SLV1_EN<br>~~ee~~|I2C_SLV1_BY<br>TE_SW<br>~~ee~~|I2C_SLV1_RE<br>G_DIS<br>~~ee~~|I2C_SLV1_GR<br>P<br>~~ee~~|I2C_SLV1_LENG[3:0]<br>~~ee~~||||
|0A<br>~~Pe~~<br>~~a~~|10<br>~~Pe~~<br>~~a~~|I2C_SLV1_DO<br>~~ee~~<br>~~a~~|R/W<br>~~ee~~|I2C_SLV1_DO[7:0]<br>~~ee~~||||||||
|0B<br>~~a~~|11<br>~~a~~|I2C_SLV2_ADDR<br>~~aee~~|R/W<br>~~ee~~|I2C_SLV2_RN<br>W<br>~~ee~~|I2C_ID_2[6:0]<br>~~ee~~|||||||
|0C<br>~~a~~<br>~~a~~<br>~~a~~|12<br>~~a~~<br>~~a~~<br>~~a~~|I2C_SLV2_REG<br>~~aee~~<br>~~a~~<br>|R/W<br>~~ee~~<br>~~Oe~~|I2C_SLV2_REG[7:0]<br>~~eeee~~||||||||
|0D<br>~~ee~~<br>~~a~~|13<br>~~ee~~<br>~~a~~|I2C_SLV2_CTRL<br>~~ee~~<br>|R/W<br>~~ee~~<br>~~Oe~~|I2C_SLV2_EN<br>~~ee~~|I2C_SLV2_BY<br>TE_SW<br>~~ee~~|I2C_SLV2_RE<br>G_DIS<br>~~ee~~|I2C_SLV2_GR<br>P<br>~~ee~~|I2C_SLV2_LENG[3:0]<br>~~ee~~||||
|0E<br>~~a~~|14<br>~~a a~~|I2C_SLV2_DO<br>~~a~~|R/W<br>~~Oe~~|I2C_SLV2_DO[7:0]||||||||
|0F<br>~~Pe~~|15<br>~~Pe~~|I2C_SLV3_ADDR|R/W|I2C_SLV3_RN<br>W|I2C_ID_3[6:0]|||||||
|10<br>~~a~~<br>~~a~~|16<br>~~a~~<br>~~a~~|I2C_SLV3_REG<br>~~a~~<br>|R/W<br>~~Oe~~|I2C_SLV3_REG[7:0]||||||||
|11<br>~~ee~~<br>~~a~~|17<br>~~ee~~<br>~~a~~|I2C_SLV3_CTRL<br>~~ee~~<br>|R/W<br>~~ee~~<br>~~Oe~~|I2C_SLV3_EN<br>~~ee~~|I2C_SLV3_BY<br>TE_SW<br>~~ee~~|I2C_SLV3_RE<br>G_DIS<br>~~ee~~|I2C_SLV3_GR<br>P<br>~~ee~~|I2C_SLV3_LENG[3:0]<br>~~ee~~||||
|12<br>~~a~~|18<br>~~a a~~|I2C_SLV3_DO<br>~~a~~|R/W<br>~~Oe~~|I2C_SLV3_DO[7:0]||||||||
|13<br>~~Pe~~|19<br>~~Pe~~|I2C_SLV4_ADDR|R/W|I2C_SLV4_RN<br>W|I2C_ID_4[6:0]|||||||
|14<br>~~a~~<br>|20<br>~~a~~<br>~~ee~~|I2C_SLV4_REG<br>~~ee Oe~~|R/W<br>~~Oe~~|I2C_SLV4_REG[7:0]||||||||
|15<br>~~a~~|21<br>~~aee~~|I2C_SLV4_CTRL<br>~~ee Oe~~|R/W<br>~~Oe~~|I2C_SLV4_EN|I2C_SLV4_BY<br>TE_SW|I2C_SLV4_RE<br>G_DIS|I2C_SLV4_DLY[4:0]|||||
|16<br><br>~~a~~|22<br>~~ee~~<br>~~a~~|I2C_SLV4_DO<br>~~ee Oe~~<br>~~a~~|R/W<br>~~Oe~~|I2C_SLV4_DO[7:0]||||||||
|17<br>~~a~~|23<br>~~a ~~|I2C_SLV4_DI<br> ~~a~~|R|I2C_SLV4_DI[7:0]||||||||
|7F|127|REG_BANK_SEL|R/W|-||USER_BANK[1:0]||-||||
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Document Number: DS-000179 Revision: 1.2
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_**ICM-20648**_
## _**12 USR BANK 0 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 0.
**Note:** The device will come up in sleep mode upon power-up.
## **12.1 WHO_AM_I**
**Name: WHO_AM_I Address: 0 (00h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0xE0 BIT NAME FUNCTION** 7:0 WHO_AM_I[7:0] Register to indicate to user which device is being accessed. The value for ICM-20648 is 0xE0
## **12.2 USER_CTRL**
|**12.2 USER_CTRL_CTRLCTRL**|**12.2 USER_CTRL_CTRLCTRL**|**12.2 USER_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: USER_CTRL**<br>**Address: 3 (03h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|DMP_EN|1 – Enables DMP features.<br>0 – DMP features are disabled after the currentprocessinground has completed.|
|6|FIFO_EN|1 – Enable FIFO operation mode.<br>0 – Disable FIFO access from serial interface.<br>To disable FIFO writes by DMA, use FIFO_EN register. To disable possible FIFO writes<br>from DMP,disable the DMP.|
|5|I2C_MST_EN|1 – Enable the I2C Master I/F module; pins ES_DA and ES_SCL are isolated from pins<br>SDA/SDI and SCL/ SCLK.<br>0 – Disable I2C Master I/F module; pins ES_DA and ES_SCL are logically driven by pins<br>SDA/SDI and SCL/SCLK.|
|4|I2C_IF_DIS|1 – Reset I2C Slave module andput the serial interface in SPI mode only.|
|3|DMP_RST|1 – Reset DMP module. Reset is asynchronous. This bit auto clears after one clock<br>cycle of the internal 20 MHz clock.|
|2|SRAM_RST|1 – Reset SRAM module. Reset is asynchronous. This bit auto clears after one clock<br>cycle of the internal 20 MHz clock.|
|1|I2C_MST_RST|1 – Reset I2C Master module. Reset is asynchronous. This bit auto clears after one<br>clock cycle of the internal 20 MHz clock.<br>**Note:**This bit should only be set when the I2C master has hung. If this bit is set during an active<br>I2C master transaction,the I2C slave will hang,which will require the host to reset the slave.|
|0|-|Reserved|
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## **12.3 LP_CONFIG**
**Name: LP_CONFIG Address: 5 (05h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x40**
|**12.3 LP_CONFIG_CONFIGCONFIG**|**12.3 LP_CONFIG_CONFIGCONFIG**|**12.3 LP_CONFIG_CONFIGCONFIG**|
|---|---|---|
|**Name: LP_CONFIG**<br>**Address: 5 (05h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x40**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|-|Reserved|
|6|I2C_MST_CYCLE|1 - Operate I2C master in duty cycled mode. ODR is determined by<br>I2C_MST_ODR_CONFIG register.<br>0 – Disable I2C master dutycycled mode.|
|5|ACCEL_CYCLE|1 – Operate ACCEL in duty cycled mode. ODR is determined by ACCEL_SMPLRT_DIV<br>register.<br>0 – Disable ACCEL dutycycled mode.|
|4|GYRO_CYCLE|1 – Operate GYRO in duty cycled mode. ODR is determined by GYRO_SMPLRT_DIV<br>register.<br>0 – Disable GYRO dutycycled mode.|
|3:0|-|Reserved|
## **12.4 PWR_MGMT_1**
**Name: PWR_MGMT_1 Address: 6 (06h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x41**
|**12.4 PWR_MGMT_1_MGMT_1MGMT_1_11 **|**12.4 PWR_MGMT_1_MGMT_1MGMT_1_11 **|**12.4 PWR_MGMT_1_MGMT_1MGMT_1_11 **|
|---|---|---|
|**Name: PWR_MGMT_1**<br>**Address: 6 (06h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x41**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|DEVICE_RESET|1 – Reset the internal registers and restores the default settings. Write a 1 to set the<br>reset,the bit will auto clear.|
|6|SLEEP|When set, the chip is set to sleep mode (in sleep mode all analog is powered off).<br>Clearingthe bit wakes the chipfrom sleepmode.|
|5|LP_EN|The LP_EN only affects the digital circuitry, it helps to reduce the digital current when<br>sensors are in LP mode. Please note that the sensors themselves are set in LP mode<br>by the LP_CONFIG register settings. Sensors in LP mode, and use of LP_EN bit<br>together help to reduce overall current. The bit settings are:<br>1: Turn on low power feature<br>0: Turn off low power feature<br>LP_EN has no effect when the sensors are in low-noise mode.|
|4|-|Reserved.|
|3|TEMP_DIS|When set to 1,this bit disables the temperature sensor.|
|2:0|CLKSEL[2:0]|**Code: Clock Source**<br>0: Internal 20 MHz oscillator<br>1-5: Auto selects the best available clock source – PLL if ready, else use the Internal<br>oscillator<br>6: Internal 20 MHz oscillator<br>7: Stops the clock and keeps timing generator in reset<br>**Note**: CLKSEL[2:0]should be set to 1~5 to achieve fullgyroscopeperformance.|
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## **12.5 PWR_MGMT_2**
|**12.5 PWR_MGMT_2_MGMT_2MGMT_2_22 **|**12.5 PWR_MGMT_2_MGMT_2MGMT_2_22 **|**12.5 PWR_MGMT_2_MGMT_2MGMT_2_22 **|
|---|---|---|
|**Name: PWR_MGMT_2**<br>**Address: 7 (07h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|DISABLE_ACCEL|Only the following values are applicable:<br>111 – Accelerometer (all axes) disabled<br>000 – Accelerometer(all axes)on|
|2:0|DISABLE_GYRO|Only the following values are applicable:<br>111 – Gyroscope (all axes) disabled<br>000 – Gyroscope(all axes)on|
## **12.6 INT_PIN_CFG**
|**12.6 INT_PIN_CFG_PIN_CFGPIN_CFG_CFGCFG**|**12.6 INT_PIN_CFG_PIN_CFGPIN_CFG_CFGCFG**|**12.6 INT_PIN_CFG_PIN_CFGPIN_CFG_CFGCFG**|
|---|---|---|
|**Name: INT_PIN_CFG**<br>**Address: 15 (0Fh)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT1_ACTL|1 – The logic level for INT1 pin is active low.<br>0 – The logic level for INT1pin is active high.|
|6|INT1_OPEN|1 – INT1 pin is configured as open drain.<br>0 – INT1pin is configured aspush-pull.|
|5|INT1_LATCH__EN|1 – INT1 pin level held until interrupt status is cleared.<br>0 – INT1pin indicates interruptpulse is width 50µs.|
|4|INT_ANYRD_2CLEAR|1 – Interrupt status in INT_STATUS is cleared (set to 0) if any read operation is<br>performed.<br>0 – Interrupt status in INT_STATUS is cleared (set to 0) only by reading INT_STATUS<br>register.<br>This bit only affects the interrupt status bits that are contained in the register<br>INT_STATUS, and the corresponding hardware interrupt.<br>This bit does not affect the interrupt status bits that are contained in registers<br>INT_STATUS_1, INT_STATUS_2, INT_STATUS_3, and the corresponding hardware<br>interrupt.|
|3|ACTL_FSYNC|1 – The logic level for the FSYNC pin as an interrupt to the ICM-20648 is active low.<br>0 – The logic level for the FSYNCpin as an interrupt to the ICM-20648 is active high.|
|2|FSYNC_INT_MODE_EN|1 – This enables the FSYNC pin to be used as an interrupt. A transition to the active<br>level described by the ACTL_FSYNC bit will cause an interrupt. The status of the<br>interrupt is read in the I2C Master Status register PASS_THROUGH bit.<br>0 – This disables the FSYNCpin from causingan interrupt.|
|1|BYPASS_EN|When asserted, the I2C_MASTER interface pins (ES_CL and ES_DA) will go into<br>‘bypass mode’ when the I2C master interface is disabled.|
|0|-|Reserved|
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## **12.7 INT_ENABLE**
**Name: INT_ENABLE Address: 16 (10h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00**
|**12.7 INT_ENABLE_ENABLEENABLE**|**12.7 INT_ENABLE_ENABLEENABLE**|**12.7 INT_ENABLE_ENABLEENABLE**|
|---|---|---|
|**Name: INT_ENABLE**<br>**Address: 16 (10h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|REG_WOF_EN|1 – Enable wake on FSYNC interrupt<br>0 – Function is disabled.|
|6:5|-|Reserved|
|4|DMP_INT2_EN|1 – Enable DMP interrupt to propagate to interrupt pin 2.<br>0 – Function is disabled.|
|3|WOM_INT_EN|1 – Enable interrupt for wake on motion to propagate to interrupt pin 1.<br>0 – Function is disabled.|
|2|PLL_RDY_EN|1 – Enable PLL RDY interrupt (PLL RDY means PLL is running and in use as the clock<br>source for the system) to propagate to interrupt pin 1.<br>0 – Function is disabled.|
|1|DMP_INT1_EN|1 – Enable DMP interrupt to propagate to interrupt pin 1.<br>0 – Function is disabled.|
|0|I2C_MST_INT_EN|1 – Enable I2C master interrupt to propagate to interrupt pin 1.<br>0 – Function is disabled.|
## **12.8 INT_ENABLE_1**
|**12.8 INT_ENABLE_1_ENABLE_1ENABLE_1_11 **|**12.8 INT_ENABLE_1_ENABLE_1ENABLE_1_11 **|**12.8 INT_ENABLE_1_ENABLE_1ENABLE_1_11 **|
|---|---|---|
|**Name: INT_ENABLE_1**<br>**Address: 17 (11h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|INT2_ACTL|1 – The logic level for INT2 pin is active low.<br>0 – The logic level for INT2pin is active high.|
|6|INT2_OPEN|1 – INT2 pin is configured as open drain.<br>0 – INT2pin is configured aspush-pull.|
|5|INT2_LATCH_EN|1 – INT2 pin level held until interrupt status is cleared.<br>0 – INT2pin indicates interruptpulse is width 50µs.|
|4:1|-|Reserved|
|0|RAW_DATA_0_RDY_EN|1 – Enable raw data ready interrupt from any sensor to propagate to interrupt pin 1.<br>0 – Function is disabled.|
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## **12.9 INT_ENABLE_2**
**Name: INT_ENABLE_2 Address: 18 (12h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:5 - Reserved 4:0 FIFO_OVERFLOW_EN[4:0] 1 – Enable interrupt for FIFO overflow to propagate to interrupt pin 1. 0 – Function is disabled.
## **12.10 INT_ENABLE_3**
|**12.10 INT_ENABLE_3_ENABLE_3ENABLE_3_33 **|**12.10 INT_ENABLE_3_ENABLE_3ENABLE_3_33 **|**12.10 INT_ENABLE_3_ENABLE_3ENABLE_3_33 **|
|---|---|---|
|**Name: INT_ENABLE_3**<br>**Address: 19 (13h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:0|FIFO_WM_EN[4:0]|1 – Enable interrupt for FIFO watermark to propagate to interrupt pin 1.<br>0 – function is disabled|
## **12.11 I2C_MST_STATUS**
|**12.11 I2C_MST_STATUS_MST_STATUSMST_STATUS_STATUSSTATUS**|**12.11 I2C_MST_STATUS_MST_STATUSMST_STATUS_STATUSSTATUS**|**12.11 I2C_MST_STATUS_MST_STATUSMST_STATUS_STATUSSTATUS**|
|---|---|---|
|**Name: I2C_MST_STATUS**<br>**Address: 23 (17h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/C**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|PASS_THROUGH|Status of FSYNC interrupt – used as a way to pass an external interrupt through this<br>chip to the host. If enabled in the INT_PIN_CFG register by asserting bit<br>FSYNC_INT_MODE_EN, this will cause an interrupt. A read of this register clears all<br>status bits in this register.|
|6|I2C_SLV4_DONE|Asserted when I2C slave 4’s transfer is complete, will cause an interrupt if bit<br>I2C_MST_INT_EN in the INT_ENABLE register is asserted, and if the<br>SLV4_DONE_INT_EN bit is asserted in the I2C_SLV4_CTRL register.|
|5|I2C_LOST_ARB|Asserted when I2C slave loses arbitration of the I2C bus, will cause an interrupt if bit<br>I2C_MST_INT_EN in the INT_ENABLE register is asserted.|
|4|I2C_SLV4_NACK|Asserted when slave 4 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN<br>in the INT_ENABLE register is asserted.|
|3|I2C_SLV3_NACK|Asserted when slave 3 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN<br>in the INT_ENABLE register is asserted.|
|2|I2C_SLV2_NACK|Asserted when slave 2 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN<br>in the INT_ENABLE register is asserted.|
|1|I2C_SLV1_NACK|Asserted when slave 1 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN<br>in the INT_ENABLE register is asserted.|
|0|I2C_SLV0_NACK|Asserted when slave 0 receives a NACK, will cause an interrupt if bit I2C_MST_INT_EN<br>in the INT_ENABLE register is asserted.|
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## **12.12 INT_STATUS**
|**12.12 INT_STATUS_STATUSSTATUS**|**12.12 INT_STATUS_STATUSSTATUS**|**12.12 INT_STATUS_STATUSSTATUS**|
|---|---|---|
|**Name: INT_STATUS**<br>**Address: 25 (19h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/C**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|WOM_INT|1 – Wake on motion interrupt occurred.|
|2|PLL_RDY_INT|1 – Indicates that the PLL has been enabled and is ready (delayof 4 ms ensures lock).|
|1|DMP_INT1|1 – Indicates the DMP hasgenerated INT1 interrupt|
|0|I2C_MST_INT|1 - Indicates I2C master hasgenerated an interrupt|
## **12.13 INT_STATUS_1**
|**12.13 INT_STATUS_1_STATUS_1STATUS_1_11 **|**12.13 INT_STATUS_1_STATUS_1STATUS_1_11 **|**12.13 INT_STATUS_1_STATUS_1STATUS_1_11 **|
|---|---|---|
|**Name: INT_STATUS_1**<br>**Address: 26 (1Ah)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/C**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:1|-|Reserved|
|0|RAW_DATA_0_RDY_INT|1 – Sensor Register Raw Data,from all sensors,is updated and readyto be read.|
## **12.14 INT_STATUS_2**
|**12.14 INT_STATUS_2_STATUS_2STATUS_2_22 **||
|---|---|
|**Name: INT_STATUS_2**||
|**Address: 27 (1Bh)**||
|**Type: USR0**||
|**Bank: 0**||
|**Serial IF: R/C**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:5<br>-|Reserved|
|4:0<br>FIFO_OVERFLOW_INT[4:0]|1 – FIFO Overflow interrupt occurred.|
## **12.15 INT_STATUS_3**
|**12.15 INT_STATUS_3_STATUS_3STATUS_3_33 **|**12.15 INT_STATUS_3_STATUS_3STATUS_3_33 **|**12.15 INT_STATUS_3_STATUS_3STATUS_3_33 **|
|---|---|---|
|**Name: INT_STATUS_3**<br>**Address: 28 (1Ch)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/C**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:0|FIFO_WM_INT[4:0]|1 – Watermark interrupt for FIFO occurred|
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## **12.16 DELAY_TIMEH**
|**12.16 DELAY_TIMEH_TIMEHTIMEH**|**12.16 DELAY_TIMEH_TIMEHTIMEH**|**12.16 DELAY_TIMEH_TIMEHTIMEH**|
|---|---|---|
|**Name: DELAY_TIMEH**<br>**Address: 40 (28h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|DELAY_TIMEH[7:0]|High-byte of delay time between FSYNC event and the 1st gyro ODR event (after the<br>FSYNC event).<br>Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next<br>update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take<br>the next update due to an FSYNC event.|
## **12.17 DELAY_TIMEL**
|**12.17 DELAY_TIMEL_TIMELTIMEL**|**12.17 DELAY_TIMEL_TIMELTIMEL**|**12.17 DELAY_TIMEL_TIMELTIMEL**|
|---|---|---|
|**Name: DELAY_TIMEL**<br>**Address: 41 (29h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|DELAY_TIMEL[7:0]|Low-byte of delay time between FSYNC event and the 1st gyro ODR event (after the<br>FSYNC event).<br>Reading DELAY_TIMEH will lock DELAY_TIMEH and DELAY_TIMEL from the next<br>update. Reading DELAY_TIMEL will unlock DELAY_TIMEH and DELAY_TIMEL to take<br>the next update due to an FSYNC event.<br>Delaytime inµs =(DELAY_TIMEH * 256 + DELAY_TIMEL)* 0.9645|
## **12.18 ACCEL_XOUT_H**
|**12.18 ACCEL_XOUT_H_XOUT_HXOUT_H_HH **||
|---|---|
|**Name: ACCEL_XOUT_H**||
|**Address: 45 (2Dh)**||
|**Type: USR0**||
|**Bank: 0**||
|**Serial IF: R**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>ACCEL_XOUT_H[7:0]|High Byte of Accelerometer X-axis data|
## **12.19 ACCEL_XOUT_L**
|**12.19 ACCEL_XOUT_L_XOUT_LXOUT_L_LL **|**12.19 ACCEL_XOUT_L_XOUT_LXOUT_L_LL **|**12.19 ACCEL_XOUT_L_XOUT_LXOUT_L_LL **|
|---|---|---|
|**Name: ACCEL_XOUT_L**<br>**Address: 46 (2Eh)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ACCEL_XOUT_L[7:0]|Low Byte of Accelerometer X-axis data<br>To convert the output of the accelerometer to acceleration measurement use the<br>formula below:<br>X_acceleration = ACCEL_XOUT/Accel_Sensitivity|
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## **12.20 ACCEL_YOUT_H**
**Name: ACCEL_YOUT_H Address: 47 (2Fh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 ACCEL_YOUT_H[7:0] High Byte of Accelerometer Y-axis data **12.21 ACCEL_YOUT_L Name: ACCEL_YOUT_L Address: 48 (30h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 ACCEL_YOUT_L[7:0] Low Byte of Accelerometer Y-axis data To convert the output of the accelerometer to acceleration measurement use the formula below: ~~—~~ Y_acceleration = ACCEL_YOUT/Accel_Sensitivity **12.22 ACCEL_ZOUT_H Name: ACCEL_ZOUT_H Address: 49 (31h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 ACCEL_ZOUT_H[7:0] High Byte of Accelerometer Z-axis data **12.23 ACCEL_ZOUT_L Name: ACCEL_ZOUT_L Address: 50 (32h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 ACCEL_ZOUT_L[7:0] Low Byte of Accelerometer Z-axis data To convert the output of the accelerometer to acceleration measurement use the formula below: ~~—~~ Z_acceleration = ACCEL_ZOUT/Accel_Sensitivity **12.24 GYRO_XOUT_H Name: GYRO_XOUT_H Address: 51 (33h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** ~~——~~ 7:0 GYRO_XOUT_H[7:0] High Byte of Gyroscope X-axis data Document Number: DS-000179 Page 49 of 82 Revision: 1.2
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## **12.25 GYRO_XOUT_L**
|**12.25 GYRO_XOUT_L_XOUT_LXOUT_L_LL **|**12.25 GYRO_XOUT_L_XOUT_LXOUT_L_LL **|**12.25 GYRO_XOUT_L_XOUT_LXOUT_L_LL **|
|---|---|---|
|**Name: GYRO_XOUT_L**<br>**Address: 52 (34h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_XOUT_L[7:0]|Low Byte of Gyroscope X-axis data<br>To convert the output of the gyroscope to angular rate measurement use the<br>formula below:<br>X_angular_rate = GYRO_XOUT/Gyro_Sensitivity|
## **12.26 GYRO_YOUT_H**
|**12.26 GYRO_YOUT_H_YOUT_HYOUT_H_HH **||
|---|---|
|**Name: GYRO_YOUT_H**||
|**Address: 53 (35h)**||
|**Type: USR0**||
|**Bank: 0**||
|**Serial IF: R**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>GYRO_YOUT_H[7:0]|High Byte of Gyroscope Y-axis data|
## **12.27 GYRO_YOUT_L**
|**12.27 GYRO_YOUT_L_YOUT_LYOUT_L_LL **|**12.27 GYRO_YOUT_L_YOUT_LYOUT_L_LL **|**12.27 GYRO_YOUT_L_YOUT_LYOUT_L_LL **|
|---|---|---|
|**Name: GYRO_YOUT_L**<br>**Address: 54 (36h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_YOUT_L[7:0]|Low Byte of Gyroscope Y-axis data<br>To convert the output of the gyroscope to angular rate measurement use the<br>formula below:<br>Y_angular_rate = GYRO_YOUT/Gyro_Sensitivity|
## **12.28 GYRO_ZOUT_H**
|**12.28 GYRO_ZOUT_H_ZOUT_HZOUT_H_HH **||
|---|---|
|**Name: GYRO_ZOUT_H**||
|**Address: 55 (37h)**||
|**Type: USR0**||
|**Bank: 0**||
|**Serial IF: R**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>GYRO_ZOUT_H[7:0]|High Byte of Gyroscope Z-axis data|
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## **12.29 GYRO_ZOUT_L**
|**12.29 GYRO_ZOUT_L_ZOUT_LZOUT_L_LL **|**12.29 GYRO_ZOUT_L_ZOUT_LZOUT_L_LL **|**12.29 GYRO_ZOUT_L_ZOUT_LZOUT_L_LL **|
|---|---|---|
|**Name: GYRO_ZOUT_L**<br>**Address: 56 (38h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_ZOUT_L[7:0]|Low Byte of Gyroscope Z-axis data<br>To convert the output of the gyroscope to angular rate measurement use the<br>formula below:<br>Z_angular_rate = GYRO_ZOUT/Gyro_Sensitivity|
## **12.30 TEMP_OUT_H**
|**12.30 TEMP_OUT_H_OUT_HOUT_H_HH **||
|---|---|
|**Name: TEMP_OUT_H**||
|**Address: 57 (39h)**||
|**Type: USR0**||
|**Bank: 0**||
|**Serial IF: R**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>TEMP_OUT_H[7:0]|High Byte of Tempsensor data|
## **12.31 TEMP_OUT_L**
|**12.31 TEMP_OUT_L_OUT_LOUT_L_LL **|**12.31 TEMP_OUT_L_OUT_LOUT_L_LL **|**12.31 TEMP_OUT_L_OUT_LOUT_L_LL **|
|---|---|---|
|**Name: TEMP_OUT_L**<br>**Address: 58 (3Ah)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|TEMP_OUT_L[7:0]|Low Byte of Temp sensor data<br>To convert the output of the temperature sensor to degrees C use the following<br>formula:<br>TEMP_degC =((TEMP_OUT – RoomTemp_Offset)/Temp_Sensitivity)+ 21degC|
## **12.32 EXT_SLV_SENS_DATA_00**
|**Name: EXT_SLV_SENS_DATA_00**<br>**Address: 59 (3Bh)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|**Name: EXT_SLV_SENS_DATA_00**<br>**Address: 59 (3Bh)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|**Name: EXT_SLV_SENS_DATA_00**<br>**Address: 59 (3Bh)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|EXT_SLV_SENS_DATA_00[7:0]|Sensor data read from external I2C devices via the I2C master interface. sThe data<br>stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0-<br>4)_CTRL registers|
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**12.33 EXT_SLV_SENS_DATA_01**
**Name: EXT_SLV_SENS_DATA_01 Address: 60 (3Ch) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_01[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~co~~ 4)_CTRL registers **12.34 EXT_SLV_SENS_DATA_02 Name: EXT_SLV_SENS_DATA_02 Address: 61 (3Dh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_02[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~co~~ 4)_CTRL registers **12.35 EXT_SLV_SENS_DATA_03 Name: EXT_SLV_SENS_DATA_03 Address: 62 (3Eh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_03[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~ce~~ 4)_CTRL registers **12.36 EXT_SLV_SENS_DATA_04 Name: EXT_SLV_SENS_DATA_04 Address: 63 (3Fh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_04[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~ce~~ 4)_CTRL registers **12.37 EXT_SLV_SENS_DATA_05 Name: EXT_SLV_SENS_DATA_05 Address: 64 (40h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_05[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~——~~ 4)_CTRL registers Document Number: DS-000179 Page 52 of 82 Revision: 1.2
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## **12.38 EXT_SLV_SENS_DATA_06**
**Name: EXT_SLV_SENS_DATA_06 Address: 65 (41h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_06[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.39 EXT_SLV_SENS_DATA_07**
**Name: EXT_SLV_SENS_DATA_07 Address: 66 (42h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_07[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.40 EXT_SLV_SENS_DATA_08**
**Name: EXT_SLV_SENS_DATA_08 Address: 67 (43h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_08[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.41 EXT_SLV_SENS_DATA_09**
**Name: EXT_SLV_SENS_DATA_09 Address: 68 (44h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_09[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.42 EXT_SLV_SENS_DATA_10**
**Name: EXT_SLV_SENS_DATA_10 Address: 69 (45h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00**
~~ee~~ **BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_10[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
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**12.43 EXT_SLV_SENS_DATA_11**
**Name: EXT_SLV_SENS_DATA_11 Address: 70 (46h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_11[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~co~~ 4)_CTRL registers **12.44 EXT_SLV_SENS_DATA_12 Name: EXT_SLV_SENS_DATA_12 Address: 71 (47h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_12[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~co~~ 4)_CTRL registers **12.45 EXT_SLV_SENS_DATA_13 Name: EXT_SLV_SENS_DATA_13 Address: 72 (48h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_13[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~ce~~ 4)_CTRL registers **12.46 EXT_SLV_SENS_DATA_14 Name: EXT_SLV_SENS_DATA_14 Address: 73 (49h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_14[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~ce~~ 4)_CTRL registers **12.47 EXT_SLV_SENS_DATA_15 Name: EXT_SLV_SENS_DATA_15 Address: 74 (4Ah) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_15[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0- ~~——~~ 4)_CTRL registers Document Number: DS-000179 Page 54 of 82 Revision: 1.2
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## **12.48 EXT_SLV_SENS_DATA_16**
**Name: EXT_SLV_SENS_DATA_16 Address: 75 (4Bh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_16[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.49 EXT_SLV_SENS_DATA_17**
**Name: EXT_SLV_SENS_DATA_17 Address: 76 (4Ch) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_17[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.50 EXT_SLV_SENS_DATA_18**
**Name: EXT_SLV_SENS_DATA_18 Address: 77 (4Dh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_18[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.51 EXT_SLV_SENS_DATA_19**
|**12.51 EXT_SLV_SENS_DATA_19_SLV_SENS_DATA_19SLV_SENS_DATA_19_SENS_DATA_19SENS_DATA_19_DATA_19DATA_19_1919**|**12.51 EXT_SLV_SENS_DATA_19_SLV_SENS_DATA_19SLV_SENS_DATA_19_SENS_DATA_19SENS_DATA_19_DATA_19DATA_19_1919**|**12.51 EXT_SLV_SENS_DATA_19_SLV_SENS_DATA_19SLV_SENS_DATA_19_SENS_DATA_19SENS_DATA_19_DATA_19DATA_19_1919**|
|---|---|---|
|**Name: EXT_SLV_SENS_DATA_19**<br>**Address: 78 (4Eh)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|EXT_SLV_SENS_DATA_19[7<br>:0]|Sensor data read from external I2C devices via the I2C master interface. The<br>data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and<br>I2C_SLV(0-4)_CTRL registers|
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## **12.52 EXT_SLV_SENS_DATA_20**
**Name: EXT_SLV_SENS_DATA_20 Address: 79 (4Fh) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_20[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.53 EXT_SLV_SENS_DATA_21**
**Name: EXT_SLV_SENS_DATA_21 Address: 80 (50h) Type: USR0 Bank: 0 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 EXT_SLV_SENS_DATA_21[7:0] Sensor data read from external I[2] C devices via the I[2] C master interface. The data stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(04)_CTRL registers
## **12.54 EXT_SLV_SENS_DATA_22**
|**12.54 EXT_SLV_SENS_DATA_22_SLV_SENS_DATA_22SLV_SENS_DATA_22_SENS_DATA_22SENS_DATA_22_DATA_22DATA_22_2222**|**12.54 EXT_SLV_SENS_DATA_22_SLV_SENS_DATA_22SLV_SENS_DATA_22_SENS_DATA_22SENS_DATA_22_DATA_22DATA_22_2222**|**12.54 EXT_SLV_SENS_DATA_22_SLV_SENS_DATA_22SLV_SENS_DATA_22_SENS_DATA_22SENS_DATA_22_DATA_22DATA_22_2222**|
|---|---|---|
|**Name: EXT_SLV_SENS_DATA_22**<br>**Address: 81 (51h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|EXT_SLV_SENS_DATA_22[7:0]|Sensor data read from external I2C devices via the I2C master interface. The data<br>stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0-<br>4)_CTRL registers|
## **12.55 EXT_SLV_SENS_DATA_23**
|**12.55 EXT_SLV_SENS_DATA_23_SLV_SENS_DATA_23SLV_SENS_DATA_23_SENS_DATA_23SENS_DATA_23_DATA_23DATA_23_2323**|**12.55 EXT_SLV_SENS_DATA_23_SLV_SENS_DATA_23SLV_SENS_DATA_23_SENS_DATA_23SENS_DATA_23_DATA_23DATA_23_2323**|**12.55 EXT_SLV_SENS_DATA_23_SLV_SENS_DATA_23SLV_SENS_DATA_23_SENS_DATA_23SENS_DATA_23_DATA_23DATA_23_2323**|
|---|---|---|
|**Name: EXT_SLV_SENS_DATA_23**<br>**Address: 82 (52h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|EXT_SLV_SENS_DATA_23[7:0]|Sensor data read from external I2C devices via the I2C master interface. The data<br>stored is controlled by the I2C_SLV(0-4)_ADDR, I2C_SLV(0-4)_REG, and I2C_SLV(0-<br>4)_CTRL registers|
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## **12.56 FIFO_EN_1**
|**12.56 FIFO_EN_1_EN_1EN_1_11 **|**12.56 FIFO_EN_1_EN_1EN_1_11 **|**12.56 FIFO_EN_1_EN_1EN_1_11 **|
|---|---|---|
|**Name: FIFO_EN_1**<br>**Address: 102 (66h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3|SLV_3_FIFO_EN|1 – write EXT_SENS_DATA registers associated to SLV_3 (as determined by<br>I2C_SLV2_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate;<br>0 – function is disabled|
|2|SLV_2_FIFO_EN|1 – write EXT_SENS_DATA registers associated to SLV_2 (as determined by<br>I2C_SLV0_CTRL, I2C_SLV1_CTRL, and I2C_SL20_CTRL) to the FIFO at the sample rate;<br>0 – function is disabled|
|1|SLV_1_FIFO_EN|1 – write EXT_SENS_DATA registers associated to SLV_1 (as determined by<br>I2C_SLV0_CTRL and I2C_SLV1_CTRL) to the FIFO at the sample rate;<br>0 – function is disabled|
|0|SLV_0_FIFO_EN|1 – write EXT_SENS_DATA registers associated to SLV_0 (as determined by<br>I2C_SLV0_CTRL) to the FIFO at the sample rate;<br>0 – function is disabled|
## **12.57 FIFO_EN_2**
**Name: FIFO_EN_2 Address: 103 (67h) Type: USR0 Bank: 0 Serial IF: R/W Reset Value: 0x00**
|**12.57 FIFO_EN_2_EN_2EN_2_22 **|**12.57 FIFO_EN_2_EN_2EN_2_22 **|**12.57 FIFO_EN_2_EN_2EN_2_22 **|
|---|---|---|
|**Name: FIFO_EN_2**<br>**Address: 103 (67h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|ACCEL_FIFO_EN|1 – write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,<br>ACCEL_ZOUT_H, and ACCEL_ZOUT_L to the FIFO at the sample rate;<br>0 – function is disabled|
|3|GYRO_Z_FIFO_EN|1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate<br>0 – function is disabled|
|2|GYRO_Y_FIFO_EN|1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate<br>0 – function is disabled|
|1|GYRO_X_FIFO_EN|1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate<br>0 – function is disabled|
|0|TEMP_FIFO_EN|1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate<br>0 – function is disabled|
## **12.58 FIFO_RST**
|**12.58 FIFO_RST_RSTRST**|**12.58 FIFO_RST_RSTRST**|**12.58 FIFO_RST_RSTRST**|
|---|---|---|
|**Name: FIFO_RST**<br>**Address: 104 (68h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:0|FIFO_RESET[4:0]|S/W FIFO reset. Assert and hold to set FIFO size to 0. Assert and de-assert to reset<br>FIFO.|
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## **12.59 FIFO_MODE**
|**12.59 FIFO_MODE_MODEMODE**|**12.59 FIFO_MODE_MODEMODE**|**12.59 FIFO_MODE_MODEMODE**|
|---|---|---|
|**Name: FIFO_MODE**<br>**Address: 105 (69h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:0|FIFO_MODE[4:0]|0 - Stream<br>1 - Snapshot<br>When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.<br>When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO,<br>replacingthe oldest data.|
## **12.60 FIFO_COUNTH**
|**Name: FIFO_COUNTH**<br>**Address: 112 (70h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|**Name: FIFO_COUNTH**<br>**Address: 112 (70h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|**Name: FIFO_COUNTH**<br>**Address: 112 (70h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4:0|FIFO_CNT[12:8]|High Bits, count indicates the number of written bytes in the FIFO.<br>Readingthis byte latches the data for both FIFO_COUNTH,and FIFO_COUNTL.|
## **12.61 FIFO_COUNTL**
|**Name: FIFO_COUNTL**<br>**Address: 113 (71h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|**Name: FIFO_COUNTL**<br>**Address: 113 (71h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|**Name: FIFO_COUNTL**<br>**Address: 113 (71h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R**<br>**Reset Value: 0x00**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_CNT[7:0]|Low bits,count indicates the number of written bytes in the FIFO.|
## **12.62 FIFO_R_W**
|**Name: FIFO_R_W**<br>**Address: 114 (72h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|**Name: FIFO_R_W**<br>**Address: 114 (72h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|**Name: FIFO_R_W**<br>**Address: 114 (72h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:0|FIFO_R_W[7:0]|Reading from or writing to this register actually reads/writes the FIFO. For example,<br>to write a byte to the FIFO, write the desired byte value to FIFO_R_W[7:0]. To read a<br>byte from the FIFO, perform a register read operation and access the result in<br>FIFO_R_W[7:0].|
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## **12.63 DATA_RDY_STATUS**
|**12.63 DATA_RDY_STATUS_RDY_STATUSRDY_STATUS_STATUSSTATUS**|**12.63 DATA_RDY_STATUS_RDY_STATUSRDY_STATUS_STATUSSTATUS**|**12.63 DATA_RDY_STATUS_RDY_STATUSRDY_STATUS_STATUSSTATUS**|
|---|---|---|
|**Name: DATA_RDY_STATUS**<br>**Address: 116 (74h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/C**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|WOF_STATUS|Wake on FSYNC interrupt status. Cleared on read.|
|6:4|-|Reserved.|
|3:0|RAW_DATA_RDY[3:0]|Data from sensors is copied to FIFO or SRAM.<br>Set when sequence controller kicks off on a sensor data load. Only bit 0 is relevant in<br>a single FIFO configuration. Cleared on read.|
## **12.64 FIFO_CFG**
|**12.64 FIFO_CFG_CFGCFG**|**12.64 FIFO_CFG_CFGCFG**|**12.64 FIFO_CFG_CFGCFG**|
|---|---|---|
|**Name: FIFO_CFG**<br>**Address: 118 (76h)**<br>**Type: USR0**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:1|-|Reserved|
|0|FIFO_CFG|This bit should be set to 1 if interrupt status for each sensor is required.|
## **12.65 REG_BANK_SEL**
|**12.65 REG_BANK_SEL_BANK_SELBANK_SEL_SELSEL**|**12.65 REG_BANK_SEL_BANK_SELBANK_SEL_SELSEL**|**12.65 REG_BANK_SEL_BANK_SELBANK_SEL_SELSEL**|
|---|---|---|
|**Name: REG_BANK_SEL**<br>**Address: 127 (7Fh)**<br>**Type: ALL**<br>**Bank: 0**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:4|USER_BANK[1:0]|Use the following values in this bit-field to select a USER BANK<br>0: Select USER BANK 0<br>1: Select USER BANK 1<br>2: Select USER BANK 2<br>3: Select USER BANK 3|
|3:0|-|Reserved|
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## _**13 USR BANK 1 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 1.
**Note:** The device will come up in sleep mode upon power-up.
## **13.1 SELF_TEST_X_GYRO**
|**13.1 SELF_TEST_X_GYRO_TEST_X_GYROTEST_X_GYRO_X_GYROX_GYRO_GYROGYRO**|**13.1 SELF_TEST_X_GYRO_TEST_X_GYROTEST_X_GYRO_X_GYROX_GYRO_GYROGYRO**|**13.1 SELF_TEST_X_GYRO_TEST_X_GYROTEST_X_GYRO_X_GYROX_GYRO_GYROGYRO**|
|---|---|---|
|**Name: SELF_TEST_X_GYRO**<br>**Address: 2 (02h)**<br>**Type: USR1**<br>**Bank: 1**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|XG_ST_DATA[7:0]|The value in this register indicates the self-test output generated during<br>manufacturing tests. This value is to be used to check against subsequent self-test<br>outputsperformed bythe end user.|
## **13.2 SELF_TEST_Y_GYRO**
|**13.2 SELF_TEST_Y_GYRO_TEST_Y_GYROTEST_Y_GYRO_Y_GYROY_GYRO_GYROGYRO**|**13.2 SELF_TEST_Y_GYRO_TEST_Y_GYROTEST_Y_GYRO_Y_GYROY_GYRO_GYROGYRO**|**13.2 SELF_TEST_Y_GYRO_TEST_Y_GYROTEST_Y_GYRO_Y_GYROY_GYRO_GYROGYRO**|
|---|---|---|
|**Name: SELF_TEST_Y_GYRO**<br>**Address: 3 (03h)**<br>**Type: USR1**<br>**Bank: 1**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|YG_ST_DATA[7:0]|The value in this register indicates the self-test output generated during<br>manufacturing tests. This value is to be used to check against subsequent self-test<br>outputsperformed bythe end user.|
## **13.3 SELF_TEST_Z_GYRO**
|**13.3 SELF_TEST_Z_GYRO_TEST_Z_GYROTEST_Z_GYRO_Z_GYROZ_GYRO_GYROGYRO**|**13.3 SELF_TEST_Z_GYRO_TEST_Z_GYROTEST_Z_GYRO_Z_GYROZ_GYRO_GYROGYRO**|**13.3 SELF_TEST_Z_GYRO_TEST_Z_GYROTEST_Z_GYRO_Z_GYROZ_GYRO_GYROGYRO**|
|---|---|---|
|**Name: SELF_TEST_Z_GYRO**<br>**Address: 4 (04h)**<br>**Type: USR1**<br>**Bank: 1**<br>**Serial IF: R/W**<br>**Reset Value: 0x00s**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|ZG_ST_DATA[7:0]|The value in this register indicates the self-test output generated during<br>manufacturing tests. This value is to be used to check against subsequent self-test<br>outputsperformed bythe end user.|
## **13.4 SELF_TEST_X_ACCEL**
|**13.4 SELF_TEST_X_ACCEL_TEST_X_ACCELTEST_X_ACCEL_X_ACCELX_ACCEL_ACCELACCEL**|**13.4 SELF_TEST_X_ACCEL_TEST_X_ACCELTEST_X_ACCEL_X_ACCELX_ACCEL_ACCELACCEL**|**13.4 SELF_TEST_X_ACCEL_TEST_X_ACCELTEST_X_ACCEL_X_ACCELX_ACCEL_ACCELACCEL**|
|---|---|---|
|**Name: SELF_TEST_X_ACCEL**<br>**Address: 14 (0Eh)**<br>**Type: USR1**<br>**Bank: 1**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|XA_ST_DATA[7:0]|Contains self-test data for the X Accelerometer.|
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**13.5 SELF_TEST_Y_ACCEL**
**Name: SELF_TEST_Y_ACCEL Address: 15 (0Fh) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 YA_ST_DATA[7:0] Contains self-test data for the Y Accelerometer. **13.6 SELF_TEST_Z_ACCEL Name: SELF_TEST_Z_ACCEL Address: 16 (10h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 ZA_ST_DATA[7:0] Contains self-test data for the Z Accelerometer. **13.7 XA_OFFS_H Name: XA_OFFS_H Address: 20 (14h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION** ~~a~~ 7:0 XA_OFFS[14:7] Upper bits of the X accelerometer offset cancellation. **13.8 XA_OFFS_L Name: XA_OFFS_L Address: 21 (15h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION** 7:1 XA_OFFS[6:0] Lower bits of the X accelerometer offset cancellation. 0 - Reserved ~~oo~~
**13.9 YA_OFFS_H**
**Name: YA_OFFS_H Address: 23 (17h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION** ~~a~~ 7:0 YA_OFFS[14:7] Upper bits of the Y accelerometer offset cancellation.
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**13.10 YA_OFFS_L**
**Name: YA_OFFS_L Address: 24 (18h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION** 7:1 YA_OFFS[6:0] Lower bits of the Y accelerometer offset cancellation. 0 - Reserved ~~—~~ **13.11 ZA_OFFS_H Name: ZA_OFFS_H Address: 26 (1Ah) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION** ~~—~~ 7:0 ZA_OFFS[14:7] Upper bits of the Z accelerometer offset cancellation. **13.12 ZA_OFFS_L Name: ZA_OFFS_L Address: 27 (1Bh) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: Trimmed on a per-part basis for optimal performance BIT NAME FUNCTION** 7:1 ZA_OFFS[6:0] Lower bits of the Z accelerometer offset cancellation. 0 - Reserved ~~——~~ **13.13 TIMEBASE_CORRECTION_PLL Name: TIMEBASE_CORRECTION_PLL Address: 40 (28h) Type: USR1 Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 TBC_PLL[7:0] System PLL clock period error (signed, [-10%, +10%]) **13.14 REG_BANK_SEL Name: REG_BANK_SEL Address: 127 (7Fh) Type: Bank: 1 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:6 - Reserved 5:4 USER_BANK[1:0] Use the following values in this bit-field to select a USER BANK 0: Select USER BANK 0 1: Select USER BANK 1 2: Select USER BANK 2 3: Select USER BANK 3 3:0 - Reserved ~~——~~ Document Number: DS-000179 Page 62 of 82 Revision: 1.2
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## _**14 USR BANK 2 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 2.
**Note:** The device will come up in sleep mode upon power-up.
## **14.1 GYRO_SMPLRT_DIV**
|**14.1 GYRO_SMPLRT_DIV_SMPLRT_DIVSMPLRT_DIV_DIVDIV**|**14.1 GYRO_SMPLRT_DIV_SMPLRT_DIVSMPLRT_DIV_DIVDIV**|**14.1 GYRO_SMPLRT_DIV_SMPLRT_DIVSMPLRT_DIV_DIVDIV**|
|---|---|---|
|**Name: GYRO_SMPLRT_DIV**<br>**Address: 0 (00h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|GYRO_SMPLRT_DIV[7:0]|Gyro sample rate divider. Divides the internal sample rate to generate the sample<br>rate that controls sensor data output rate, FIFO sample rate, and DMP sequence rate.<br>**Note**: This register is only effective when FCHOICE = 1’b1 (FCHOICE_B register bit is 1’b0), and<br>(0 < DLPF_CFG < 7).<br>ODR is computed as follows:<br>1.1 kHz/(1+GYRO_SMPLRT_DIV[7:0])|
## **14.2 GYRO_CONFIG_1**
|**14.2 GYRO_CONFIG_1_CONFIG_1CONFIG_1_11 **|**14.2 GYRO_CONFIG_1_CONFIG_1CONFIG_1_11 **|**14.2 GYRO_CONFIG_1_CONFIG_1CONFIG_1_11 **|
|---|---|---|
|**Name: GYRO_CONFIG_1**<br>**Address: 1 (01h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x01**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:3|GYRO_DLPFCFG[2:0]|Gyro lowpass filter configuration as shown in the table below|
|2:1|GYRO_FS_SEL[1:0]|Gyro Full Scale Select:<br>00 = ±250 dps<br>01= ±500 dps<br>10 = ±1000 dps<br>11 = ±2000 dps|
|0|GYRO_FCHOICE|0 – bypass gyro DLPF<br>1 – enablegyro DLPF|
The gyroscope DLPF is configured by GYRO_DLPFCFG _,_ when GYRO_FCHOICE = 1. The gyroscope data is filtered according to the value of GYRO_DLPFCFG and GYRO_FCHOICE as shown in the table below.
|**GYRO_FCHOICE**<br>~~es~~|**GYRO_DLPFCFG**|**Output**|**Output**|**Output**|
|---|---|---|---|---|
|||**3dB BW**<br>**[Hz]**|**NBW [Hz]**|**Rate [Hz]**|
|0<br>~~es~~|x|12106|12316|9000|
|1<br>~~es~~<br>~~a~~|0<br>~~ee~~|196.6<br>~~ee~~|229.8|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255|
|1<br>~~a~~<br>~~en~~|1<br>~~ee~~<br>~~en~~|151.8<br>~~ee~~<br>~~en~~|187.6<br>~~en~~|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255<br>~~en~~|
|1<br>~~a~~<br>~~es~~|2<br>~~ee~~<br>~~es~~|119.5<br>~~ee~~|154.3|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255|
|1<br>~~es~~|3<br>~~es~~|51.2|73.3|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255|
|1<br>~~es ~~<br>~~en~~|4<br> ~~es~~<br>~~en~~|23.9<br>~~en~~|35.9<br>~~en~~|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255<br>~~en~~|
|1<br>~~a~~<br>~~es~~|5<br>~~ee~~<br>~~es~~|11.6<br>~~ee~~|17.8|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255|
|1<br>~~a~~<br>~~es~~|6<br>~~ee~~<br>~~es~~|5.7<br>~~ee~~|8.9|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255|
|1<br>~~es ~~<br>~~ee~~|7<br> ~~es~~<br>~~ee~~|361.4<br>~~ee~~|376.5<br>~~ee~~|1125/(1+GYRO_SMPLRT_DIV)Hz where<br>GYRO_SMPLRT_DIV is 0,1,2,…255<br>~~ee~~|
TDK InvenSense
_**ICM-20648**_
## **14.3 GYRO_CONFIG_2**
**Name: GYRO_CONFIG_2 Address: 2 (02h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00**
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5|XGYRO_CTEN|X Gyro self-test enable|
|4|YGYRO_CTEN|Y Gyro self-test enable|
|3|ZGYRO_CTEN|Z Gyro self-test enable|
|2:0|GYRO_AVGCFG[2:0]|Averaging filter configuration settings for low-power mode|
|||0: 1x averaging|
|||1: 2x averaging|
|||2: 4x averaging|
|||3: 8x averaging|
|||4: 16x averaging|
|||5: 32x averaging|
|||6: 64x averaging|
|||7: 128x averaging|
The following table lists the gyroscope filter bandwidths available in the low-power mode of operation. In the low-power mode of operation, the gyroscope is duty-cycled.
||**Averages**<br>~~ps~~|**1x**<br>~~ps~~<br>~~|~~|**2x**<br>~~|~~|**4x**<br>~~rT~~|**8x**<br>~~rT~~|**16x**<br>|**32x**<br>|**64x**<br>|**128x**<br>|
|---|---|---|---|---|---|---|---|---|---|
||**GYRO_FCHOICE**<br>~~ps~~|1<br>~~ps~~<br>~~|~~|1<br>~~|~~|1<br>~~rT~~|1<br>~~rT|~~|1<br>~~|~~|1<br>~~|~~|1<br>~~|~~|1<br>~~|~~|
||**GYRO_AVGCFG**<br>~~ps~~|0<br>~~ps~~<br>~~|~~<br>~~eee~~<br>~~a~~|1<br>~~|~~<br>~~eee~~<br>~~ee~~|2<br>~~rT~~<br>~~eee~~<br>~~ee~~|3<br>~~rT|~~<br>~~eee~~<br>~~ee~~|4<br>~~|~~<br>~~eee~~<br>~~ee~~|5<br>~~|~~<br>~~eee~~<br>~~ee~~|6<br>~~|~~<br>~~eee~~<br>~~ee~~|7<br>~~|~~<br>~~eee~~<br>~~ee~~|
||**Ton [ms]**|1.15<br>~~a~~|1.59<br>~~ee~~|2.48<br>~~ee~~|4.26<br>~~ee~~|7.82<br>~~ee~~|14.93<br>~~ee~~|29.15<br>~~ee~~|57.59<br>~~ee~~|
||**NBW [Hz]**|773.5<br>~~a~~|469.8<br>~~ee ~~|257.8<br> ~~ee~~<br>~~tt~~|134.8<br>~~ee~~<br>~~tt~~|68.9<br>~~ee~~<br>~~tt|~~|34.8<br>~~ee~~<br>~~|~~|17.5<br>~~ee~~<br>~~|~~|8.8<br>~~ee~~<br>~~|~~|
||**RMS Noise**<br>**[dps-rms] TYP**<br>**(based on gyroscope**<br>**noise: 0.011dps/√Hz)**|0.31<br>~~ptt~~|0.24<br>~~ptt~~|0.18<br>~~ptt~~<br>~~tt~~|0.13<br>~~ptt~~<br>~~tt~~|0.09<br>~~ptt~~<br>~~tt|~~|0.06<br>~~ptt~~<br>~~|~~|0.05<br>~~ptt~~<br>~~|~~|0.03<br>~~ptt~~<br>~~|~~|
|**GYRO_SMPLRT_DIV**|**ODR [Hz]**|**Current Consumption [mA] TYP**<br>~~tt | |~~||||||||
|255<br>~~pO~~<br>~~PC~~|4.4<br>~~pO~~|1.04<br>~~pO~~|1.05<br>~~pO~~|1.05<br>~~pO~~|1.06<br>~~pO~~|1.09<br>~~pO~~|1.14<br>~~pO~~|1.24<br>~~pO~~|1.45<br>~~pO~~|
|64<br>~~PC~~<br>~~Po~~<br>~~rrr—(_i~~|17.3<br>~~rrr—(_i~~|1.07|1.08|1.10|1.15|1.25|1.45|1.85|N/A|
|63<br>~~PC~~<br>~~Po~~<br>~~rrr—(_i~~|17.6<br>~~rrr—(_i~~|1.07|1.08|1.11|1.16|1.26|1.46|1.87||
|32<br>~~Po~~<br>~~rrr—(_i~~<br>~~pO~~<br>~~PcCU~~|34.1<br>~~rrr—(_i~~<br>~~pO~~<br>~~CU~~|1.10<br>~~pO~~|1.12<br>~~pO~~|1.17<br>~~pO~~|1.27<br>~~pO~~|1.47<br>~~pO~~|1.86<br>~~pO~~|N/A||
|31<br>~~PcCU~~|35.2<br>~~CU~~|1.10|1.13|1.18|1.28|1.48|1.89|||
|22<br>~~Pc CU~~<br>~~pO~~|48.9<br>~~CU~~<br>~~pO~~<br>~~ss~~|1.13<br>~~pO~~<br>~~ss~~|1.16<br>~~pO~~|1.23<br>~~pO~~|1.37<br>~~pO~~|1.66<br>~~pO~~|2.22<br>~~pO~~|||
|16<br>~~es~~|66.2<br>~~es~~<br>~~ss~~<br>~~ss~~|1.16<br>~~es~~<br>~~ss~~<br>~~ss~~|1.21<br>~~es~~<br>~~Gs~~|1.30<br>~~es~~<br>~~Gs~~|1.49<br>~~es~~|1.88<br>~~es~~|N/A|||
|15<br>~~es~~|70.3<br>~~ss~~<br>~~es~~<br>~~ss~~|1.17<br>~~ss~~<br>~~es~~<br>~~ss~~|1.22<br>~~es~~<br>~~Gs~~|1.32<br>~~es~~<br>~~Gs~~|1.52<br>~~es~~|1.93<br>~~es~~||||
|10<br>~~ss~~<br>~~es~~|102.3<br>~~ss~~<br>~~ss~~<br>~~ss~~|1.23<br>~~ss~~<br>~~ss~~<br>~~ss~~|1.30<br>~~Gs~~<br>~~ss~~|1.45<br>~~Gs~~<br>~~ss~~|1.74<br>~~ss~~|2.34<br>~~ss~~||||
|8<br>~~ss~~<br>~~es~~|125.0<br>~~ss~~<br>~~ss~~|1.27<br>~~ss~~<br>~~ss~~|1.36<br>~~ss~~|1.54<br>~~ss~~|1.90<br>~~ss~~|N/A<br>~~ss~~||||
|7<br>~~es~~<br>~~ss~~|140.6<br>~~ss~~<br>~~ss~~|1.30<br>~~ss~~<br>~~ss~~|1.40<br>~~ss~~|1.60<br>~~ss~~|2.01<br>~~ss~~|||||
|5<br>~~ss~~<br>~~er~~|187.5<br>~~ss~~<br>~~er~~|1.38<br>~~ss~~<br>~~er~~|1.52<br>~~ss~~<br>~~er~~|1.79<br>~~ss~~<br>~~er~~|2.33<br>~~ss~~<br>~~er~~|||||
|4<br>~~es~~|225.0<br>~~es~~|1.45<br>~~es~~|1.62<br>~~es~~|1.94<br>~~es~~|N/A|||||
|3<br>~~es~~<br>~~rr~~|281.3<br>~~es~~<br>~~rr~~|1.56<br>~~es~~<br>~~rr~~|1.76<br>~~es~~<br>~~rr~~|2.17<br>~~es~~<br>~~rr~~||||||
|2<br>~~es~~|375.0<br>~~es~~|1.74<br>~~es~~|2.00<br>~~es~~|N/A||||||
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1 562.5 2.09 N/A **Note** : Ton is the ON time for motion measurement when the gyroscope is in duty cycle mode. **14.4 XG_OFFS_USRH Name: XG_OFFS_USRH Address: 3 (03h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 X_OFFS_USER[15:8] Upper byte of X gyro offset cancellation **14.5 XG_OFFS_USRL Name: XG_OFFS_USRL Address: 4 (04h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 X_OFFS_USER[7:0] Lower byte of X gyro offset cancellation **14.6 YG_OFFS_USRH Name: YG_OFFS_USRH Address: 5 (05h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 Y_OFFS_USER[15:8] Upper byte of Y gyro offset cancellation **14.7 YG_OFFS_USRL Name: YG_OFFS_USRL Address: 6 (06h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~a~~ 7:0 Y_OFFS_USER[7:0] Lower byte of Y gyro offset cancellation **14.8 ZG_OFFS_USRH Name: ZG_OFFS_USRH Address: 7 (07h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~——~~ 7:0 Z_OFFS_USER[15:8] Upper byte of Z gyro offset cancellation **14.9 ZG_OFFS_USRL Name: ZG_OFFS_USRL Address: 8 (08h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** ~~ee~~
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7:0 Z_OFFS_USER[7:0] Lower byte of Z gyro offset cancellation ~~a~~
## **14.10 ODR_ALIGN_EN**
**Name: ODR_ALIGN_EN Address: 9 (09h) Type: USR2 Bank: 2 OTP: No Serial IF: R/W Reset Value: 0x00**
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:1|-|Reserved|
|0|ODR_ALIGN_EN|0: Disables ODR start-time alignment|
|||1: Enables ODR start-time alignment when any of the following registers is written|
|||(with the same value or with different values): GYRO_SMPLRT_DIV,|
|||ACCEL_SMPLRT_DIV_1,ACCEL_SMPLRT_DIV_2,I2C_MST_ODR_CONFIG|
## **14.11 ACCEL_SMPLRT_DIV_1**
|**14.11 ACCEL_SMPLRT_DIV_1_SMPLRT_DIV_1SMPLRT_DIV_1_DIV_1DIV_1_11 **||
|---|---|
|**Name: ACCEL_SMPLRT_DIV_1**||
|**Address: 16 (10h)**||
|**Type: USR2**||
|**Bank: 2**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:4<br>-|Reserved|
|3:0<br>ACCEL_SMPLRT_DIV[11:8]|MSB for ACCEL sample rate div|
## **14.12 ACCEL_SMPLRT_DIV_2**
|**14.12 ACCEL_SMPLRT_DIV_2_SMPLRT_DIV_2SMPLRT_DIV_2_DIV_2DIV_2_22 **||
|---|---|
|**Name: ACCEL_SMPLRT_DIV_2**||
|**Address: 17 (11h)**||
|**Type: USR2**||
|**Bank: 2**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>ACCEL_SMPLRT_DIV[7:0]|LSB for ACCEL sample rate div|
||ODR is computed as follows:|
||1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0])|
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## **14.13 ACCEL_INTEL_CTRL**
|**14.13 ACCEL_INTEL_CTRL_INTEL_CTRLINTEL_CTRL_CTRLCTRL**|**14.13 ACCEL_INTEL_CTRL_INTEL_CTRLINTEL_CTRL_CTRLCTRL**|**14.13 ACCEL_INTEL_CTRL_INTEL_CTRLINTEL_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: ACCEL_INTEL_CTRL**<br>**Address: 18 (12h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:2|-|Reserved|
|1|ACCEL_INTEL_EN|Enable the WOM logic|
|0|ACCEL_INTEL_MODE_INT|Selects WOM algorithm<br>1 = Compare the current sample with the previous sample.<br>0 = Initial sample is stored,all future samples are compared to the initial sample|
## **14.14 ACCEL_WOM_THR**
|**14.14 ACCEL_WOM_THR_WOM_THRWOM_THR_THRTHR**|**14.14 ACCEL_WOM_THR_WOM_THRWOM_THR_THRTHR**|**14.14 ACCEL_WOM_THR_WOM_THRWOM_THR_THRTHR**|
|---|---|---|
|**Name: ACCEL_WOM_THR**<br>**Address: 19 (13h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|WOM_THRESHOLD[7:0]|This register holds the threshold value for the Wake on Motion Interrupt for ACCEL<br>x/y/z axes. LSB = 4 mg. Range is 0 mgto 1020 mg|
## **14.15 ACCEL_CONFIG**
**Name: ACCEL_CONFIG Address: 20 (14h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x01**
|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|7:6|-|Reserved|
|5:3|ACCEL_DLPFCFG[2:0]|Accelerometer lowpass filter configuration as shown in the table below|
|2:1|ACCEL_FS_SEL[1:0]|Accelerometer Full Scale Select:|
|||00: ±2_g_|
|||01: ±4_g_|
|||10: ±8_g_|
|||11: ±16_g_|
|0|ACCEL_FCHOICE|0: bypass accel DLPF|
|||1: enable accel DLPF|
|**ACCEL_FCHOICE**|**ACCEL_DLPFCFG**|**Output**|**Output**|**Output**|
|---|---|---|---|---|
|||**3dB**<br>**BW**<br>**[Hz]**|**NBW [Hz]**|**Rate [Hz]**|
|0|x|1209|1248|4500|
|1|0|246.0|265.0|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
|1|1|246.0|265.0|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
|1|2|111.4|136.0|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
|1|3|50.4|68.8|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
|1|4|23.9|34.4|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
|1|5|11.5|17.0|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
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|**ACCEL_FCHOICE**|**ACCEL_DLPFCFG**|**Output**|**Output**|**Output**|
|---|---|---|---|---|
|||**3dB**<br>**BW**<br>**[Hz]**|**NBW [Hz]**|**Rate [Hz]**|
|1|6|5.7|8.3|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
|1|7|473|499|1125/(1+ACCEL_SMPLRT_DIV)Hz where<br>ACCEL_SMPLRT_DIV is 0,1,2,…4095|
The data rate out of the DLPF filter block can be further reduced by a factor of 1.125 kHz/(1+ACCEL_SMPLRT_DIV[11:0]) where ACCEL_SMPLRT_DIV is a 12-bit integer.
## **14.16 ACCEL_CONFIG_2**
|**Name: ACCEL_CONFIG_2**<br>**Address: 21 (15h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|**Name: ACCEL_CONFIG_2**<br>**Address: 21 (15h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|**Name: ACCEL_CONFIG_2**<br>**Address: 21 (15h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:5|-|Reserved|
|4|AX_ST_EN_REG|X Accel self-test enable|
|3|AY_ST_EN_REG|Y Accel self-test enable|
|2|AZ_ST_EN_REG|Z Accel self-test enable|
|1:0|DEC3_CFG[1:0]|Controls the number of samples averaged in the accelerometer decimator:<br>0: average 1 or 4 samples depending on ACCEL_FCHOICE (see table below)<br>1: average 8 samples<br>2: average 16 samples<br>3: average 32 samples|
The following table lists the accelerometer filter bandwidths available in the low-power mode of operation. In the low-power mode of operation, the accelerometer is duty-cycled.
||**Averages**<br>~~pF~~|**1x**<br>~~pF~~|**4x**|**8x**|**16x**|**32x**|
|---|---|---|---|---|---|---|
||**ACCEL_FCHOICE**<br>~~pF~~|0<br>~~pF~~<br>|<br>~~ee~~|1<br>|<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|1<br>~~ee~~|
||**ACCEL_DLPFCFG**<br>~~pF~~|x<br>~~pF~~<br>~~ee~~|7<br>~~ee~~|7<br>~~ee~~|7<br>~~ee~~|7<br>~~ee~~|
||**DEC3_CFG**|0<br>~~ee~~<br>~~a~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|2<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~|
||**Ton (ms)**|0.821<br>~~a~~<br>~~ee~~|1.488<br>~~ee~~|2.377<br>~~ee~~|4.154<br>~~ee~~|7.71<br>~~ee~~|
||**NBW (Hz)**|1237.5<br>~~ee~~|496.8<br>~~ee~~<br>~~|~~|264.8<br>~~ee~~<br>~~||~~|136.5<br>~~ee~~<br>~~| |~~|69.2<br>~~ee~~<br>~~|~~|
||**RMS Noise**<br>**[mg-rms] TYP**<br>**(based on accelerometer**<br>**noise: 190µg/√Hz)**|6.7<br>~~P|~~|4.2<br>~~P|~~<br>~~|~~|3.1<br>~~P|~~<br>~~||~~|2.2<br>~~P|~~<br>~~| |~~|1.6<br>~~P|~~<br>~~|~~|
|**ACCEL_SMPLRT_DIV**|**ODR [Hz]**|**Current Consumption [µA] TYP**<br>~~P|~~<br>~~| | |~~|||||
|4095<br>~~eG~~|0.27<br>~~eG~~|6.2<br>~~eG~~|6.3<br>~~eG~~|6.5<br>~~eG~~|6.9<br>~~eG~~|7.6<br>~~eG~~|
|2044<br>~~eG~~|0.55<br>~~eG~~<br>~~(~~|6.3<br>~~eG~~<br>~~G~~|6.6<br>~~eG~~<br>~~G~~|7.0<br>~~eG~~|7.7<br>~~eG~~|9.2<br>~~eG~~|
|1022<br>~~es~~|1.1<br>~~es~~<br>~~(~~|6.7<br>~~es~~<br>~~G~~|7.2<br>~~es~~<br>~~G~~|8.0<br>~~es~~|9.4<br>~~es~~|12.3<br>~~es~~|
|513<br>~~eG~~|2.2<br>~~(~~<br>~~eG~~<br>~~(~~|7.3<br>~~G~~<br>~~eG~~<br>~~G~~|8.4<br>~~G~~<br>~~eG~~<br>~~G~~|9.9<br>~~eG~~|12.8<br>~~eG~~|18.6<br>~~eG~~|
|255<br>~~es~~|4.4<br>~~es~~<br>~~(~~|8.7<br>~~es~~<br>~~G~~|10.9<br>~~es~~<br>~~G~~|13.8<br>~~es~~|19.7<br>~~es~~|31.4<br>~~es~~|
|127<br>~~es~~<br>~~nO~~|8.8<br>~~es~~<br>~~(~~<br>~~nO~~|11.4<br>~~es~~<br>~~G~~<br>~~nO~~|15.8<br>~~es~~<br>~~G~~<br>~~nO~~|21.6<br>~~es~~<br>~~nO~~|33.3<br>~~es~~<br>~~nO~~|56.7<br>~~es~~<br>~~nO~~|
|63<br>~~eG~~|17.6<br>~~eG~~<br>~~(~~|16.8<br>~~eG~~<br>~~G~~|25.6<br>~~eG~~<br>~~G~~|37.3<br>~~eG~~|60.7<br>~~eG~~|107.5<br>~~eG~~|
|31<br>~~es~~|35.2<br>~~es~~<br>~~(~~|27.6<br>~~es~~<br>~~G~~|45.2<br>~~es~~<br>~~G~~|68.6<br>~~es~~|115.3<br>~~es~~|208.9<br>~~es~~|
|22<br>~~es~~<br>~~eG~~<br>~~Or~~|48.9<br>~~es~~<br>~~(~~<br>~~eG~~|36.1<br>~~es~~<br>~~G~~<br>~~eG~~|60.5<br>~~es~~<br>~~G~~<br>~~eG~~|93.0<br>~~es~~<br>~~eG~~|158.1<br>~~es~~<br>~~eG~~|288.3<br>~~es~~<br>~~eG~~|
|15<br>~~Or~~|70.3|49.2|84.3|131.1|224.7|411.9|
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|10|102.3|68.9|119.9|188.0|324.1|596.3|
|---|---|---|---|---|---|---|
|7|140.6|92.4|162.7|256.3|443.3|N/A|
|5|187.5|121.2|214.9||||
|3|281.3|178.9|319.3|N/A|||
|1|562.5|351.7|N/A||||
**Note** : Ton is the ON time for motion measurement when the accelerometer is in duty cycle mode.
## **14.17 FSYNC_CONFIG**
|**14.17 FSYNC_CONFIG_CONFIGCONFIG**|**14.17 FSYNC_CONFIG_CONFIGCONFIG**|**14.17 FSYNC_CONFIG_CONFIGCONFIG**|
|---|---|---|
|**Name: FSYNC_CONFIG**<br>**Address: 82 (52h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|DELAY_TIME_EN|0: Disables delay time measurement between FSYNC event and the first ODR event<br>(after FSYNC event)<br>1: Enables delay time measurement between FSYNC event and the first ODR event<br>(after FSYNC event)|
|6|-|Reserved|
|5|WOF_DEGLITCH_EN|Enable digital deglitchingof FSYNC input for Wake on FSYNC|
|4|WOF_EDGE_INT|0: FSYNC is a level interrupt for Wake on FSYNC<br>1: FSYNC is an edge interrupt for Wake on FSYNC<br>ACTL_FSYNC is used to set thepolarityof the interrupt|
|3:0|EXT_SYNC_SET[3:0]|Enables the FSYNC pin data to be sampled.<br>EXT_SYNC_SET FSYNC bit location<br>0: Function disabled<br>1: TEMP_OUT_L[0]<br>2: GYRO_XOUT_L[0]<br>3: GYRO_YOUT_L[0]<br>4: GYRO_ZOUT_L[0]<br>5: ACCEL_XOUT_L[0]<br>6: ACCEL_YOUT_L[0]<br>7: ACCEL_ZOUT_L[0]|
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## **14.18 TEMP_CONFIG**
**Name: TEMP_CONFIG Address: 83 (53h) Type: USR2 Bank: 2 Serial IF: R/W Reset Value: 0x00**
|**14.18 TEMP_CONFIG_CONFIGCONFIG**|**14.18 TEMP_CONFIG_CONFIGCONFIG**|**14.18 TEMP_CONFIG_CONFIGCONFIG**|
|---|---|---|
|**Name: TEMP_CONFIG**<br>**Address: 83 (53h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|2:0|TEMP_DLPFCFG[2:0]|Low pass filter configuration for temperature sensor as shown in the table below:<br>TEMP_DLPCFG<2:0><br>TempSensor<br>NBW(Hz)<br>Rate(kHz)<br>0<br>7932.0<br>9<br>1<br>217.9<br>1.125<br>2<br>123.5<br>1.125<br>3<br>65.9<br>1.125<br>4<br>34.1<br>1.125<br>5<br>17.3<br>1.125<br>6<br>8.8<br>Rate(kHz)<br>7<br>7932.0<br>9<br>~~——~~<br>~~———~~|
## **14.19 MOD_CTRL_USR**
|**Name: MOD_CTRL_USR**<br>**Address: 84 (54h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x03**|**Name: MOD_CTRL_USR**<br>**Address: 84 (54h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x03**|**Name: MOD_CTRL_USR**<br>**Address: 84 (54h)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x03**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:1|-|Reserved|
|0|REG_LP_DMP_EN|Enable turningon DMP in Low Power Accelerometer mode.|
## **14.20 REG_BANK_SEL**
|**Name: REG_BANK_SEL**<br>**Address: 127 (7Fh)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|**Name: REG_BANK_SEL**<br>**Address: 127 (7Fh)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|**Name: REG_BANK_SEL**<br>**Address: 127 (7Fh)**<br>**Type: USR2**<br>**Bank: 2**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|
|---|---|---|
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:4|USER_BANK[1:0]|Use the following values in this bit-field to select a USER BANK<br>0: Select USER BANK 0<br>1: Select USER BANK 1<br>2: Select USER BANK 2<br>3: Select USER BANK 3|
|3:0|-|Reserved|
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## _**15 USR BANK 3 REGISTER MAP – DESCRIPTIONS**_
This section describes the function and contents of each register within USR Bank 3.
**Note:** The device will come up in sleep mode upon power-up.
## **15.1 I2C_MST_ODR_CONFIG**
|**15.1 I2C_MST_ODR_CONFIG_MST_ODR_CONFIGMST_ODR_CONFIG_ODR_CONFIGODR_CONFIG_CONFIGCONFIG**|**15.1 I2C_MST_ODR_CONFIG_MST_ODR_CONFIGMST_ODR_CONFIG_ODR_CONFIGODR_CONFIG_CONFIGCONFIG**|**15.1 I2C_MST_ODR_CONFIG_MST_ODR_CONFIGMST_ODR_CONFIG_ODR_CONFIGODR_CONFIG_CONFIGCONFIG**|
|---|---|---|
|**Name: I2C_MST_ODR_CONFIG**<br>**Address: 0 (00h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:4|-|Reserved|
|3:0|I2C_MST_ODR_CONFIG[3:0]|ODR configuration for external sensor when gyroscope and accelerometer are<br>disabled. ODR is computed as follows:<br>1.1 kHz/(2^((odr_config[3:0])) )<br>When gyroscope is enabled, all sensors (including I2C_MASTER) use the gyroscope<br>ODR. If gyroscope is disabled then all sensors (including I2C_MASTER) use the<br>accelerometer ODR.|
## **15.2 I2C_MST_CTRL**
|**15.2 I2C_MST_CTRL_MST_CTRLMST_CTRL_CTRLCTRL**|**15.2 I2C_MST_CTRL_MST_CTRLMST_CTRL_CTRLCTRL**|**15.2 I2C_MST_CTRL_MST_CTRLMST_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_MST_CTRL**<br>**Address: 1 (01h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|MULT_MST_EN|Enables multi-master capability. When disabled, clocking to the I2C_MST_IF can be<br>disabled when not in use and the logic to detect lost arbitration is disabled.|
|6:5|-|Reserved|
|4|I2C_MST_P_NSR|This bit controls the I2C Master’s transition from one slave read to the next slave<br>read.<br>0 - there is a restart between reads.<br>1 - there is a stopbetween reads.|
|3:0|I2C_MST_CLK[3:0]|Sets I2C master clock frequencyas shown in the table below|
|I2C_MST_CLK<br>|<br>~~ee~~|Nominal CLK Frequency [kHz]<br>~~ee~~|Duty Cycle|
|---|---|---|
|0<br>|<br>~~ee~~<br>~~ee ee~~|370.29<br>~~ee~~<br>~~ee~~|50.00%|
|1<br>|<br>~~ee ~~<br>~~ee ee~~<br>~~ee ee~~|-<br> ~~ee~~<br>~~ee~~<br>~~ee~~|-|
|2<br>~~ee ee~~<br>~~ee ee~~<br>~~ee~~|370.29<br>~~ee~~<br>~~ee~~<br>~~ee~~|50.00%|
|3<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|432.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|50.00%|
|4<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~|370.29<br> ~~ee~~<br>~~ee~~<br>~~ee~~|42.86%|
|5<br>~~ee ~~<br>~~ee ee~~<br>~~ee~~|370.29<br> ~~ee~~<br>~~ee~~<br>~~ee~~|50.00%|
|6<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|345.60<br>~~ee~~<br>~~ee~~<br>~~ee~~|40.00%|
|7<br>~~ee ~~<br>~~ee ee~~<br>~~ee~~|345.60<br> ~~ee~~<br>~~ee~~<br>~~ee~~|46.67%|
|8<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~|304.94<br>~~ee~~<br>~~ee~~<br>~~ee~~|47.06%|
|9<br>~~ee ~~<br>~~ee ee~~<br>~~ee~~|432.00<br> ~~ee~~<br>~~ee~~<br>~~ee~~|50.00%|
|10<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|432.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|41.67%|
|11<br>~~ee ~~<br>~~ee~~<br>~~ee ee~~|432.00<br> ~~ee~~<br>~~ee~~<br>~~ee~~|41.67%|
|12<br>~~ee ~~<br>~~ee ee~~<br>~~ee~~|471.27<br> ~~ee~~<br>~~ee~~<br>~~ee~~|45.45%|
|13<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|432.00<br>~~ee~~<br>~~ee~~<br>~~ee~~|50.00%|
|14<br>~~ee ~~<br>~~ee~~|345.60<br> ~~ee~~<br>~~ee~~|46.67%|
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## ‘TDK InvenSense I2C_MST_CLK Nominal CLK Frequency [kHz] Duty Cycle 15 345.60 46.67% ~~ee~~
## **15.3 I2C_MST_DELAY_CTRL**
|**15.3 I2C_MST_DELAY_CTRL_MST_DELAY_CTRLMST_DELAY_CTRL_DELAY_CTRLDELAY_CTRL_CTRLCTRL**|**15.3 I2C_MST_DELAY_CTRL_MST_DELAY_CTRLMST_DELAY_CTRL_DELAY_CTRLDELAY_CTRL_CTRLCTRL**|**15.3 I2C_MST_DELAY_CTRL_MST_DELAY_CTRLMST_DELAY_CTRL_DELAY_CTRLDELAY_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_MST_DELAY_CTRL**<br>**Address: 2 (02h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|DELAY_ES_SHADOW|Delays shadowingof external sensor data until all data is received|
|6:5|-|Reserved|
|4|I2C_SLV4_DELAY_EN|When enabled, slave 4 will only be accessed 1/(1+I2C_SLC4_DLY) samples as<br>determined byI2C_MST_ODR_CONFIG|
|3|I2C_SLV3_DELAY_EN|When enabled, slave 3 will only be accessed 1/(1+I2C_SLC4_DLY) samples as<br>determined byI2C_MST_ODR_CONFIG|
|2|I2C_SLV2_DELAY_EN|When enabled, slave 2 will only be accessed 1/(1+I2C_SLC4_DLY) samples as<br>determined byI2C_MST_ODR_CONFIG|
|1|I2C_SLV1_DELAY_EN|When enabled, slave 1 will only be accessed 1/(1+I2C_SLC4_DLY) samples as<br>determined byI2C_MST_ODR_CONFIG|
|0|I2C_SLV0_DELAY_EN|When enabled, slave 0 will only be accessed 1/(1+I2C_SLC4_DLY) samples as<br>determined byI2C_MST_ODR_CONFIG|
## **15.4 I2C_SLV0_ADDR**
|**15.4 I2C_SLV0_ADDR_SLV0_ADDRSLV0_ADDR_ADDRADDR**||
|---|---|
|**Name: I2C_SLV0_ADDR**||
|**Address: 3 (03h)**||
|**Type: USR3**||
|**Bank: 3**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7<br>I2C_SLV0_RNW|1 – Transfer is a read|
||0 – Transfer is a write|
|6:0<br>I2C_ID_0[6:0]|Physical address of I2C slave 0|
## **15.5 I2C_SLV0_REG**
|**15.5 I2C_SLV0_REG_SLV0_REGSLV0_REG_REGREG**|**15.5 I2C_SLV0_REG_SLV0_REGSLV0_REG_REGREG**|**15.5 I2C_SLV0_REG_SLV0_REGSLV0_REG_REGREG**|
|---|---|---|
|**Name: I2C_SLV0_REG**<br>**Address: 4 (04h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2C_SLV0_REG[7:0]|I2C slave 0 register address from where to begin data transfer|
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## **15.6 I2C_SLV0_CTRL**
**Name: I2C_SLV0_CTRL Address: 5 (05h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00**
|**15.6 I2C_SLV0_CTRL_SLV0_CTRLSLV0_CTRL_CTRLCTRL**|**15.6 I2C_SLV0_CTRL_SLV0_CTRLSLV0_CTRL_CTRLCTRL**|**15.6 I2C_SLV0_CTRL_SLV0_CTRLSLV0_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_SLV0_CTRL**<br>**Address: 5 (05h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|I2C_SLV0_EN|1 – Enable reading data from this slave at the sample rate and storing data at the first<br>available EXT_SENS_DATA register, which is always EXT_SENS_DATA_00 for I2C slave 0.<br>0 – function is disabled for this slave|
|6|I2C_SLV0_BYTE_SW|1 – Swap bytes when reading both the low and high byte of a word. Note there is<br>nothing to swap after reading the first byte if I2C_SLV0_REG[0] = 1, or if the last byte<br>read has a register address lsb = 0.<br>For example, if I2C_SLV0_REG = 0x1, and I2C_SLV0_LENG = 0x4:<br>1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_00,<br>2) the second and third bytes will be read and swapped, so the data read from address<br>0x2 will be stored at EXT_SENS_DATA_02, and the data read from address 0x3 will be<br>stored at EXT_SENS_DATA_01,<br>3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_03<br>0 – no swappingoccurs,bytes are written in order read.|
|5|I2C_SLV0_REG_DIS|When set, the transaction does not write a register value, it will only read data, or<br>write data|
|4|I2C_SLV0_GRP|External sensor data typically comes in as groups of two bytes. This bit is used to<br>determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc., or if<br>the groups are address 1 and 2, 3 and 4, etc.<br>0 indicates slave register addresses 0 and 1 are grouped together (odd numbered<br>register ends the group). 1 indicates slave register addresses 1 and 2 are grouped<br>together (even numbered register ends the group). This allows byte swapping of<br>registers that aregrouped startingat anyaddress.|
|3:0|I2C_SLV0_LENG[3:0]|Number of bytes to be read from I2C slave 0|
## **15.7 I2C_SLV0_DO**
**Name: I2C_SLV0_DO Address: 6 (06h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV0_DO[7:0] Data out when slave 0 is set to write
## **15.8 I2C_SLV1_ADDR**
|**15.8 I2C_SLV1_ADDR_SLV1_ADDRSLV1_ADDR_ADDRADDR**||
|---|---|
|**Name: I2C_SLV1_ADDR**||
|**Address: 7 (07h)**||
|**Type: USR3**||
|**Bank: 3**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7<br>I2C_SLV1_RNW|1 – Transfer is a read|
||0 – Transfer is a write|
|6:0<br>I2C_ID_1[6:0]|Physical address of I2C slave 1|
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## **15.9 I2C_SLV1_REG**
**Name: I2C_SLV1_REG Address: 8 (08h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV1_REG[7:0] I[2] C slave 1 register address from where to begin data transfer
## **15.10 I2C_SLV1_CTRL**
|**15.10 I2C_SLV1_CTRL_SLV1_CTRLSLV1_CTRL_CTRLCTRL**|**15.10 I2C_SLV1_CTRL_SLV1_CTRLSLV1_CTRL_CTRLCTRL**|**15.10 I2C_SLV1_CTRL_SLV1_CTRLSLV1_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_SLV1_CTRL**<br>**Address: 9 (09h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|I2C_SLV1_EN|1 – Enable reading data from this slave at the sample rate and storing data at the first<br>available EXT_SENS_DATA register as determined by I2C_SLV0_EN and<br>I2C_SLV0_LENG.<br>0 – function is disabled for this slave|
|6|I2C_SLV1_BYTE_SW|1 – Swap bytes when reading both the low and high byte of a word. Note there is<br>nothing to swap after reading the first byte if I2C_SLV1_REG[0] = 1, or if the last byte<br>read has a register address lsb = 0.<br>For example, if I2C_SLV0_EN = 0x1, and I2C_SLV0_LENG = 0x3 (to show swap has to<br>do with I2C slave address not EXT_SENS_DATA address), and if I2C_SLV1_REG = 0x1,<br>and I2C_SLV1_LENG = 0x4:<br>1) The first byte read from address 0x1 will be stored at EXT_SENS_DATA_03 (slave<br>0’s data will be in EXT_SENS_DATA_00, EXT_SENS_DATA_01, and<br>EXT_SENS_DATA_02),<br>2) the second and third bytes will be read and swapped, so the data read from<br>address 0x2 will be stored at EXT_SENS_DATA_04, and the data read from address<br>0x3 will be stored at EXT_SENS_DATA_05,<br>3) The last byte read from address 0x4 will be stored at EXT_SENS_DATA_06<br>0 – no swappingoccurs,bytes are written in order read.|
|5|I2C_SLV1_REG_DIS|When set, the transaction does not write a register value, it will only read data, or<br>write data|
|4|I2C_SLV1_GRP|External sensor data typically comes in as groups of two bytes. This bit is used to<br>determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc., or<br>if the groups are address 1 and 2, 3 and 4, etc.<br>0 indicates slave register addresses 0 and 1 are grouped together (odd numbered<br>register ends the group). 1 indicates slave register addresses 1 and 2 are grouped<br>together (even numbered register ends the group). This allows byte swapping of<br>registers that aregrouped startingat anyaddress.|
|3:0|I2C_SLV1_LENG[3:0]|Number of bytes to be read from I2C slave 1|
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## **15.11 I2C_SLV1_DO**
**Name: I2C_SLV1_DO Address: 10 (0Ah) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV1_DO[7:0] Data out when slave 1 is set to write
## **15.12 I2C_SLV2_ADDR**
|**15.12 I2C_SLV2_ADDR_SLV2_ADDRSLV2_ADDR_ADDRADDR**||
|---|---|
|**Name: I2C_SLV2_ADDR**||
|**Address: 11 (0Bh)**||
|**Type: USR3**||
|**Bank: 3**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7<br>I2C_SLV2_RNW|1 – Transfer is a read|
||0 – Transfer is a write|
|6:0<br>I2C_ID_2[6:0]|Physical address of I2C slave 2|
## **15.13 I2C_SLV2_REG**
|**15.13 I2C_SLV2_REG_SLV2_REGSLV2_REG_REGREG**|**15.13 I2C_SLV2_REG_SLV2_REGSLV2_REG_REGREG**|**15.13 I2C_SLV2_REG_SLV2_REGSLV2_REG_REGREG**|
|---|---|---|
|**Name: I2C_SLV2_REG**<br>**Address: 12 (0Ch)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:0|I2C_SLV2_REG[7:0]|I2C slave 2 register address from where to begin data transfer|
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## **15.14 I2C_SLV2_CTRL**
**Name: I2C_SLV2_CTRL Address: 13 (0Dh) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00**
|**15.14 I2C_SLV2_CTRL_SLV2_CTRLSLV2_CTRL_CTRLCTRL**|**15.14 I2C_SLV2_CTRL_SLV2_CTRLSLV2_CTRL_CTRLCTRL**|**15.14 I2C_SLV2_CTRL_SLV2_CTRLSLV2_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_SLV2_CTRL**<br>**Address: 13 (0Dh)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|I2C_SLV2_EN|1 – Enable reading data from this slave at the sample rate and storing data at the first<br>available EXT_SENS_DATA register as determined by I2C_SLV0_EN, I2C_SLV0_LENG,<br>I2C_SLV1_EN and I2C_SLV1_LENG.<br>0 – function is disabled for this slave|
|6|I2C_SLV2_BYTE_SW|1 – Swap bytes when reading both the low and high byte of a word. Note there is<br>nothing to swap after reading the first byte if I2C_SLV2_REG[0] = 1, or if the last byte<br>read has a register address lsb = 0.<br>See I2C_SLV1_CTRL for an example.<br>0 – no swappingoccurs,bytes are written in order read.|
|5|I2C_SLV2_REG_DIS|When set, the transaction does not write a register value, it will only read data, or<br>write data|
|4|I2C_SLV2_GRP|External sensor data typically comes in as groups of two bytes. This bit is used to<br>determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc., or<br>if the groups are address 1 and 2, 3 and 4, etc.<br>0 indicates slave register addresses 0 and 1 are grouped together (odd numbered<br>register ends the group). 1 indicates slave register addresses 1 and 2 are grouped<br>together (even numbered register ends the group). This allows byte swapping of<br>registers that aregrouped startingat anyaddress.|
|3:0|I2C_SLV2_LENG[3:0]|Number of bytes to be read from I2C slave 2|
## **15.15 I2C_SLV2_DO**
**Name: I2C_SLV2_DO Address: 14 (0Eh) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV2_DO[7:0] Data out when slave 2 is set to write
## **15.16 I2C_SLV3_ADDR**
|**15.16 I2C_SLV3_ADDR_SLV3_ADDRSLV3_ADDR_ADDRADDR**||
|---|---|
|**Name: I2C_SLV3_ADDR**||
|**Address: 15 (0Fh)**||
|**Type: USR3**||
|**Bank: 3**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7<br>I2C_SLV3_RNW|1 – Transfer is a read|
||0 – Transfer is a write|
|6:0<br>I2C_ID_3[6:0]|Physical address of I2C slave 3|
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## **15.17 I2C_SLV3_REG**
**Name: I2C_SLV3_REG Address: 16 (10h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV3_REG[7:0] I[2] C slave 3 register address from where to begin data transfer
## **15.18 I2C_SLV3_CTRL**
|**15.18 I2C_SLV3_CTRL_SLV3_CTRLSLV3_CTRL_CTRLCTRL**|**15.18 I2C_SLV3_CTRL_SLV3_CTRLSLV3_CTRL_CTRLCTRL**|**15.18 I2C_SLV3_CTRL_SLV3_CTRLSLV3_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_SLV3_CTRL**<br>**Address: 17 (11h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|I2C_SLV3_EN|1 – Enable reading data from this slave at the sample rate and storing data at the first<br>available EXT_SENS_DATA register as determined by I2C_SLV0_EN, I2C_SLV0_LENG,<br>I2C_SLV1_EN, I2C_SLV1_LENG, I2C_SLV2_EN and I2C_SLV2_LENG.<br>0 – function is disabled for this slave|
|6|I2C_SLV3_BYTE_SW|1 – Swap bytes when reading both the low and high byte of a word. Note there is<br>nothing to swap after reading the first byte if I2C_SLV3_REG[0] = 1, or if the last byte<br>read has a register address lsb = 0.<br>See I2C_SLV1_CTRL for an example.<br>0 – no swappingoccurs,bytes are written in order read.|
|5|I2C_SLV3_REG_DIS|When set, the transaction does not write a register value, it will only read data, or<br>write data|
|4|I2C_SLV3_GRP|External sensor data typically comes in as groups of two bytes. This bit is used to<br>determine if the groups are from the slave’s register address 0 and 1, 2 and 3, etc., or<br>if the groups are address 1 and 2, 3 and 4, etc.<br>0 indicates slave register addresses 0 and 1 are grouped together (odd numbered<br>register ends the group). 1 indicates slave register addresses 1 and 2 are grouped<br>together (even numbered register ends the group). This allows byte swapping of<br>registers that aregrouped startingat anyaddress.|
|3:0|I2C_SLV3_LENG[3:0]|Number of bytes to be read from I2C slave 3|
## **15.19 I2C_SLV3_DO**
**Name: I2C_SLV3_DO Address: 18 (12h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV3_DO[7:0] Data out when slave 3 is set to write
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## **15.20 I2C_SLV4_ADDR**
|**15.20 I2C_SLV4_ADDR_SLV4_ADDRSLV4_ADDR_ADDRADDR**||
|---|---|
|**Name: I2C_SLV4_ADDR**||
|**Address: 19 (13h)**||
|**Type: USR3**||
|**Bank: 3**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7<br>I2C_SLV4_RNW|1 – Transfer is a read|
||0 – Transfer is a write|
|6:0<br>I2C_ID_4[6:0]|Physical address of I2C slave 4|
**Note** : The I[2] C Slave 4 interface can be used to perform only single byte read and write transactions.
## **15.21 I2C_SLV4_REG**
**Name: I2C_SLV4_REG Address: 20 (14h) Type: USR3 Bank: 3 Serial IF: R/W Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV4_REG[7:0] I[2] C slave 4 register address from where to begin data transfer
## **15.22 I2C_SLV4_CTRL**
|**15.22 I2C_SLV4_CTRL_SLV4_CTRLSLV4_CTRL_CTRLCTRL**|**15.22 I2C_SLV4_CTRL_SLV4_CTRLSLV4_CTRL_CTRLCTRL**|**15.22 I2C_SLV4_CTRL_SLV4_CTRLSLV4_CTRL_CTRLCTRL**|
|---|---|---|
|**Name: I2C_SLV4_CTRL**<br>**Address: 21 (15h)**<br>**Type: USR3**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7|I2C_SLV4_EN|1 – Enable data transfer with this slave at the sample rate. If read command, store<br>data in I2C_SLV4_DI register, if write command, write data stored in I2C_SLV4_DO<br>register. Bit is cleared when a single transfer is complete. Be sure to write<br>I2C_SLV4_DO first<br>0 – function is disabled for this slave|
|6|I2C_SLV4_INT_EN|1 – Enables the completion of the I2C slave 4 data transfer to cause an interrupt.<br>0 – Completion of the I2C slave 4 data transfer will not cause an interrupt.|
|5|I2C_SLV4_REG_DIS|When set, the transaction does not write a register value, it will only read data, or<br>write data|
|4:0|I2C_SLV4_DLY[4:0]|When enabled via the I2C_MST_DELAY_CTRL, those slaves will only be enabled<br>every1/(1+I2C_SLV4_DLY)samples as determined byI2C_MST_ODR_CONFIG|
## **15.23 I2C_SLV4_DO**
|**15.23 I2C_SLV4_DO_SLV4_DOSLV4_DO_DODO**||
|---|---|
|**Name: I2C_SLV4_DO**||
|**Address: 22 (16h)**||
|**Type: USR3**||
|**Bank: 3**||
|**Serial IF: R/W**||
|**Reset Value: 0x00**||
|**BIT**<br>**NAME**|**FUNCTION**|
|7:0<br>I2C_SLV4_DO[7:0]|Data out when slave 4 is set to write|
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## **15.24 I2C_SLV4_DI**
**Name: I2C_SLV4_DI Address: 23 (17h) Type: USR3 Bank: 3 Serial IF: R Reset Value: 0x00 BIT NAME FUNCTION** 7:0 I2C_SLV4_DI[7:0] Data read from I[2] C Slave 4.
## **15.25 REG_BANK_SEL**
|**15.25 REG_BANK_SEL_BANK_SELBANK_SEL_SELSEL**|**15.25 REG_BANK_SEL_BANK_SELBANK_SEL_SELSEL**|**15.25 REG_BANK_SEL_BANK_SELBANK_SEL_SELSEL**|
|---|---|---|
|**Name: REG_BANK_SEL**<br>**Address: 127 (7Fh)**<br>**Type:**<br>**Bank: 3**<br>**Serial IF: R/W**<br>**Reset Value: 0x00**|||
|**BIT**|**NAME**|**FUNCTION**|
|7:6|-|Reserved|
|5:4|USER_BANK[1:0]|Use the following values in this bit-field to select a USER BANK<br>0: Select USER BANK 0<br>1: Select USER BANK 1<br>2: Select USER BANK 2<br>3: Select USER BANK 3|
|3:0|-|Reserved|
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## _**16 REFERENCE**_
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
- Manufacturing Recommendations
- Assembly Guidelines and Recommendations
- PCB Design Guidelines and Recommendations
- MEMS Handling Instructions
- ESD Considerations
- Reflow Specification
- Storage Specifications
- Package Marking Specification
- Tape & Reel Specification
- Reel & Pizza Box Label
- Packaging
- Representative Shipping Carton Label
- Compliance
- Environmental Compliance
- DRC Compliance
- Compliance Declaration Disclaimer
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## _**17 REVISION HISTORY**_
|**REVISION DATE**|**REVISION**|**DESCRIPTION**|
|---|---|---|
|10/26/2016|1.0|Initial Release|
|11/02/2016|1.1|Minor cosmetic changes|
|10/23/2017|1.2|Minor section one fix. Logo update.|
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This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2017 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective companies with which they are associated.
©2016—2017 InvenSense. All rights reserved.
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Updated at April 17, 2026
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