ICG-20660L

MEMS Module, Accelerometer, Gyroscope, X, Y, Z, 1.71 V, 3.45 V, LGA, 16 Pins

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Manufacturer: TDK INVENSENSE
Product type: MEMS Modules
Available until stocks are exhausted
MSL: MSL 3 - 168 hours
SVHC: No SVHC (15-Jun-2015)
No. of Pins: 16Pins
Sensor Type: Accelerometer, Gyroscope
Sensing Axis: X, Y, Z
Product Range: -
Output Interface: I2C, SPI
Sensor Case Style: LGA
Supply Voltage Max: 3.45V
Supply Voltage Min: 1.71V
MEMS Module Function: Tri-Axis Gyroscope, Tri-Axis Accelerometer
Sensor Case / Package: LGA
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Sensing Range - Gyroscope: ± 125°/s, ± 250°/s, ± 500°/s
Temperature Sensing Range: -
Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g, ± 16g
Delivery and price
Units per pack	500
Price	2.6 €
Current stock	1000+
Lead time	30 days
Datasheet
_**ICG-20660**_ 

## Hi h Performance 6-Axis OIS/EIS O timized MEMS Sensor g p 

## **GENERAL DESCRIPTION** 

The ICG-20660 is a 6-axis MotionTracking device that combines a 3-axis gyroscope, 3-axis accelerometer, in a small 3 mm x 3 mm x 0.75 mm (16-pin LGA) package. 

- High performance specs 

   - Gyroscope sensitivity error: ±3% 

   - Gyroscope noise: 6.5mdps/Hz 

- Includes 512-byte FIFO to reduce traffic on the serial bus interface, and reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode 

- EIS FSYNC support 

The ICG-20660 includes on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features an operating voltage range down to 1.71 V. Communication ports include I[2] C and high speed SPI at 7 MHz. 

## **ORDERING INFORMATION** 

|**PART**|**AXES**|**TEMP RANGE**|**PACKAGE**|
|---|---|---|---|
|ICG-20660†|X,Y,Z|-40°C to +85°C|16-Pin LGA|



†Denotes RoHS and Green-Compliant Package 

## **BLOCK DIAGRAM** 

## **APPLICATIONS** 

- OIS (Optical Image Stabilization) in phone camera modules, DSLR, and DSC 

- EIS (Electronic Image Stabilization) in DSC, and phone camera modules 

## **FEATURES** 

- ±3% Gyro initial sensitivity 

- 3-Axis optimized OIS/EIS programmable gyro FSR of ±125 dps, ±250 dps, ±500 dps, and ±250 dps 

- 3-Axis Accelerometer with Programmable FSR of 

   - ±2 _g_ , ±4 _g_ , ±8 _g_ , and ±16 _g_ 

- User-programmable interrupts 

- Wake-on-motion interrupt for low power operation of applications processor 

- 512-byte FIFO buffer enables the applications processor to read the data in bursts 

- On-Chip 16-bit ADCs and Programmable Filters 

- Host interface: 7 MHz SPI or 400 kHz Fast Mode I[2] C 

- Digital-output temperature sensor 

- VDD operating range of 1.71 V to 3.45 V 

- MEMS structure hermetically sealed and bonded at wafer level 

- RoHS and Green compliant 

## **TYPICAL OPERATING CIRCUIT** 

**==> picture [495 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
ICG-20660<br>INT<br>Self test X Accel ADC Interrupt RegisterStatus  CS 1.8 – 3.3VDCC2, 0.1 mF C4, 2.2 mFVDD REGOUT<br>Self test Y Accel ADC — FIFO Slave I2C and SPI Serial Interface [ 3 SA0 / SDOSCL / SPC 16 15 14 C1, 0.47 mF<br>Self test Z Accel ADC User & Config  SDA / SDI 1.8 – 3.3 VDC VDDIO 1 13 GND<br>GH =6=) - Self test : X Gyro =- AD C = RegistersRegistersSensor  ee— FSYNC C3, 10 nF : SCLSDA - SCL/SPCSDA/SDI 23 ICG-20660 1211 NCNC A<br>Self test Y Gyro ADC VDDIO AD0 SA0/SDOCS 54 109 NCNC<br>=BL} Self test a; Z Gyro AD C - 6 7 8<br>H Temp Sensor o ADC<br>Charge  Bias & LDOs<br>Pump<br>VDD GND REGOUT<br>RESV<br>Signal Conditioning<br>INT RESV FSYNC<br>**----- End of picture text -----**<br>


**InvenSense Inc.** 1745 Technology Drive, San Jose, CA 95110 U.S.A +1(408) 988–7339 www.invensense.com 

Document Number: DS-000135 Revision: 1.1 

InvenSense reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 

Rev. Date: 09/20/2016 

_**ICG-20660**_ 

## **TABLE OF CONTENTS** 

||**TABLE OF CONTENTS**|**TABLE OF CONTENTS**|
|---|---|---|
||GENERALDESCRIPTION.................................................................................................................................................................. 1||
||ORDERINGINFORMATION............................................................................................................................................................... 1||
||BLOCK|LOCKDIAGRAM.......................................................................................................................................................................... 1|
||APPLICATIONS.............................................................................................................................................................................. 1||
||FEATURES.................................................................................................................................................................................... 1||
||TYPICALOPERATINGCIRCUIT.......................................................................................................................................................... 1||
|**TABLE OF CONTENTS ........................................................................................................................................................... 2**|||
|**LIST OF FIGURES .................................................................................................................................................................. 5**|||
|**LIST OF TABLES .................................................................................................................................................................... 6**|||
|**1**|**INTRODUCTION ............................................................................................................................................................ 7**||
||1.1|PURPOSE AND SCOPE ................................................................................................................................................... 7|
||1.2|PRODUCTOVERVIEW......................................................................................................................................................... 7|
||1.3|APPLICATIONS.................................................................................................................................................................. 7|
|**2**|**FEATURES .................................................................................................................................................................... 8**||
||2.1|GYROSCOPEFEATURES....................................................................................................................................................... 8|
||2.2|ACCELEROMETERFEATURES................................................................................................................................................ 8|
||2.3|ADDITIONALFEATURES...................................................................................................................................................... 8|
|**3**|**ELECTRICAL CHARACTERISTICS ..................................................................................................................................... 9**||
||3.1|GYROSCOPESPECIFICATIONS............................................................................................................................................... 9|
||3.2|ACCELEROMETERSPECIFICATIONS...................................................................................................................................... 10|
||3.3|ELECTRICALSPECIFICATIONS.............................................................................................................................................. 11|
||3.4|I2C TIMINGCHARACTERIZATION........................................................................................................................................ 14|
||3.5|SPI TIMINGCHARACTERIZATION........................................................................................................................................ 15|
||3.6|ABSOLUTEMAXIMUMRATINGS......................................................................................................................................... 16|
|**4**|**APPLICATIONS INFORMATION ................................................................................................................................... 17**||
||4.1|PINOUTDIAGRAM ANDSIGNALDESCRIPTION...................................................................................................................... 17|
||4.2|TYPICALOPERATINGCIRCUIT............................................................................................................................................. 18|
||4.3|BILL OFMATERIALS FOREXTERNALCOMPONENTS................................................................................................................. 18|
||4.4|BLOCKDIAGRAM............................................................................................................................................................ 19|
||4.5|OVERVIEW..................................................................................................................................................................... 19|
||4.6|THREE-AXISMEMS GYROSCOPE WITH16-BITADCS ANDSIGNALCONDITIONING...................................................................... 20|
||4.7|THREE-AXISMEMS ACCELEROMETER WITH16-BITADCS ANDSIGNALCONDITIONING............................................................... 20|
||4.8|I2CANDSPI SERIALCOMMUNICATIONSINTERFACES.............................................................................................................. 20|
||4.9|SELF-TEST..................................................................................................................................................................... 21|
||4.10|CLOCKING..................................................................................................................................................................... 21|
||4.11|SENSORDATAREGISTERS................................................................................................................................................. 22|
||4.12|FIFO ............................................................................................................................................................................ 22|
||4.13|INTERRUPTS................................................................................................................................................................... 22|
||4.14|DIGITAL-OUTPUTTEMPERATURESENSOR............................................................................................................................ 22|
||4.15|BIAS ANDLDOS.............................................................................................................................................................. 22|
||4.16|CHARGEPUMP............................................................................................................................................................... 22|
||4.17|STANDARDPOWERMODES.............................................................................................................................................. 22|
|**5**|**PROGRAMMABLE INTERRUPTS .................................................................................................................................. 23**||
|**6**|**DIGITAL INTERFACE .................................................................................................................................................... 24**||



Page 2 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

|6.1|I2CANDSPI SERIALINTERFACES........................................................................................................................................ 24|
|---|---|
|6.2|I2C INTERFACE................................................................................................................................................................ 24|
|6.3|I2C COMMUNICATIONSPROTOCOL..................................................................................................................................... 25|
|6.4|I2C TERMS..................................................................................................................................................................... 27|
|6.5|SPI INTERFACE............................................................................................................................................................... 28|
|**7**<br>**SERIAL INTERFACE CONSIDERATIONS ......................................................................................................................... 29**||
|7.1|ICG-20660 SUPPORTEDINTERFACES................................................................................................................................. 29|
|**8**<br>**ASSEMBLY .................................................................................................................................................................. 30**||
|8.1|ORIENTATION OFAXES..................................................................................................................................................... 30|
|8.2|PACKAGEDIMENSIONS.................................................................................................................................................... 31|
|**9**<br>**PART NUMBER PACKAGE MARKING........................................................................................................................... 33**||
|**10**<br>**REFERENCE ............................................................................................................................................................. 34**||
|**11**<br>**REGISTER MAP ....................................................................................................................................................... 35**||
|**12**<br>**REGISTER DESCRIPTIONS ........................................................................................................................................ 38**||
|12.1|REGISTERS0TO2 – GYROSCOPESELF-TESTREGISTERS.......................................................................................................... 38|
|12.2|REGISTER4 – GYROSCOPEOFFSETTEMPERATURECOMPENSATION(TC) REGISTER..................................................................... 38|
|12.3|REGISTER5 – GYROSCOPEOFFSETTEMPERATURECOMPENSATION(TC) REGISTER..................................................................... 39|
|12.4|REGISTER07 – GYROSCOPEOFFSETTEMPERATURECOMPENSATION(TC) REGISTER................................................................... 39|
|12.5|REGISTER08 – GYROSCOPEOFFSETTEMPERATURECOMPENSATION(TC) REGISTER................................................................... 39|
|12.6|REGISTER10 – GYROSCOPEOFFSETTEMPERATURECOMPENSATION(TC) REGISTER................................................................... 40|
|12.7|REGISTER11 – GYROSCOPEOFFSETTEMPERATURECOMPENSATION(TC) REGISTER................................................................... 40|
|12.8|REGISTERS13TO15 – ACCELEROMETERSELF-TESTREGISTERS............................................................................................... 40|
|12.9|REGISTERS19 – GYROOFFSETADJUSTMENTREGISTER.......................................................................................................... 41|
|12.10|REGISTERS20 – GYROOFFSETADJUSTMENTREGISTER...................................................................................................... 41|
|12.11|REGISTERS21 – GYROOFFSETADJUSTMENTREGISTER...................................................................................................... 41|
|12.12|REGISTERS22 – GYROOFFSETADJUSTMENTREGISTER...................................................................................................... 41|
|12.13|REGISTERS23 – GYROOFFSETADJUSTMENTREGISTER...................................................................................................... 42|
|12.14|REGISTER24 – GYROOFFSETADJUSTMENTREGISTER....................................................................................................... 42|
|12.15|REGISTER25 – SAMPLERATEDIVIDER............................................................................................................................ 42|
|12.16|REGISTER26 – CONFIGURATION.................................................................................................................................... 43|
|12.17|REGISTER27 – GYROSCOPECONFIGURATION................................................................................................................... 44|
|12.18|REGISTER28 – ACCELEROMETERCONFIGURATION............................................................................................................ 44|
|12.19|REGISTER29 – ACCELEROMETERCONFIGURATION2 ......................................................................................................... 45|
|12.20|REGISTER30 – LOWPOWERMODECONFIGURATION........................................................................................................ 46|
|12.21|REGISTER31 – WAKE-ONMOTIONTHRESHOLD(ACCELEROMETER) ..................................................................................... 47|
|12.22|REGISTER35 – FIFO ENABLE........................................................................................................................................ 47|
|12.23|REGISTER54 – FSYNC INTERRUPTSTATUS...................................................................................................................... 47|
|12.24|REGISTER55 – INT PIN/ BYPASSENABLECONFIGURATION................................................................................................ 48|
|12.25|REGISTER56 – INTERRUPTENABLE................................................................................................................................ 48|
|12.26|REGISTER58 – INTERRUPTSTATUS................................................................................................................................. 49|
|12.27|REGISTERS59TO64 – ACCELEROMETERMEASUREMENTS................................................................................................. 49|
|12.28|REGISTERS65AND66 – TEMPERATUREMEASUREMENT.................................................................................................... 50|
|12.29|REGISTERS67TO72 – GYROSCOPEMEASUREMENTS........................................................................................................ 50|
|12.30|REGISTER104 – SIGNALPATHRESET............................................................................................................................. 51|
|12.31|REGISTER105 – ACCELEROMETERINTELLIGENCECONTROL................................................................................................ 52|
|12.32|REGISTER106 – USERCONTROL................................................................................................................................... 52|
|12.33|REGISTER107 – POWERMANAGEMENT1 ...................................................................................................................... 53|
|12.34|REGISTER108 – POWERMANAGEMENT2 ...................................................................................................................... 54|



Page 3 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

|12.35|REGISTER114AND115 – FIFO COUNTREGISTERS.......................................................................................................... 54|
|---|---|
|12.36|REGISTER116 – FIFO READWRITE............................................................................................................................... 54|
|12.37|REGISTER117 – WHOAMI ......................................................................................................................................... 55|
|12.38|REGISTERS119, 120, 122, 123, 125, 126 ACCELEROMETEROFFSETREGISTERS.................................................................. 55|
|**13**<br>**REVISION HISTORY ................................................................................................................................................. 57**||



Page 4 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **LIST OF FIGURES** 

|FIGURE|IGURE1. I2C BUSTIMINGDIAGRAM................................................................................................................................................. 14|
|---|---|
|FIGURE|IGURE2. SPI BUSTIMINGDIAGRAM................................................................................................................................................ 15|
|FIGURE|IGURE3. PIN OUTDIAGRAM FORICG-20660 3MM X3MM X0.75MMLGA ......................................................................................... 17|
|FIGURE|IGURE4. ICG-20660 LGA APPLICATIONSCHEMATIC.......................................................................................................................... 18|
|FIGURE|IGURE5. ICG-20660 BLOCKDIAGRAM............................................................................................................................................ 19|
|FIGURE|IGURE6. ICG-20660 SOLUTIONUSINGI2C INTERFACE....................................................................................................................... 20|
|FIGURE|IGURE7. ICG-20660 SOLUTIONUSINGSPI INTERFACE....................................................................................................................... 21|
|FIGURE|IGURE8. STARTANDSTOP CONDITIONS......................................................................................................................................... 25|
|FIGURE|IGURE9. ACKNOWLEDGE ON THEI2C BUS.......................................................................................................................................... 25|
|FIGURE|IGURE10. COMPLETEI2C DATATRANSFER........................................................................................................................................ 26|
|FIGURE|IGURE11. TYPICALSPI MASTER/SLAVECONFIGURATION..................................................................................................................... 28|
|FIGURE|IGURE12. I/O LEVELS ANDCONNECTIONS......................................................................................................................................... 29|
|FIGURE|IGURE13. ORIENTATION OFAXES OFSENSITIVITY ANDPOLARITY OFROTATION........................................................................................ 30|
|FIGURE|IGURE8. PACKAGEDIMENSIONS...................................................................................................................................................... 31|



Page 5 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **LIST OF TABLES** 

|TABLE|ABLE1. GYROSCOPESPECIFICATIONS.................................................................................................................................................. 9|
|---|---|
|TABLE|ABLE2. ACCELEROMETERSPECIFICATIONS......................................................................................................................................... 10|
|TABLE|ABLE3. D.C. ELECTRICALCHARACTERISTICS....................................................................................................................................... 11|
|TABLE|ABLE4. A.C. ELECTRICALCHARACTERISTICS....................................................................................................................................... 13|
|TABLE|ABLE5. OTHERELECTRICALSPECIFICATIONS....................................................................................................................................... 13|
|TABLE|ABLE6. I2C TIMINGCHARACTERISTICS.............................................................................................................................................. 14|
|TABLE|ABLE7. SPI TIMINGCHARACTERISTICS(7 MHZOPERATION) ................................................................................................................ 15|
|TABLE|ABLE8. ABSOLUTEMAXIMUMRATINGS............................................................................................................................................ 16|
|TABLE|ABLE9. SIGNALDESCRIPTIONS........................................................................................................................................................ 17|
|TABLE|ABLE10. BILL OFMATERIALS.......................................................................................................................................................... 18|
|TABLE|ABLE11. STANDARDPOWERMODES FORICG-20660 ........................................................................................................................ 22|
|TABLE|ABLE12. TABLE OFINTERRUPTSOURCES........................................................................................................................................... 23|
|TABLE|ABLE13. SERIALINTERFACE............................................................................................................................................................ 24|
|TABLE|ABLE14. I2C TERMS...................................................................................................................................................................... 27|
|TABLE|ABLE15. PACKAGEDIMENSIONS..................................................................................................................................................... 32|
|TABLE|ABLE16. PACKAGENUMBERPACKAGEMARKING............................................................................................................................... 33|
|TABLE|ABLE17. ICG-20660REGISTER MAP............................................................................................................................................... 36|



Page 6 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**1 INTRODUCTION**_ 

## **1.1 PURPOSE AND SCOPE** 

This document provides a description, specifications, and design-related information on the ICG-20660 MotionTracking device for imaging applications, such as Optical Image Stabilization, OIS, or Electronic Image Stabilization, EIS. The device is housed in a small 3 mm x 3 mm x 0.75 mm 16-pin LGA package. 

## **1.2 PRODUCT OVERVIEW** 

The ICG-20660 is a 6-axis MotionTracking device that combines a 3-axis gyroscope, and a 3-axis accelerometer in a small 3 mm x 3 mm x 0.75 mm (16-pin LGA) package. The 6-axis sensor allows efficient implementation of advanced 5- and 6-axes Optical Image Stabilization in high-end still and video cameras. It also features a 512-byte FIFO for EIS applications to lower the traffic on the serial bus interface, and reduce power consumption by allowing the system processor to burst read sensor data for a given video frame. The unique support for FSYNC (frame sync), facilitates synchronization of Video Frame Sync from Image sensors and Motion data from the gyroscopes and accelerators collected during a given frame via an interrupt to the host.  ICG-20660, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete devices. 

The gyroscope has a programmable full-scale range of ±125 dps, ±250 dps, and ±500 dps, optimized for Image Stabilization applications. The accelerometer has a user-programmable accelerometer full-scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ , and ±16 _g_ . Factorycalibrated initial sensitivity of both sensors reduces production-line calibration requirements. 

Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and programmable interrupts. The device features I[2] C and SPI serial interfaces, a VDD operating range of 1.71 V to 3.6 V, and a separate digital IO supply, VDDIO from 1.71 V to 3.6 V. 

Communication with all registers of the device is performed using either I[2] C at 400 kHz or SPI at 7 MHz. 

By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of 3x3x0.75 mm (16-pin LGA), to provide a very small yet high-performance, low-cost package. The device provides high robustness by supporting 10,000 _g_ shock reliability. 

## **1.3 APPLICATIONS** 

- _OIS,_ Optical Image Stabilization in phone camera modules, DSLR, and DSC 

- _EIS,_ Electronic Image Stabilization in DSC, and phone camera modules 

Page 7 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**2 FEATURES**_ 

## **2.1 GYROSCOPE FEATURES** 

The triple-axis MEMS gyroscope in the ICG-20660 includes a wide range of features: 

- Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±125 dps, ±250 dps, and ±500 dps and integrated 16-bit ADCs 

- Digitally-programmable low-pass filter 

- Factory calibrated sensitivity scale factor 

- Self-test 

## **2.2 ACCELEROMETER FEATURES** 

The triple-axis MEMS accelerometer in ICG-20660 includes a wide range of features: 

- Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2 _g_ , ±4 _g_ , ±8 _g_ , and ±16 _g_ and integrated 16-bit ADCs 

- User-programmable interrupts 

- Wake-on-motion interrupt for low power operation of applications processor 

- Self-test 

## **2.3 ADDITIONAL FEATURES** 

The ICG-20660 includes the following additional features: 

- Minimal cross-axis sensitivity between the accelerometer and gyroscope axes 

- 512-byte FIFO buffer enable the applications processor to read the data in bursts 

- Digital-output temperature sensor 

- User-programmable digital filters for gyroscope, accelerometer, and temp sensor 

- 10,000 _g_ shock tolerant 

- 400 kHz Fast Mode I[2] C for communicating with all registers 

- 7 MHz SPI serial interface for communicating with all registers 

- MEMS structure hermetically sealed and bonded at wafer level 

- RoHS and Green compliant 

Page 8 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**3 ELECTRICAL CHARACTERISTICS**_ 

## **3.1 GYROSCOPE SPECIFICATIONS** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**GYROSCOPE SENSITIVITY**<br>~~eee~~<br>~~ns OsI~~|||||||
|Full-Scale Range|FS_SEL = 0<br>~~ns~~|~~ns~~<br>~~ns Os~~<br>~~Gs~~|±125<br>~~ns~~<br>~~Os~~|~~ns~~<br>~~I~~|dps<br>~~ns~~|3<br>~~ns~~|
||FS_SEL = 1<br>~~es~~|~~ns Os~~<br>~~es~~<br>~~Gs~~<br>~~ey nD~~|±250<br>~~Os ~~<br>~~es~~<br>~~nD~~|~~I~~<br>~~es~~<br>~~I~~|dps<br>~~es~~<br>~~I~~|3<br>~~es~~|
||FS_SEL = 2<br>~~rs~~|~~Gs~~<br>~~rs~~<br>~~ey nD~~|±500<br>~~rs~~<br>~~nD~~|~~rs~~<br>~~I~~|dps<br>~~rs~~<br>~~I~~|3<br>~~rs~~|
|ADC Word Length<br>~~ID~~|~~ID~~|~~ey nD~~<br>~~ID~~<br>~~Rs~~|16<br>~~nD ~~<br>~~ID~~|~~I~~<br>~~ID~~|bits<br>~~I~~<br>~~ID~~|3<br>~~ID~~|
|Sensitivity Scale Factor|FS_SEL = 0<br>~~es~~|~~es~~<br>~~Rs~~<br>~~es~~|262<br>~~es~~<br>~~Ps es~~|~~es~~<br>~~es~~|LSB/(dps)<br>~~es~~|3<br>~~es~~|
||FS_SEL = 1<br>~~es~~|~~Rs~~<br>~~es~~<br>~~es~~<br>~~es~~|131<br>~~es~~<br>~~Ps es~~<br>~~Ps~~|~~es~~<br>~~es~~<br>~~ns~~|LSB/(dps)<br>~~es~~|3<br>~~es~~|
||FS_SEL = 2<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~(OD~~|65.5<br>~~Ps es~~<br>~~es~~<br>~~Ps~~<br>~~GS~~|~~es~~<br>~~es~~<br>~~ns~~<br>~~(O~~|LSB/(dps)<br>~~es~~|3<br>~~es~~|
|Initial SensitivityScale Factor Tolerance<br>~~nD~~|25°C<br>~~nD~~<br>~~QO~~|~~es~~<br>~~nD~~<br>~~(OD~~<br>~~QO~~|±3<br>~~Ps~~<br>~~nD~~<br>~~GS~~<br>~~(OS~~|~~ns~~<br>~~nD~~<br>~~(O~~|%<br>~~nD~~|2<br>~~nD~~|
|SensitivityScale Factor Variation Over Temperature<br>~~I~~|-20°C to +75°C<br>~~I~~<br>~~QO~~|~~(OD~~<br>~~I~~<br>~~QO~~|±3<br>~~GS~~<br>~~I~~<br>~~(OS~~|~~(O~~<br>~~I~~|%<br>~~I~~|1<br>~~I~~|
|Nonlinearity<br>~~ef~~|Best fit straight line; 25°C<br>~~QO~~<br>~~ef~~|~~QO~~<br>~~ef~~|±0.1<br>~~(OS~~<br>~~ef~~<br>~~sO~~|~~ef~~<br>~~sO~~|%<br>~~ef~~|1<br>~~ef~~|
|Cross-Axis Sensitivity<br>~~ef~~<br>~~fs~~|~~ef~~<br>~~fs~~|~~ef~~<br>~~fs~~|±5<br>~~ef~~<br>~~fs~~<br>~~sO~~|~~ef~~<br>~~fs~~<br>~~sO~~|%<br>~~ef~~<br>~~fs~~|1<br>~~ef~~<br>~~fs~~|
|**ZERO-RATE OUTPUT (ZRO)**<br>~~fs~~<br>~~sO~~|||||||
|Initial ZRO Tolerance<br>~~ff~~|25°C<br>~~ff~~|~~ff~~|±5<br>~~ff~~<br>~~sO~~|~~ff~~<br>~~sO~~|dps<br>~~ff~~|2<br>~~ff~~|
|ZRO Variation Over Temperature<br>~~ff~~<br>~~fs~~|-20°C to +75°C<br>~~ff~~<br>~~fs~~|~~ff~~<br>~~fs~~|±5<br>~~ff~~<br>~~fs~~<br>~~sO~~|~~ff~~<br>~~fs~~<br>~~sO~~|dps<br>~~ff~~<br>~~fs~~|1<br>~~ff~~<br>~~fs~~|
|**GYROSCOPE NOISE PERFORMANCE (FS_SEL = 0)**<br>~~fs~~<br>~~sO~~<br>~~nsPs~~<br>~~ns~~|||||||
|Total RMS Noise|DLPFCFG = 2(92 Hz)<br>~~rs~~|~~rs~~<br>~~ns~~|0.075<br>~~rs~~<br>~~Ps~~<br>~~ss~~|~~rs~~<br>~~ns~~<br>~~ss~~|dps-rms<br>~~rs~~|2<br>~~rs~~|
||DLPFCFG = 1(176 Hz)<br>~~ee~~|~~ns~~<br>~~ee~~<br>~~es~~|0.10<br>~~Ps~~<br>~~ee~~<br>~~ss~~<br>~~es~~|~~ns~~<br>~~ee~~<br>~~ss~~<br>~~es~~|dps-rms<br>~~ee~~|2<br>~~ee~~|
||DLPFCFG = 0(250 Hz)<br>~~ee~~<br>~~es~~|~~ee~~<br>~~es~~<br>~~es~~<br>~~es~~|0.12<br>~~ee~~<br>~~ss~~<br>~~es~~<br>~~es~~<br>~~es~~|~~ee~~<br>~~ss~~<br>~~es~~<br>~~es~~<br>~~es~~|dps-rms<br>~~ee~~<br>~~es~~|2<br>~~ee~~<br>~~es~~|
|Total Peak-to-Peak Noise<br>~~a~~|DLPFCFG = 2(92 Hz)<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es es~~|0.37<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|dps-p-p<br>~~es~~<br>~~es~~|2<br>~~es~~<br>~~es~~|
||DLPFCFG = 1(176 Hz)<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~es es~~<br>~~es~~|0.50<br>~~es~~<br>~~es ~~<br>~~es~~<br>~~es~~|~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~|dps-p-p<br>~~es~~<br>~~es~~|2<br>~~es~~<br>~~es~~|
||DLPFCFG = 0 (250 Hz)<br>~~es~~<br>~~es~~<br>~~(OD~~|~~es~~<br>~~es es~~<br>~~es~~<br>~~es~~<br>~~(OD~~|0.60<br>~~es~~<br>~~es~~<br>~~es~~<br>~~(OO~~|~~es~~<br>~~es~~<br>~~es~~<br>~~(OO~~|dps-p-p<br>~~es~~<br>~~es~~|2<br>~~es~~<br>~~es~~|
|Rate Noise Spectral Density<br>~~a~~|At 10 Hz<br>~~(OD~~|~~es~~<br>~~(OD~~|0.0065<br>~~(OO~~|~~(OO~~|dps /√Hz|4|
|**GYROSCOPE MECHANICAL**<br>Mechanical Frequency<br>Sensor Mechanical Bandwidth|~~(OD~~|25.6<br>1.2<br>~~(OD~~<br>~~EN~~|27<br>~~(OO~~<br>~~ENsO~~|29<br>~~(OO~~<br>~~sO~~|kHz<br>kHz<br>~~sO~~|2<br>1<br>~~sO~~|
|**LOW PASS FILTER RESPONSE**<br>~~«LO~~|Programmable Range<br>~~«LO~~|92<br>~~«LO~~<br>~~EN~~|~~«LO~~<br>~~ENsO~~|250<br>~~«LO~~<br>~~sO~~|Hz<br>~~«LO~~<br>~~sO~~|3<br>~~«LO~~<br>~~sO~~|
|**GYROSCOPE START-UP TIME**<br>~~«LO~~|~~«LO~~<br>~~Gr~~|~~«LO~~<br>~~EN ~~<br>~~re~~|80<br>~~«LO~~<br> ~~ENsO~~|<br>~~«LO~~<br>~~sO~~|ms<br>~~«LO~~<br>~~sO~~|1<br>~~«LO~~<br>~~sO~~|
|**OUTPUT DATA RATE**<br>~~es~~|Programmable, Normal (Filtered)<br>mode<br>~~es~~<br>~~Gr~~|1000<br>~~es~~<br>~~re~~|~~es~~|8000<br>~~es~~|Hz<br>~~es~~|1<br>~~es~~|



## **Table 1. Gyroscope Specifications** 

## **Notes:** 

1. Derived from validation or characterization of parts, not guaranteed in production. 

2. Tested in production. 

3. Guaranteed by design. 

4. Calculated from Total RMS Noise. 

Page 9 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **3.2 ACCELEROMETER SPECIFICATIONS** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|**NOTES**|
|---|---|---|---|---|---|---|
|**ACCELEROMETER SENSITIVITY**<br>~~Pee~~<br>~~RD~~|||||||
|Full-Scale Range|AFS_SEL = 0<br>~~rs~~|~~rs~~<br>~~RD~~<br>~~RU~~|±2<br>~~rs~~|~~rs~~|_g_<br>~~rs~~|3<br>~~rs~~|
||AFS_SEL = 1<br>~~rs~~|~~RD~~<br>~~rs~~<br>~~RU~~<br>~~RU~~|±4<br>~~rs~~|~~rs~~|_g_<br>~~rs~~|3<br>~~rs~~|
||AFS_SEL = 2<br>~~rs~~|~~RU~~<br>~~rs~~<br>~~RU~~<br>~~Rn~~|±8<br>~~rs~~|~~rs~~|_g_<br>~~rs~~|3<br>~~rs~~|
||AFS_SEL = 3<br>~~rs~~|~~RU~~<br>~~rs~~<br>~~Rn~~<br>~~GO~~|±16<br>~~rs~~|~~rs~~|_g_<br>~~rs~~|3<br>~~rs~~|
|ADC Word Length<br>~~nn~~|Output in two’s complement format<br>~~nn~~|~~Rn~~<br>~~nn~~<br>~~GO~~<br>~~nts~~|16<br>~~nn~~<br>~~nn~~|~~nn~~<br>~~ts~~|bits<br>~~nn~~|3<br>~~nn~~|
|Sensitivity Scale Factor|AFS_SEL = 0<br>~~rs~~|~~GO~~<br>~~rs~~<br>~~nts~~<br>~~ns~~|16,384<br>~~rs~~<br>~~nn~~<br>~~nn~~|~~rs~~<br>~~ts~~<br>~~ts~~|LSB/_g_<br>~~rs~~|3<br>~~rs~~|
||AFS_SEL = 1<br>~~rs~~|~~nts~~<br>~~rs~~<br>~~ns~~<br>~~ns~~|8,192<br>~~nn ~~<br>~~rs~~<br>~~nn~~<br>~~nn~~|~~ts~~<br>~~rs~~<br>~~ts~~<br>~~ts~~|LSB/_g_<br>~~rs~~|3<br>~~rs~~|
||AFS_SEL = 2<br>~~rs~~|~~ns ~~<br>~~rs~~<br>~~ns~~<br>~~nr~~|4,096<br> ~~nn ~~<br>~~rs~~<br>~~nn~~<br>~~tn ts~~|~~ts~~<br>~~rs~~<br>~~ts~~<br>~~ts~~|LSB/_g_<br>~~rs~~|3<br>~~rs~~|
||AFS_SEL = 3<br>~~rs~~|~~ns ~~<br>~~rs~~<br>~~nr~~|2,048<br> ~~nn ~~<br>~~rs~~<br>~~tn ts~~|~~ts~~<br>~~rs~~<br>~~ts~~|LSB/_g_<br>~~rs~~|3<br>~~rs~~|
|SensitivityInitial Tolerance<br>~~a~~|Component-level<br>~~es~~|~~nr ~~<br>~~ee~~|±1<br> ~~tn ts~~<br>~~ee~~|~~ts~~<br>~~es~~|%|2|
|Sensitivity Change vs. Temperature<br>~~a~~<br>~~es~~|-20°C to +75°C AFS_SEL = 0<br>Component-level<br>~~es~~<br>~~es~~|~~ee~~<br>~~GD~~|±2.5<br>~~ee~~|~~es~~|%|1|
|Nonlinearity<br>~~a~~<br>~~es~~<br>~~es~~|Best Fit Straight Line<br>~~es ~~<br>~~es~~<br>~~ND~~|~~ee ~~<br>~~GD~~<br>~~(I~~|±0.5<br> ~~ee ~~|~~es~~|%|1|
|Cross-Axis Sensitivity<br>~~es~~<br>~~es~~|~~es~~<br>~~ND~~|~~GD~~<br>~~(I~~|±2||%|1|
|**ZERO-G OUTPUT**<br>~~esND(I~~|||||||
|Initial Tolerance|Component-level, X and Y axes|~~Rn~~|±40||m_g_|2|
||Component-level, Z axis<br>~~rs~~|~~rs~~<br>~~Rn~~|±65<br>~~rs~~|~~rs~~|mg<br>~~rs~~|2<br>~~rs~~|
|Zero-G Level Change vs. Temperature|-20°C to +75°C|~~Rn~~|±50||m_g_|1|
|**NOISE PERFORMANCE**<br>~~Pe~~<br>~~es rs~~|||||||
|Power Spectral Density<br>~~Pe~~<br>~~es rs~~<br>~~rs~~|~~Pe~~<br>~~rs~~<br>~~Ss~~|~~Pe~~|220<br>~~Pe~~|~~Pe~~|µ_g_/√Hz<br>~~Pe~~|4<br>~~Pe~~|
|Total RMS Noise<br>~~es rs~~<br>~~rs~~<br>~~ry ns~~|DLPFCFG = 2(100 Hz)<br>~~rs~~<br>~~Ss~~<br>~~ns~~|~~G~~|2||mg-rms|2|
|**LOW PASS FILTER RESPONSE**<br>~~rs~~<br>~~ry ns~~<br>~~a~~|Programmable Range<br>~~Ss~~<br>~~ns~~<br>~~ne~~<br>|5<br>~~G~~<br>~~GO~~<br>|~~GO~~<br>|260<br>~~GO~~<br>|Hz<br>~~GO~~<br>|3<br>|
|**INTELLIGENCE FUNCTION INCREMENT**<br>~~ry ns~~<br>~~nD~~<br>~~a~~|~~ns~~<br>~~nD~~<br>~~ne~~<br>|~~G~~<br>~~nD~~<br>~~GO~~<br>|4<br>~~nD~~<br>~~GO~~<br>|~~nD~~<br>~~GO~~<br>|m_g_/LSB<br>~~nD~~<br>~~GO~~<br>|3<br>~~nD~~<br>|
|**ACCELEROMETER STARTUP TIME**<br>~~a~~<br>~~OO~~|From Sleepmode<br>~~ne~~<br>|~~GO~~<br>|20<br>~~GO~~<br>|~~GO~~<br>|ms<br>~~GO~~<br>|1<br>|
||From Cold Start,1ms VDD ramp<br>~~ne~~<br>~~ee~~|~~GO~~<br>~~ee~~|30<br>~~GO~~<br>~~ee~~|~~GO~~<br>~~ee~~|ms<br>~~GO~~<br>~~ee~~|1<br>~~ee~~|
|**OUTPUT DATA RATE**<br>~~a ~~<br>~~OO~~|Low power (duty-cycled)<br>~~ne~~<br> ~~ee~~|0.24<br>~~GO~~<br>~~ee~~|~~GO~~<br>~~ee~~|500<br>~~GO~~<br>~~ee~~|Hz<br>~~GO~~<br>~~ee~~|1<br>~~ee~~|
||Duty-cycled, over temp<br> ~~ee~~|~~ee~~|±15<br>~~ee~~|~~ee~~|%<br>~~ee~~||
||Low noise (active)<br> ~~ee~~|4<br>~~ee~~|~~ee~~|4000<br>~~ee~~|Hz<br>~~ee~~||



2. Tested in production. 

3. Guaranteed by design. 

4. Calculated from Total RMS Noise. 

Page 10 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **3.3 ELECTRICAL SPECIFICATIONS** 

## **3.3.1 D.C. Electrical Characteristics** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

**PARAMETER CONDITIONS MIN TYP MAX Units Notes SUPPLY VOLTAGES** ~~OO~~ VDD 1.71 1.8 3.45 V 1 ~~a (~~ VDDIO 1.71 1.8 3.45 V 1 **SUPPLY CURRENTS & BOOT TIME** ~~ae~~ Active Current 6-Axis Gyroscope + Accelerometer 3 mA 1 Accelerometer Low -Power Mode 100 Hz ODR, 1x averaging 57 µA 2 ~~——————~~ (Gyroscope disabled) ~~nD~~ Full-Chip Sleep Mode ~~I (OD (OU~~ 10 ~~OO~~ µA 1 Boot Time VDD on to first register write 50 ms 1 **TEMPERATURE RANGE** ~~OO Pe~~ Operating Temperature Range -40 ~~ff~~ +85 °C 1 **Table 3. D.C. Electrical Characteristics** 

## **Notes:** 

1. Derived from validation or characterization of parts, not guaranteed in production. 

2. Based on simulation. 

Page 11 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **3.3.2 A.C. Electrical Characteristics** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

|**Parameter**<br>~~I~~|**Conditions**<br>~~I~~<br>~~(~~|**MIN**<br>~~I~~<br>~~(~~|**TYP**<br>~~I~~<br>~~(~~|**MAX**<br>~~I~~<br>~~(~~|**Units**<br>~~I~~|**NOTES**<br>~~I~~|
|---|---|---|---|---|---|---|
|**SUPPLIES**<br>~~(~~<br>~~(~~|||||||
|Supply Ramp Time|Monotonic ramp. Ramp rate is<br>10% to 90% of the final value|0.1||100|ms|1|
|**TEMPERATURE SENSOR**|||||||
|Operating Range<br>_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd|Ambient<br>_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd<br>~~fh~~|-40<br>_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd<br>~~fh hdr~~|_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd<br>~~hdr~~|85<br>_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd<br>~~hdr~~|°C<br>_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd<br>~~hdr~~|1<br>_ti‘“t=C;‘;!WCr™’!OUOC(‘(;‘C;!C*r?;!.COC~édr~S~COC~‘(CLLCN!”*dCO!”tCd<br>~~hdr~~|
|Room Temperature Offset<br>~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~|25°C<br>~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~<br>~~fh~~|~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~<br>~~fh hdr~~|0<br>~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~<br>~~hdr~~|~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~<br>~~hdr~~|°C<br>~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~<br>~~hdr~~|1<br>~~t~<‘“CS™S~S~O~C~CSCCCCCCY.TCOTTT..~~<br>~~hdr~~|
|Sensitivity<br>~~es~~|Untrimmed<br>~~fh~~<br>~~es~~|~~fh hdr~~<br>~~es~~|326.8<br>~~hdr~~<br>~~es~~|~~hdr~~<br>~~es~~|LSB/°C<br>~~hdr~~<br>~~es~~|1<br>~~hdr~~<br>~~es~~|
|**Power-On RESET**<br>~~ee ee~~<br>~~eeeeee~~|||||||
|Supply Ramp Time (TRAMP)<br>~~ee ee~~|Valid power-on RESET<br>~~ee~~|0.01<br>~~ee~~|20<br>~~ee~~|100<br>~~ee~~|ms|1|
|Start-up time for register read/write<br>~~ee ee~~|From power-up<br>~~ee~~<br>~~rs~~|~~ee~~<br>~~Pe~~|11<br>~~ee~~<br>~~es~~|100<br>~~ee~~<br>~~es ee~~|ms<br>~~ee~~|1|
|**I2C ADDRESS**<br>~~ee ee~~<br>~~es~~|SA0 = 0<br>SA0 = 1<br>~~ee~~<br>~~es~~<br>~~rs~~|~~ee ~~<br>~~es~~<br>~~Pe~~|1101000<br>1101001<br> ~~ee ~~<br>~~es~~<br>~~es~~|~~ee~~<br>~~es~~<br>~~es ee~~|~~es~~<br>~~ee~~|~~es~~|
|**DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)**<br>~~es~~<br>~~rs Pe es ee~~<br>~~en~~|||||||
|VIH, High Level Input Voltage<br>~~es~~|~~es~~<br>~~en~~<br>~~es~~|0.7*VDDIO<br>~~es~~|~~es~~|~~es~~|V<br>~~es~~|1|
|VIL, Low Level Input Voltage<br>~~es~~<br>~~es~~|~~es~~<br>~~en~~<br>~~es~~<br>~~es~~<br>~~er~~|~~es~~<br>~~es~~|~~es~~<br>~~es~~|0.3*VDDIO<br>~~es~~<br>~~es~~|V<br>~~es~~<br>~~es~~||
|CI, Input Capacitance<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~<br>~~es~~<br>~~er~~|~~es~~<br>~~es~~|< 10<br>~~es~~<br>~~es~~|~~es~~<br>~~es~~|pF<br>~~es~~<br>~~es~~||
|**DIGITAL OUTPUT (SDO, INT)**<br>~~es~~<br>~~er~~<br>~~en~~|||||||
|VOH, High Level Output Voltage<br>~~es~~|RLOAD= 1 MΩ;<br>~~es~~<br>~~en~~|0.9*VDDIO<br>~~es~~|~~es~~|~~es~~|V<br>~~es~~|1|
|VOL1, LOW-Level Output Voltage<br>~~es~~|RLOAD= 1 MΩ;<br>~~es~~<br>~~en~~<br>~~es~~|~~es~~<br>~~es~~|~~es~~<br>~~es~~|0.1*VDDIO<br>~~es~~<br>~~ee~~|V<br>~~es~~||
|VOL.INT, INT Low-Level Output Voltage<br>~~ee~~|OPEN = 1, 0.3 mA sink<br>Current<br>~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|~~ee~~<br>~~es~~|0.1<br>~~ee~~<br>~~ee~~|V<br>~~ee~~||
|Output Leakage Current<br>~~ee~~<br>~~en~~|OPEN = 1<br>~~ee~~<br>~~es~~<br>~~en~~<br>~~en~~|~~ee~~<br>~~es~~<br>~~en~~|100<br>~~ee~~<br>~~es~~<br>~~en~~|~~ee~~<br>~~ee~~<br>~~en~~|nA<br>~~ee~~<br>~~en~~||
|tINT, INT Pulse Width<br>~~en~~<br>~~en~~|LATCH_INT_EN = 0<br>~~en~~<br>~~en~~<br>~~en~~|~~en~~<br>~~en~~|50<br>~~en~~<br>~~en~~|~~en~~<br>~~en~~|µs<br>~~en~~<br>~~en~~||
|**I2C I/O (SCL, SDA)**<br>~~en~~<br>~~en~~<br>~~Se~~|||||||
|VIL, LOW Level Input Voltage<br>~~es~~|~~es~~<br>~~Se~~|-0.5<br>~~es~~|~~es~~|0.3*VDDIO<br>~~es~~|V<br>~~es~~|1|
|VIH, HIGH-Level Input Voltage<br>~~es~~<br>~~en~~|~~es~~<br>~~Se~~<br>~~en~~|0.7*VDDIO<br>~~es~~<br>~~en~~|~~es~~<br>~~en~~|VDDIO + 0.5V<br>~~es~~<br>~~en~~|V<br>~~es~~<br>~~en~~||
|Vhys, Hysteresis<br>~~en~~<br>~~a~~|~~en~~<br>|~~en~~<br>|0.1*VDDIO<br>~~en~~<br>|~~en~~<br>|V<br>~~en~~<br>||
|VOL, LOW-Level Output Voltage<br><br>~~a~~|3mA sink current<br><br>~~es es~~|0<br><br>~~es~~||0.4<br>|V<br>||
|IOL, LOW-Level Output Current<br>~~ae~~<br>~~a~~|VOL= 0.4V<br>VOL= 0.6V<br>~~ae~~<br>~~es es~~|~~ae~~<br>~~es~~|3<br>6<br>~~ae~~|~~ae~~|mA<br>mA<br>~~ae~~||
|Output Leakage Current<br>~~ae~~<br>~~a~~|~~ae~~<br>~~es es~~|~~ae~~<br>~~es~~|100<br>~~ae~~|~~ae~~|nA<br>~~ae~~||
|tof, Output Fall Time from VIHmaxto VILmax<br>~~en~~|Cbbus capacitance in pf<br>~~en~~|20+0.1Cb<br>~~en~~|~~en~~|300<br>~~en~~|ns<br>~~en~~||
|**INTERNAL CLOCK SOURCE**|||||||
|Sample Rate|FCHOICE_B = 1,2,3<br>SMPLRT_DIV = 0||32||kHz|2|
||FCHOICE_B = 0;<br>DLPFCFG = 0 or 7<br>SMPLRT_DIV = 0||8||kHz|2|
||FCHOICE_B = 0;<br>DLPFCFG = 1,2,3,4,5,6;<br>SMPLRT_DIV = 0||1||kHz|2|
|Clock Frequency Initial Tolerance|CLK_SEL= 0, 6 or gyro inactive;<br>25°C|-5||+5|%|1|



Page 12 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

|**Parameter**|**Conditions**|**MIN**|**TYP**|**MAX**|**Units**|**NOTES**|
|---|---|---|---|---|---|---|
||CLK_SEL = 1,2,3,4,5 and gyro<br>active;25°C|-1||+1|%|1|
|Frequency Variation over Temperature|CLK_SEL = 0,6 or gyro inactive|-10||+10|%|1|
||CLK_SEL = 1,2,3,4,5 and gyro<br>active||±1||%|1|



**Table 4. A.C. Electrical Characteristics** 

## **Notes:** 

1. Derived from validation or characterization of parts, not guaranteed in production. 

2. Guaranteed by design. 

## **3.3.3 Other Electrical Specifications** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

|**PARAMETER**|**CONDITIONS**|**MIN**|**TYP**|**MAX**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|**SERIAL INTERFACE**|||||||
|SPI Operating Frequency, All Registers<br>Read/Write|Low Speed Characterization||100 ±10%||kHz|1|
||High Speed Characterization||1|7|MHz|1, 2|
|SPI Modes|||Modes 0<br>and 3||||
|I2C Operating Frequency|All registers, Fast-mode|||400|kHz|1|
||All registers, Standard-mode|||100|kHz|1|



**Table 5. Other Electrical Specifications** 

## **Notes:** 

1. Derived from validation or characterization of parts, not guaranteed in production. 

2. SPI clock duty cycle between 45% and 55% should be used for 7 MHz operation. 

Page 13 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **3.4 I[2] C TIMING CHARACTERIZATION** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

|**Parameters**<br>~~a~~|**Conditions**<br>~~GCOS~~|**Min**<br>~~GCOS~~|**Typical**<br>~~GCOS~~|**Max**<br>~~GCOS~~<br>~~(OO~~|**Units**<br>~~GCOS~~<br>~~(OO~~|**Notes**<br>~~GCOS~~|
|---|---|---|---|---|---|---|
|**I2C TIMING**<br>~~eG~~|**I2C FAST-MODE**<br>~~eG~~|~~eG~~|~~eG~~|~~(OO~~<br>~~eG~~|~~(OO~~<br>~~eG~~|~~eG~~|
|fSCL, SCL Clock Frequency<br>~~GG~~|~~GG~~|~~GG~~|~~GG~~|400<br>~~GG~~|kHz<br>~~GG~~|1<br>~~GG~~|
|tHD.STA, (Repeated) START Condition Hold Time<br>~~a~~|~~GG~~|0.6<br>~~GG~~|~~GG~~|~~GG~~|µs<br>~~GG~~|1<br>~~GG~~|
|tLOW, SCL Low Period<br>~~GG~~|~~GG~~|1.3<br>~~GG~~|~~GG~~|~~GG~~|µs<br>~~GG~~|1<br>~~GG~~|
|tHIGH, SCL High Period<br>~~CG~~|~~CG~~|0.6<br>~~CG~~|~~CG~~|~~CG~~|µs<br>~~CG~~|1<br>~~CG~~|
|tSU.STA, Repeated START Condition Setup Time<br>~~a~~|~~GO~~|0.6<br>~~GO~~|~~GO~~|~~GO~~|µs<br>~~GO~~|1<br>~~GO~~|
|tHD.DAT, SDA Data Hold Time<br>~~GG~~|~~GG~~|0<br>~~GG~~|~~GG~~|~~GG~~|µs<br>~~GG~~|1<br>~~GG~~|
|tSU.DAT, SDA Data SetupTime<br>~~GG~~|~~GG~~|100<br>~~GG~~|~~GG~~|~~GG~~|ns<br>~~GG~~|1<br>~~GG~~|
|tr, SDA and SCL Rise Time<br>~~GG~~|Cbbus cap. from 10 to 400pF<br>~~GG~~|20+0.1Cb<br>~~GG~~|~~GG~~|300<br>~~GG~~|ns<br>~~GG~~|1<br>~~GG~~|
|tf, SDA and SCL Fall Time<br>~~GG~~|Cbbus cap. from 10 to 400pF<br>~~GG~~|20+0.1Cb<br>~~GG~~|~~GG~~|300<br>~~GG~~|ns<br>~~GG~~|1<br>~~GG~~|
|tSU.STO, STOP Condition Setup Time<br>~~GO~~|~~GO~~|0.6<br>~~GO~~|~~GO~~|~~GO~~|µs<br>~~GO~~|1<br>~~GO~~|
|tBUF, Bus Free Time Between STOP and START<br>Condition<br>~~GO~~<br>~~es~~|~~GO~~<br>~~es~~|1.3<br>~~GO~~<br>~~es~~|~~GO~~<br>~~es~~|~~GO~~<br>~~es~~|µs<br>~~GO~~<br>~~es~~|1<br>~~GO~~<br>~~es~~|
|Cb, Capacitive Load for each Bus Line<br>~~CG~~|~~CG~~|~~CG~~|< 400<br>~~CG~~|~~CG~~|pF<br>~~CG~~|1<br>~~CG~~|
|tVD.DAT, Data Valid Time<br>~~a~~|~~CO~~|~~CO~~|~~CO~~|0.9<br>~~CO~~|µs|1|
|tVD.ACK, Data Valid Acknowledge Time<br>~~a~~<br>~~DG~~|~~CO~~<br>~~DG~~|~~CO~~<br>~~DG~~|~~CO~~<br>~~DG~~|0.9<br>~~CO~~<br>~~DG~~|µs<br>~~DG~~|1<br>~~DG~~|



## **Notes:** 

1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets. 

**==> picture [471 x 144] intentionally omitted <==**

**----- Start of picture text -----**<br>
tf tr tSU.DAT<br>SDA 70% 70%<br>30% 30%<br>tf continued below at  A<br>tr tVD.DAT<br>SCL 70% tHD.DAT 70%<br>30% 30%<br>tHD.STA 1/fSCL tLOW 9 [th]  clock cycle<br>S 1 [st]  clock cycle tHIGH<br>tBUF<br>SDA 70%<br>A 30%<br>tSU.STA tHD.STA tVD.ACK tSU.STO<br>SCL 70%<br>30%<br>Sr 9 [th]  clock cycle P S<br>**----- End of picture text -----**<br>


**Figure 1. I[2] C Bus Timing Diagram** 

Page 14 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **3.5 SPI TIMING CHARACTERIZATION** 

Typical Operating Circuit of section 0, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted. 

|**Parameters**<br>**Conditions**<br>**Min**<br>**Typical**<br>**Max**<br>**Units**<br>**Notes**<br>**SPI TIMING**<br>fSCLK, SCLK Clock Frequency<br>7<br>MHz<br>tLOW, SCLK Low Period<br>64<br>ns<br>tHIGH, SCLK High Period<br>64<br>ns<br>tSU.CS, CS Setup Time<br>8<br>ns<br>tHD.CS, CS Hold Time<br>500<br>ns<br>tSU.SDI, SDI Setup Time<br>5<br>ns<br>tHD.SDI, SDI Hold Time<br>7<br>ns<br>tVD.SDO, SDO Valid Time<br>Cload= 20 pF<br>59<br>ns<br>tHD.SDO, SDO Hold Time<br>Cload= 20 pF<br>6<br>ns<br>tDIS.SDO, SDO Output Disable Time<br>50<br>ns<br>~~PT~~<br>~~-—_{| ft~~<br>~~**e**s ee ee~~<br>~~|~~<br>~~e~~<br>~~oT~~<br>~~a~~<br>~~——— ee ee oe ee ee~~<br>~~OOa~~<br>~~OOa~~<br>~~OOa~~<br>~~OOee~~<br>~~**—**{|__| |~~<br>~~|~~<br>~~fF~~<br>~~—~~<br>~~OO~~|**Parameters**<br>**Conditions**<br>**Min**<br>**Typical**<br>**Max**<br>**Units**<br>**Notes**<br>**SPI TIMING**<br>fSCLK, SCLK Clock Frequency<br>7<br>MHz<br>tLOW, SCLK Low Period<br>64<br>ns<br>tHIGH, SCLK High Period<br>64<br>ns<br>tSU.CS, CS Setup Time<br>8<br>ns<br>tHD.CS, CS Hold Time<br>500<br>ns<br>tSU.SDI, SDI Setup Time<br>5<br>ns<br>tHD.SDI, SDI Hold Time<br>7<br>ns<br>tVD.SDO, SDO Valid Time<br>Cload= 20 pF<br>59<br>ns<br>tHD.SDO, SDO Hold Time<br>Cload= 20 pF<br>6<br>ns<br>tDIS.SDO, SDO Output Disable Time<br>50<br>ns<br>~~PT~~<br>~~-—_{| ft~~<br>~~**e**s ee ee~~<br>~~|~~<br>~~e~~<br>~~oT~~<br>~~a~~<br>~~——— ee ee oe ee ee~~<br>~~OOa~~<br>~~OOa~~<br>~~OOa~~<br>~~OOee~~<br>~~**—**{|__| |~~<br>~~|~~<br>~~fF~~<br>~~—~~<br>~~OO~~|**Parameters**<br>**Conditions**<br>**Min**<br>**Typical**<br>**Max**<br>**Units**<br>**Notes**<br>**SPI TIMING**<br>fSCLK, SCLK Clock Frequency<br>7<br>MHz<br>tLOW, SCLK Low Period<br>64<br>ns<br>tHIGH, SCLK High Period<br>64<br>ns<br>tSU.CS, CS Setup Time<br>8<br>ns<br>tHD.CS, CS Hold Time<br>500<br>ns<br>tSU.SDI, SDI Setup Time<br>5<br>ns<br>tHD.SDI, SDI Hold Time<br>7<br>ns<br>tVD.SDO, SDO Valid Time<br>Cload= 20 pF<br>59<br>ns<br>tHD.SDO, SDO Hold Time<br>Cload= 20 pF<br>6<br>ns<br>tDIS.SDO, SDO Output Disable Time<br>50<br>ns<br>~~PT~~<br>~~-—_{| ft~~<br>~~**e**s ee ee~~<br>~~|~~<br>~~e~~<br>~~oT~~<br>~~a~~<br>~~——— ee ee oe ee ee~~<br>~~OOa~~<br>~~OOa~~<br>~~OOa~~<br>~~OOee~~<br>~~**—**{|__| |~~<br>~~|~~<br>~~fF~~<br>~~—~~<br>~~OO~~|**Parameters**<br>**Conditions**<br>**Min**<br>**Typical**<br>**Max**<br>**Units**<br>**Notes**<br>**SPI TIMING**<br>fSCLK, SCLK Clock Frequency<br>7<br>MHz<br>tLOW, SCLK Low Period<br>64<br>ns<br>tHIGH, SCLK High Period<br>64<br>ns<br>tSU.CS, CS Setup Time<br>8<br>ns<br>tHD.CS, CS Hold Time<br>500<br>ns<br>tSU.SDI, SDI Setup Time<br>5<br>ns<br>tHD.SDI, SDI Hold Time<br>7<br>ns<br>tVD.SDO, SDO Valid Time<br>Cload= 20 pF<br>59<br>ns<br>tHD.SDO, SDO Hold Time<br>Cload= 20 pF<br>6<br>ns<br>tDIS.SDO, SDO Output Disable Time<br>50<br>ns<br>~~PT~~<br>~~-—_{| ft~~<br>~~**e**s ee ee~~<br>~~|~~<br>~~e~~<br>~~oT~~<br>~~a~~<br>~~——— ee ee oe ee ee~~<br>~~OOa~~<br>~~OOa~~<br>~~OOa~~<br>~~OOee~~<br>~~**—**{|__| |~~<br>~~|~~<br>~~fF~~<br>~~—~~<br>~~OO~~|
|---|---|---|---|
|**Table 7. SPI Timing Characteristics (7 MHz Operation)**||||
|**Notes:**||||
|1.<br>Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.||||
|**tHIGH**<br>**70%**<br>**30%**<br>**1/fCLK**<br>**tHD;CS**<br>**CS**<br>**SCLK**<br>**70%**<br>**30%**<br>**tSU;CS**<br>**tSU;SDI**<br>**tHD;SDI**<br>**tLOW**<br>~~sf~~<br>~~~\ [-—~~<br>~~—~~||||
|**SDI**<br>**SDO**<br>**MSB OUT**<br>**MSB IN**<br>**LSB IN**<br>**LSB OUT**<br>**tDIS;SDO**<br>**70%**<br>**30%**<br>**70%**<br>**30%**<br>**tVD;SDO**<br>~~XX~~<br>~~aD GD GDGES=~~||||
|**Figure 2. SPI Bus Timing Diagram**||||



## **Notes:** 

Page 15 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **3.6 ABSOLUTE MAXIMUM RATINGS** 

Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.  Exposure to the absolute maximum ratings conditions for extended periods may affect device reliability. 

|**Parameter**|**Rating**|
|---|---|
|Supply Voltage, VDD|-0.5 V to +4 V|
|Supply Voltage, VDDIO|-0.5 V to +4 V|
|REGOUT|-0.5 V to 2 V|
|Input Voltage Level (SA0, FSYNC, SCL, SDA)|-0.5 V to VDD + 0.5 V|
|Acceleration (Any Axis, unpowered)|10,000_g_for 0.2 ms|
|Storage Temperature Range|-40°C to +125°C|
|Electrostatic Discharge (ESD) Protection|2 kV (HBM);<br>250 V (MM)|
|Latch-up|JEDEC Class II (2),125°C<br>±100 mA|



**Table 8. Absolute Maximum Ratings** 

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_**ICG-20660**_ 

## _**4 APPLICATIONS INFORMATION**_ 

|**Pin Number**<br>~~aa~~|**Pin Name**<br>~~aa~~|**Pin Description**<br>~~aa~~|
|---|---|---|
|1<br>~~aa~~<br>~~a~~|VDDIO<br>~~aa~~<br>~~a~~|Digital I/O supply voltage<br>~~aa~~|
|2<br>~~a~~|SCL/SPC<br>~~a~~|I2C serial clock (SCL); SPI serial clock (SPC)|
|3<br>~~a~~|SDA/SDI<br>~~a~~|I2C serial data (SDA); SPI serial data input (SDI)|
|4<br>~~a~~|SA0/SDO<br>~~a~~|I2C slave address LSB (SA0); SPI serial data output (SDO)|
|5<br>~~a~~|CS<br>~~a~~|Chip select (0 = SPI mode; 1 = I2C mode)|
|6<br>~~a~~|INT<br>~~a~~|Interrupt digital output (totem pole or open-drain)|
|7<br>~~a~~|RESV<br>~~a~~|Reserved.  Do not connect.|
|8<br>~~a~~|FSYNC<br>~~a~~|Synchronization digital input (optional).  Connect to GND if unused.|
|9<br>~~a~~|NC<br>~~a~~|Connect to GND or do not connect|
|10<br>~~a~~|NC<br>~~a~~<br>~~a~~|Connect to GND or do not connect|
|11<br>~~a~~<br>~~a~~|NC<br>~~a~~<br>~~a~~|Connect to GND or do not connect|
|12<br>~~a~~<br>~~a~~|NC|Connect to GND or do not connect|
|13<br>~~a~~<br>~~a~~|GND|Connect to GND|
|14<br>~~a~~<br>~~a ~~|REGOUT<br> ~~a~~|Regulator filter capacitor connection|
|15<br>~~a~~|RESV|Reserved. Connect to GND|
|16<br>~~a~~|VDD<br>~~a~~|Power Supply|



**Table 9. Signal Descriptions** 

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16 15 14<br>VDDIO 1 13 GND<br>SCL/SPC 2 12 NC<br>SDA/SDI 3 ICG-20660 11 NC<br>SA0/SDO 4 10 NC<br>CS 5 9 NC<br>6 7 8<br>VDD RESV REGOUT<br>INT RESV FSYNC<br>**----- End of picture text -----**<br>


**==> picture [64 x 72] intentionally omitted <==**

**----- Start of picture text -----**<br>
+Z<br>+Y +X<br>ICG-20660<br>**----- End of picture text -----**<br>


**LGA Package (Top View) 16-pin, 3mm x 3mm x 0.75 mm Typical Footprint and thickness** 

**Orientation of Axes of Sensitivity and Polarity of Rotation** 

**Figure 3. Pin out Diagram for ICG-20660 3 mm x 3 mm x0.75 mm LGA** 

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_**ICG-20660**_ 

## **4.2 TYPICAL OPERATING CIRCUIT** 

**==> picture [458 x 261] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.8 – 3.3VDC<br>VDD<br>C2, 0.1 mF C4, 2.2 mF<br>REGOUT<br>16 15 14<br>AS<br>VDDIO GND aa C1, 0.47 mF<br>1.8 – 3.3 VDC 1 13<br>C3, 10 nF nh SCLSDA SCL/SPCSDA/SDI 23 ICG-20660 1211 NCNC<br>AD0 SA0/SDO 4 10 NC<br>VDDIO<br>CS NC<br>5 9<br>6 7 8<br>RESV<br>INT RESV FSYNC<br>**----- End of picture text -----**<br>


**Figure 4. ICG-20660 LGA Application Schematic** 

## **4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS** 

|**Component**|**Label**|**Specification**|**Quantity**|
|---|---|---|---|
|REGOUT Capacitor|C1|Ceramic, X7R, 0.47 µF ±10%, 2 V|1|
|VDD Bypass Capacitors|C2|Ceramic, X7R, 0.1 µF ±10%, 4 V|1|
||C4|Ceramic, X7R, 2.2 µF ±10%, 4 V|1|
|VDDIO Bypass Capacitor|C3|Ceramic, X7R, 10 nF ±10%, 4 V|1|



**Table 10. Bill of Materials** 

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_**ICG-20660**_ 

## **4.4 BLOCK DIAGRAM** 

**==> picture [387 x 296] intentionally omitted <==**

**----- Start of picture text -----**<br>
ICG-20660<br>INT<br>Self<br>X Accel ADC<br>test Interrupt<br>Status<br>Register<br>CS<br>Self test Y Accel ADC Slave I2C and  SA0 / SDO<br>= S H O IH S - FIFO o SPI Serial  e |<br>Interface SCL / SPC<br>Self  SDA / SDI<br>test Z Accel ADC User & Config<br>Registers<br>s o e ! ) 2 FSYNC<br>Self<br>test X Gyro AD C Sensor<br>Registers<br>Self<br>test Y Gyro ADC<br>= Self test Z Gyro = AD C<br>_  LJ =<br>Temp Sensor ADC<br>[ oT<br>Charge  Bias & LDOs<br>Pump<br>VDD GND REGOUT<br>Signal Conditioning<br>**----- End of picture text -----**<br>


**Figure 5. ICG-20660 Block Diagram** 

## **4.5 OVERVIEW** 

The ICG-20660 is comprised of the following key blocks and functions: 

- Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning 

- Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning 

- Primary I[2] C and SPI serial communications interfaces 

- Self-Test 

- Clocking 

- Sensor Data Registers 

- FIFO 

- Interrupts 

- Digital-Output Temperature Sensor 

- Bias and LDOs 

- Charge Pump 

- Standard Power Modes 

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Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING** 

The ICG-20660 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.  When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate.  This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis.  The full-scale range of the gyro sensors may be digitally programmed to ±125, ±250, or ±500 degrees per second (dps). The ADC sample rate is programmable up to 8,000 samples per second with user-selectable low-pass filters enable a wide range of cut-off frequencies. 

## **4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING** 

The ICG-20660’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The ICG20660’s architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed on a flat surface, it will measure 0 _g_ on the X- and Y-axes and +1 _g_ on the Z-axis. The accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted to ±2 _g_ , ±4 _g_ , ±8 _g_ , or ±16 _g_ . 

## **4.8 I[2] C AND SPI SERIAL COMMUNICATIONS INTERFACES** 

The ICG-20660 communicates to a system processor using either a SPI or an I[2] C serial interface. The ICG-20660 always acts as a slave when communicating to the system processor. The LSB of the I[2] C slave address is set by pin 4 (SA0). 

## **4.8.1 ICG-20660 Solution Using I[2] C Interface** 

In the figure below, the system processor is an I[2] C master to the ICG-20660. 

**==> picture [315 x 240] intentionally omitted <==**

**----- Start of picture text -----**<br>
Interrupt Status  INT Isensor data [2] C Processor Bus: for reading all<br>Register<br>ICG-20660 SA0<br>VDDIO or GND<br>Slave I [2] C<br>or SPI  SCL SCL<br>Serial  System<br>Interface SDA SDA Processor<br>FIFO<br>User & Config<br>Registers<br>Sensor<br>Register<br>Factory<br>Calibration<br>Bias & LDOs<br>VDD GND REGOUT<br>**----- End of picture text -----**<br>


**Figure 6. ICG-20660 Solution Using I[2] C Interface** 

## **4.8.2 ICG-20660 Solution Using SPI Interface** 

In the figure below, the system processor is an SPI master to the ICG-20660. Pins 2, 3, 4, and 5 are used to support the SPC, SDI, SDO, and CS signals for SPI communications. 

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_**ICG-20660**_ 

**==> picture [457 x 383] intentionally omitted <==**

**----- Start of picture text -----**<br>
InvenSense_<br>Processor SPI Bus: for reading all<br>data<br>Interrupt<br>Status  INT<br>Register<br>| CS nCS<br>ICG-20660<br>SDO SDI<br>Slave I [2] C  System<br>or SPI  SPC SPC Processor<br>Serial<br>Interface SDI SDO<br>FIFO<br>i ji<br>Config<br>| Register |<br>Sensor<br>| Register<br>Factory<br>Calibratio<br>| n<br>Bias &<br>LDOs<br>VDD GND REGOUT<br>**----- End of picture text -----**<br>


**Figure 7. ICG-20660 Solution Using SPI Interface** 

## **4.9 SELF-TEST** 

Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can be activated by means of the gyroscope and accelerometer self-test registers (registers 27 and 28). 

When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is used to observe the self-test response. 

The self-test response is defined as follows: 

## SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED 

The self-test response for each gyroscope axis is defined in the gyroscope specification table, while that for each accelerometer axis is defined in the accelerometer specification table. 

When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-test.  When the self-test response exceeds the min/max values, the part is deemed to have failed self-test. It is recommended to use InvenSense MotionApps software for executing self-test. 

For further information on Self-Test please refer to the register map of ICG-20660. 

## **4.10 CLOCKING** 

The ICG-20660 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers.  An on-chip PLL provides flexibility in the allowable inputs for generating this clock. 

Allowable internal sources for generating the internal clock are: 

Page 21 of 58 

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_**ICG-20660**_ 

## a) An internal relaxation oscillator 

b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source The only setting supporting specified performance in all modes is option b).  It is recommended that option b) be used. 

## **4.11 SENSOR DATA REGISTERS** 

The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data.  They are readonly registers, and are accessed via the serial interface.  Data from these registers may be read anytime. 

## **4.12 FIFO** 

The ICG-20660 contains a 512-byte FIFO register that is accessible via the Serial Interface. The FIFO configuration register determines which data is written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, and FSYNC input.  A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst reads.  The interrupt function may be used to determine when new data is available. 

The ICG-20660 allows FIFO read in low-power accelerometer mode. 

For further information regarding the FIFO, please refer to the register map of ICG-20660. 

## **4.13 INTERRUPTS** 

Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt.  Items that can trigger an interrupt are (1) Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO overflow.  The interrupt status can be read from the Interrupt Status register. 

## **4.14 DIGITAL-OUTPUT TEMPERATURE SENSOR** 

An on-chip temperature sensor and ADC are used to measure the ICG-20660 die temperature.  The readings from the ADC can be read from the FIFO or the Sensor Data registers. 

## **4.15 BIAS AND LDOS** 

The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICG-20660. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of Materials for External Components. 

## **4.16 CHARGE PUMP** 

An on-chip charge pump generates the high voltage required for the MEMS oscillator. 

## **4.17 STANDARD POWER MODES** 

The following table lists the user-accessible power modes for ICG-20660. 

|**Mode**|**Name**|**Gyro**|**Accel**|
|---|---|---|---|
|1|Sleep Mode|Off|Off|
|2|Standby Mode|Drive On|Off|
|3|Accelerometer Low-Power Mode|Off|Duty-Cycled|
|4|Accelerometer Low-Noise Mode|Off|On|
|7|6-Axis Low-Noise Mode|On|On|



**Table 11. Standard Power Modes for ICG-20660** 

## **Notes:** 

1. Power consumption for individual modes can be found in section 0. 

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_**ICG-20660**_ 

## _**5 PROGRAMMABLE INTERRUPTS**_ 

The ICG-20660 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. 

|**Interrupt Name**|**Module**|
|---|---|
|Motion Detection|Motion|
|FIFO Overflow|FIFO|
|Data Ready|Sensor Registers|



**Table 12. Table of Interrupt Sources** 

For information regarding the interrupt enable/disable registers and flag registers, please refer to the register map of ICG20660 in this document. 

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_**ICG-20660**_ 

## _**6 DIGITAL INTERFACE**_ 

## **6.1 I[2] C AND SPI SERIAL INTERFACES** 

The internal registers and memory of the ICG-20660 can be accessed using either I[2] C at 400 kHz or SPI at 7 MHz. SPI operates in four-wire mode. 

|**Pin Number**|**Pin Name**|**Pin Description**|
|---|---|---|
|1|VDDIO|Digital I/O supply voltage.|
|4|SA0 / SDO|I2C Slave Address LSB (SA0); SPI serial data output (SDO)|
|2|SCL / SPC|I2C serial clock (SCL); SPI serial clock (SPC)|
|3|SDA / SDI|I2C serial data (SDA); SPI serial data input (SDI)|



## **Table 13. Serial Interface** 

**Note:** To prevent switching into I[2] C mode when using SPI, the I[2] C interface should be disabled by setting the _I2C_IF_DIS_ configuration bit. Setting this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in Section 6.3. 

For further information regarding the _I2C_IF_DIS_ bit, please refer to the register map of ICG-20660. 

## **6.2 I[2] C INTERFACE** 

I[2] C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-directional. In a generalized I[2] C interface implementation, attached devices can be a master or a slave. The master device puts the slave address on the bus, and the slave device with the matching address acknowledges the master. 

The ICG-20660 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz. 

The slave address of the ICG-20660 is b110100X, which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level on pin SA0. This allows two ICG-20660s to be connected to the same I[2] C bus.  When used in this configuration, the address of one of the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high). 

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_**ICG-20660**_ 

## **6.3 I[2] C COMMUNICATIONS PROTOCOL** 

## _START (S) and STOP (P) Conditions_ 

Communication on the I[2] C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGHto-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below). 

Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition. 

**==> picture [366 x 83] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>|<br>SCL<br>S P<br>START condition STOP condition<br>**----- End of picture text -----**<br>


**Figure 8. START and STOP Conditions** 

## _Data Format / Acknowledge_ 

I[2] C data bytes are defined to be 8-bits long.  There is no restriction to the number of bytes transmitted per data transfer. Each byte transferred must be followed by an acknowledge (ACK) signal.  The clock for the acknowledge signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the acknowledge clock pulse. 

If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL LOW, thus forcing the master into a wait state.  Normal data transfer resumes when the slave is ready, and releases the clock line (refer to the following figure). 

**==> picture [421 x 158] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATA OUTPUT BY<br>TRANSMITTER (SDA)<br>N L OOK<br>not acknowledge<br>DATA OUTPUT BY<br>RECEIVER (SDA)<br>acknowledge<br>7<br>SCL FROM<br>1 2 8 9<br>MASTER<br>clock pulse for<br>START  acknowledgement<br>condition<br>**----- End of picture text -----**<br>


**Figure 9. Acknowledge on the I[2] C Bus** 

Page 25 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _Communications_ 

After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8[th] bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device.  Each byte transferred must be followed by an acknowledge bit.  To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of the SCL line.  Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.  However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP condition (P).  A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the exception of start and stop conditions. 

**==> picture [402 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL 1 – 7 8 9 1 – 7 8 9 1 – 7 8 9<br>| S | YT _ P<br>START  ADDRESS R/W ACK DATA ACK DATA ACK STOP<br>condition condition<br>**----- End of picture text -----**<br>


**Figure 10. Complete I[2] C Data Transfer** 

To write the internal ICG-20660 registers, the master transmits the start condition (S), followed by the I[2] C address and the write bit (0). At the 9[th] clock cycle (when the clock is high), the ICG-20660 acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the ICG-20660 acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICG-20660 automatically increments the register address and loads the data to the appropriate register. The following figures show single and two-byte write sequences. 

## _Single-Byte Write Sequence_ 

|Master|S|AD+W||RA||DATA||P|
|---|---|---|---|---|---|---|---|---|
|Slave|||ACK||ACK||ACK||



_Burst Write Sequence_ 

|Master|S|AD+W||RA||DATA||DATA||P|
|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||ACK||ACK||ACK||ACK||



To read the internal ICG-20660 registers, the master sends a start condition, followed by the I[2] C address and a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICG-20660, the master transmits a start signal followed by the slave address and read bit. As a result, the ICG-20660 sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9[th] clock cycle. The following figures show single and two-byte read sequences. 

Page 26 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _Single-Byte Read Sequence_ 

|Master|S|AD+W||RA||S|AD+R|||NACK|P|
|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||ACK||ACK|||ACK|DATA|||



## _Burst Read Sequence_ 

|Master|S|AD+W||RA||S|AD+R|||ACK||NACK|P|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Slave|||ACK||ACK|||ACK|DATA||DATA|||



## **6.4 I[2] C TERMS** 

|**Signal**|**Description**|
|---|---|
|S|Start Condition: SDAgoes from high to low while SCL is high|
|AD|Slave I2C address|
|W|Write bit(0)|
|R|Read bit(1)|
|ACK|Acknowledge: SDA line is low while the SCL line is high at the 9thclock cycle|
|NACK|Not-Acknowledge: SDA line stays high at the 9thclock cycle|
|RA|ICG-20660 internal register address|
|DATA|Transmit or received data|
|P|Stopcondition: SDAgoingfrom low to high while SCL is high|



**Table 14. I[2] C Terms** 

Page 27 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **6.5 SPI INTERFACE** 

SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICG-20660 always operates as a Slave device during standard Master-Slave SPI operation. 

With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master. 

CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active devices. 

## _SPI Operational Features_ 

1. Data is delivered MSB first and LSB last. 

2. Data is latched on the rising edge of SPC. 

3. Data should be transitioned on the falling edge of SPC. 

4. The maximum frequency of SPC is 7 MHz. 

5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the SPI Address, and the following byte(s) contain(s) the SPI data.  The first bit of the first byte contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address.  In cases of multiple-byte Read/Writes, data is two or more bytes: 

## _SPI Address format_ 

|**MSB**|||||||**LSB**|
|---|---|---|---|---|---|---|---|
|R/W|A6|A5|A4|A3|A2|A1|A0|
|_SPI Data format_||||||||
|**MSB**|||||||**LSB**|
|D7|D6|D5|D4|D3|D2|D1|D0|



_SPI Data format_ 

6. Supports Single or Burst Read/Writes. 

**==> picture [228 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
SPC<br>SDI<br>SPI Master SDO SPI Slave 1<br>CS1  CS<br>CS2<br>SPC<br>SDI<br>SDO<br>SPI Slave 2<br>CS<br>**----- End of picture text -----**<br>


**Figure 11. Typical SPI Master/Slave Configuration** 

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_**ICG-20660**_ 

## _**7 SERIAL INTERFACE CONSIDERATIONS**_ 

## **7.1 ICG-20660 SUPPORTED INTERFACES** 

The ICG-20660 supports I[2] C communications on its serial interface **.** 

The ICG-20660’s I/O logic levels are set to be VDDIO. 

The figure below depicts a sample circuit of ICG-20660. It shows the relevant logic levels and voltage connections. 

**==> picture [352 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDDIO<br>VDD_IO<br>(0V - VDDIO) SYSTEM BUS<br>System<br>VDD Processor IO<br>VDDIO<br>VDD INT (0V - VDDIO)<br>SDA (0V - VDDIO)<br>(0V - VDDIO) SCL (0V - VDDIO)<br>SYNC<br>VDDIO<br>ICG-20660<br>| VDDIO<br>(0V, VDDIO)<br>SA0<br>**----- End of picture text -----**<br>


**Figure 12. I/O Levels and Connections** 

Page 29 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**8 ASSEMBLY**_ 

This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) gyros packaged in LGA package. 

## **8.1 ORIENTATION OF AXES** 

The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure. 

**==> picture [86 x 110] intentionally omitted <==**

**----- Start of picture text -----**<br>
+Z<br>+Z +Y<br>+Y<br>+X +X<br>ICG-20660<br>**----- End of picture text -----**<br>


**Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation** 

Page 30 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **8.2 PACKAGE DIMENSIONS** 

16 Lead LGA (3 mm x 3 mm x 0.75 mm) NiAu pad finish 

**Figure 8. Package Dimensions** 

Page 31 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

|~~Po~~|~~Po~~|**DIMENSIONS IN MILLIMETERS**<br>~~TT~~<br>~~Po~~|**DIMENSIONS IN MILLIMETERS**<br>~~TT~~<br>~~Po~~|**DIMENSIONS IN MILLIMETERS**<br>~~TT~~<br>~~Po~~|
|---|---|---|---|---|
|~~Po~~|**SYMBOLS**<br>~~Po~~|**MIN**<br>~~Po~~|**NOM**<br>~~Po~~|**MAX**<br>~~Po~~|
|**Total Thickness**<br>~~PO~~|**A**<br>~~PO~~|0.7<br>~~PO~~|0.75<br>~~PO~~|0.8<br>~~PO~~|
|**Substrate Thickness**<br>~~PO~~<br>~~QO~~|**A1**<br>~~PO~~<br>~~QO~~|0.105 REF<br>~~PO~~<br>~~QO~~|||
|**Mold Thickness**<br>~~GO~~<br>~~ee~~|**A2**<br>~~GO~~<br>~~ee~~|0.63 REF<br>~~GO~~<br>~~ee~~|||
|**Body Size**<br>~~ee~~|**D**<br>~~ee~~|2.9<br>~~ee~~|3|3.1|
||**E**<br>~~ee~~<br>~~es~~|2.9<br>~~ee~~<br>~~es~~|3<br>~~es~~|3.1<br>~~es~~|
|**Lead Width**<br>~~ee~~<br>~~es~~|**W**<br>~~ee~~<br>~~es~~<br>~~es~~|0.2<br>~~ee~~<br>~~es~~|0.25<br>~~es~~|0.3<br>~~es~~|
|**Lead Length**<br>~~es~~|**L**<br>~~es~~<br>~~es~~|0.3<br>~~es~~|0.35<br>~~es~~|0.4<br>~~es~~|
|**Lead Pitch**<br>~~GO~~|**e**<br>~~es~~<br>~~GO~~|0.5 BSC<br>~~GO~~|||
|**Lead Count**<br>~~aff~~|**n**<br>~~ff~~|16<br>~~ff~~|||
|**Edge Ball Center to Center**<br>~~ff~~|**D1**<br>~~ff~~|2 BSC<br>~~ff~~|||
||**E1**<br>~~ff~~<br>~~ee~~|1 BSC<br>~~ff~~<br>~~ee~~|||
|**Body Center to Contact Ball**<br>~~ff~~<br>~~Bf~~|**SD**<br>~~ff~~<br>~~Bf~~|---<br>~~ff~~|||
||**SE**<br>~~Bf~~<br>~~ee~~|---<br>~~ee~~|||
|**Ball Width**<br>~~DG~~|**b**<br>~~DG~~|---<br>~~DG~~|---<br>~~DG~~|---<br>~~DG~~|
|**Ball Diameter**<br>~~a~~||---|||
|**Ball Opening**<br>~~a~~||---|||
|**Ball Pitch**<br>~~a~~<br>~~es~~<br>~~a~~|**e1**<br>~~es~~|---<br>~~es~~|||
|**Ball Count**<br>~~es~~<br>~~a~~<br>~~a~~|**n1**<br>~~es~~<br>|---<br>~~es~~<br>|||
|**Pre-Solder**<br>~~a~~<br>~~a~~||---<br>|---<br>|---<br>|
|**Package Edge Tolerance**<br>~~ans~~<br>~~a~~|**aaa**<br>~~ns~~|0.1<br>~~ns~~|||
|**Mold Flatness**<br>~~ns~~<br>~~a~~<br>~~a~~|**bbb**<br>~~ns~~|0.2<br>~~ns~~|||
|**Coplanarity**<br>~~a~~<br>~~a~~<br>~~a~~|**ddd**|0.08|||
|**Ball Offset(Package)**<br>~~a~~<br>~~a~~|**eee**|---|||
|**Ball Offset(Ball)**<br>~~a~~<br>~~a~~|**fff**<br>~~nn~~|---<br>~~(~~|||
|**Lead Edge to Package Edge **<br>~~a~~<br>~~es~~|**M**<br>~~es~~<br>~~nn~~|0.01<br>~~es~~<br>~~(~~|0.06<br>~~es~~|0.11<br>~~es~~|



**Table 15. Package Dimensions** 

Page 32 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**9 PART NUMBER PACKAGE MARKING**_ 

The part number package marking for ICG-20660 devices is summarized below: 

|**Part Number**|**Part Number Package Marking**|
|---|---|
|ICG-20660|IC2660|



**Table 16. Package Number Package Marking** 

Page 33 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**10 REFERENCE**_ 

Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information: 

- Manufacturing Recommendations 

   - Assembly Guidelines and Recommendations 

   - PCB Design Guidelines and Recommendations 

   - MEMS Handling Instructions 

   - ESD Considerations 

   - Reflow Specification 

   - Storage Specifications 

   - Package Marking Specification 

   - Tape & Reel Specification 

   - Reel & Pizza Box Label 

   - Packaging 

   - Representative Shipping Carton Label 

- Compliance 

   - Environmental Compliance 

   - DRC Compliance 

   - Compliance Declaration Disclaimer 

Page 34 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**11 REGISTER MAP**_ 

The following table lists the register map for the ICG-20660. 

The device will come up in sleep mode upon power-up. In order to take the device out of the sleep mode set the PWR_MGMT_1[6] = 0 in register 107 (sleep mode bit in power management register). 

|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Accessible in**<br>**Sleep and LPA**<br>**Modes?**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|00<br>~~ee~~<br>~~a~~|00<br>~~ee~~<br>~~a~~|SELF_TEST_X_GYRO<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~|XG_ST_DATA[7:0]||||||||
|01<br>~~ee~~<br>~~a~~<br>~~SER~~|01<br>~~ee~~<br>~~a~~<br>~~SER~~|SELF_TEST_Y_GYRO<br>~~ee ~~<br>~~ee~~<br>~~SERSEE~~|READ/<br>WRITE<br> ~~ee~~<br>~~ee~~<br>~~SEE~~|N<br>~~ee~~<br>~~ee~~<br>~~SEE~~|YG_ST_DATA[7:0]<br>||||||||
|02<br>~~a~~<br>~~SER~~|02<br>~~a~~<br>~~SER~~|SELF_TEST_Z_GYRO<br>~~ee ~~<br>~~SERSEE~~|READ/<br>WRITE<br> ~~ee~~<br>~~SEE~~|N<br>~~ee~~<br>~~SEERE~~|ZG_ST_DATA[7:0]<br>~~RE~~||||||||
|04<br>~~SER~~|04<br>~~SER~~|XG_OFFS_TC_H<br>~~SERSEE~~|READ/<br>WRITE<br>~~SEE~~|N<br>~~SEERE~~|-<br>~~RE~~|-<br>~~RE~~|-<br>~~RE~~|-<br>~~RE~~|-<br>~~RE~~|-<br>~~RE~~|XG_OFFS_TC<br>_H [9]<br>~~RE~~|XG_OFFS_TC<br>_H [8]<br>~~RE~~|
|05<br>~~SER~~|05<br>~~SER~~|XG_OFFS_TC_L<br>~~SER SEE~~|READ/<br>WRITE<br>~~SEE~~|N<br>~~SEERE~~|XG_OFFS_TC_L [7:0]<br>~~RE~~||||||||
|07|07|YG_OFFS_TC_H|READ/<br>WRITE|N|-|-|-|-|-|-|YG_OFFS_TC<br>_H [9]|YG_OFFS_TC<br>_H [8]|
|08|08|YG_OFFS_TC_L|READ/<br>WRITE|N|YG_OFFS_TC_L [7:0]||||||||
|0A|10|ZG_OFFS_TC_H|READ/<br>WRITE|N|-|-|-|-|-|-|ZG_OFFS_TC<br>_H [9]|ZG_OFFS_TC<br>_H [8]|
|0B|11|ZG_OFFS_TC_L|READ/<br>WRITE|N|ZG_OFFS_TC_L [7:0]||||||||
|0D|13|SELF_TEST_X_ACCEL|READ/<br>WRITE|N|XA_ST_DATA[7:0]||||||||
|0E|14|SELF_TEST_Y_ACCEL|READ/<br>WRITE|N|YA_ST_DATA[7:0]||||||||
|0F<br>~~ee~~|15<br>~~ee~~|SELF_TEST_Z_ACCEL<br>~~ee~~|READ/<br>WRITE<br>~~ee~~|N<br>~~ee~~|ZA_ST_DATA[7:0]||||||||
|13<br>~~ee~~<br>~~ee~~|19<br>~~ee~~<br>~~ee~~|XG_OFFS_USRH<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~|X_OFFS_USR [15:8]||||||||
|14<br>~~ee~~<br>~~ee~~<br>~~ee~~|20<br>~~ee~~<br>~~ee~~<br>~~ee~~|XG_OFFS_USRL<br>~~ee ~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br> ~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|X_OFFS_USR [7:0]||||||||
|15<br>~~ee~~<br>~~ee~~<br>~~a~~|21<br>~~ee~~<br>~~ee~~<br>~~a~~|YG_OFFS_USRH<br>~~ee ~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br> ~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|Y_OFFS_USR [15:8]||||||||
|16<br>~~ee~~<br>~~a~~<br>~~a~~|22<br>~~ee~~<br>~~a~~<br>~~a~~|YG_OFFS_USRL<br>~~ee ~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br> ~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|Y_OFFS_USR [7:0]||||||||
|17<br>~~a~~<br>~~a~~<br>~~a~~|23<br>~~a~~<br>~~a~~<br>~~a~~|ZG_OFFS_USRH<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|Z_OFFS_USR [15:8]||||||||
|18<br>~~a~~<br>~~a~~<br>~~a~~|24<br>~~a~~<br>~~a~~<br>~~a~~|ZG_OFFS_USRL<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee ~~<br>~~ee~~<br>~~ee~~|N<br> ~~ee~~<br>~~ee~~<br>~~ee~~|Z_OFFS_USR [7:0]||||||||
|19<br>~~a~~<br>~~a~~<br>~~a~~|25<br>~~a~~<br>~~a~~<br>~~a~~|SMPLRT_DIV<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee ~~<br>~~ee~~<br>~~ee~~|Y<br> ~~ee~~<br>~~ee~~<br>~~ee~~|SMPLRT_DIV[7:0]<br>~~sses~~||||||||
|1A<br>~~a~~<br>~~a~~<br>~~a~~|26<br>~~a~~<br>~~a~~<br>~~a~~|CONFIG<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ss~~<br>~~es~~|FIFO_<br>MODE<br>~~ss~~<br>~~ed~~|EXT_SYNC_SET[2:0]<br>~~es~~<br>~~eees~~|||DLPF_CFG[2:0]<br>~~es~~|||
|1B<br>~~a~~<br>~~a~~<br>~~a~~|27<br>~~a~~<br>~~a~~<br>~~a~~|GYRO_CONFIG<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee ~~<br>~~ee~~<br>~~ee~~|XG_ST<br> ~~ss~~<br>~~es~~<br>~~ss~~|YG_ST<br>~~ss ~~<br>~~ed~~<br>~~ss~~|ZG_ST<br> ~~es~~<br>~~ee~~<br>~~es~~|FS_SEL [1:0]<br>~~es~~<br>~~es~~<br>~~es~~||-<br>~~es~~|FCHOICE_B[1:0]||
|1C<br>~~a~~<br>~~a~~<br>~~a~~|28<br>~~a~~<br>~~a~~<br>~~a~~|ACCEL_CONFIG<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee ~~<br>~~ee~~<br>~~ee~~|N<br> ~~ee~~<br>~~ee~~<br>~~ee~~|XA_ST<br>~~es ~~<br>~~ss~~<br>~~es~~|YA_ST<br> ~~ed ~~<br>~~ss~~<br>~~es~~|ZA_ST<br> ~~ee~~<br>~~es~~<br>~~es~~|ACCEL_FS_SEL[1:0]<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~ns~~||-<br> ~~es~~|||
|1D<br>~~a ~~<br>~~a~~<br>~~a~~|29<br> ~~a~~<br>~~a~~<br>~~es~~|ACCEL_CONFIG 2<br>~~ee~~<br>~~ee~~<br>~~es~~|READ/<br>WRITE<br>~~ee~~<br>~~ee~~|Y<br>~~ee ~~<br>~~ee~~<br>~~(On~~|FIFO_SIZE<br> ~~ss~~<br>~~es~~<br>~~(On~~<br>~~S(O~~||DEC2_CFG<br>~~eses~~<br>~~es~~<br>~~S(O~~<br>~~QO~~||ACCEL_FCHOI<br>CE_B<br>~~es~~<br>~~ns~~<br>~~QO~~|A_DLPF_CFG|||
|1E<br>~~a~~<br>~~a~~<br>~~a~~|30<br>~~a~~<br>~~es~~<br>~~es~~|LP_MODE_CFG<br>~~ee~~<br>~~es~~<br>~~es~~|R/W<br>~~ee~~<br>~~rs~~|N<br>~~ee~~<br>~~(On~~<br>~~GU~~|-<br>~~es~~<br>~~(On~~|-<br>~~es ~~<br>~~S(O~~|-<br> ~~es~~<br>~~S(O~~|-<br>~~es~~<br>~~QO~~|-<br>~~ns~~<br>~~QO~~|LPOSC_CLKSEL|||
|1F<br>~~a~~<br>~~a~~|31<br>~~es ~~<br>~~es~~|ACCEL_WOM_THR<br> ~~es~~<br>~~es~~|R/W<br>~~rs~~|N<br>~~(On~~<br>~~GU~~|WOM_THR[7:0]<br>~~(On~~<br>~~S(O~~<br>~~QO~~||||||||



Page 35 of 58 

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## _**ICG-20660**_ 

|**Addr**<br>**(Hex)**|**Addr**<br>**(Dec.)**|**Register Name**|**Serial**<br>**I/F**|**Accessible in**<br>**Sleep and LPA**<br>**Modes?**|**Bit7**|**Bit6**|**Bit5**|**Bit4**|**Bit3**|**Bit2**|**Bit1**|**Bit0**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|23<br>~~a~~|35<br>~~a~~|FIFO_EN<br>~~ee~~|READ/<br>WRITE<br>~~ee ee~~|N<br>~~ee~~|TEMP<br>_FIFO_EN<br>~~es~~|XG_FIFO_EN<br>~~errs~~|YG_FIFO_EN<br>~~re~~|ZG_FIFO_EN<br>~~rs~~|ACCEL_FIFO_<br>EN<br>~~es~~|-<br>~~es~~|-<br>~~ed~~|-|
|36<br>~~a ~~|54<br> ~~a~~|FSYNC_INT<br>~~ee~~|READ to<br>CLEAR<br>~~ee ee~~|N<br>~~ee~~|FSYNC_INT<br>~~es ~~|-<br> ~~errs ~~|-<br> ~~re ~~|-<br> ~~rs ~~|-<br> ~~es~~|-<br>~~es ~~|-<br> ~~ed~~|-|
|37|55|INT_PIN_CFG|READ/<br>WRITE|Y|INT_LEVEL|INT_OPEN|LATCH<br>_INT_EN|INT_RD<br>_CLEAR|FSYNC_INT_L<br>EVEL|FSYNC<br>_INT_MODE_<br>EN|-|-|
|38|56|INT_ENABLE|READ/<br>WRITE|Y|WOM_EN|||FIFO<br>_OFLOW<br>_EN|-|-|-|DATA_RDY_I<br>NT_EN|
|3A<br>~~a~~|58<br>~~se~~|INT_STATUS<br>~~se~~|READ to<br>CLEAR<br>~~es~~|N<br>~~Ge~~|WOM_X_IN<br>T|WOM_Y_INT|WOM_Z_INT|FIFO<br>_OFLOW<br>_INT|-|-|-|DATA<br>_RDY_INT|
|3B<br>~~a~~<br>~~a~~|59<br>~~se~~<br>~~a~~|ACCEL_XOUT_H<br>~~se~~<br>~~es es~~|READ<br>~~es~~<br>~~es~~|N<br>~~Ge~~<br>~~Ge~~|ACCEL_XOUT_H[15:8]||||||||
|3C<br>~~a ~~<br>~~a~~|60<br> ~~se~~<br>~~a~~|ACCEL_XOUT_L<br>~~se~~<br>~~es es~~|READ<br>~~es~~<br>~~es~~|N<br>~~Ge~~<br>~~Ge~~|ACCEL_XOUT_L[7:0]||||||||
|3D<br>~~a~~<br>~~a~~|61<br>~~a~~<br>~~ss~~|ACCEL_YOUT_H<br>~~es es~~<br>~~ss~~|READ<br>~~es~~<br>~~se~~|N<br>~~Ge~~<br>~~se~~|ACCEL_YOUT_H[15:8]||||||||
|3E<br>~~a~~<br>~~aa~~<br><br>~~a~~|62<br>~~ss~~<br>~~aa~~<br>~~ss~~|ACCEL_YOUT_L<br>~~ss ~~<br>~~aa~~<br>~~ss~~|READ<br> ~~se~~<br>~~rs~~|N<br>~~se~~<br>~~eG~~|ACCEL_YOUT_L[7:0]<br>~~eG~~||||||||
|3F<br>~~a~~<br>~~a~~|63<br>~~ass~~|ACCEL_ZOUT_H<br>~~ss~~|READ<br>~~rs~~|N<br>~~eG~~|ACCEL_ZOUT_H[15:8]<br>~~eG~~||||||||
|40<br>~~a~~<br>~~a~~<br>~~a~~|64<br>~~ass~~<br>~~a~~<br>~~ss~~|ACCEL_ZOUT_L<br>~~ss ~~<br>~~ss~~|READ<br> ~~rs~~<br>~~rs~~|N<br>~~eG~~<br>~~eG~~|ACCEL_ZOUT_L[7:0]<br>~~eG~~<br>~~eG~~||||||||
|41<br>~~a~~|65<br>~~ss~~|TEMP_OUT_H<br>~~ss~~|READ<br>~~rs~~|N<br>~~eG~~|TEMP_OUT[15:8]<br>~~eG~~||||||||
|42<br>~~a ~~<br>~~aa~~<br><br>~~a~~|66<br> ~~ss~~<br>~~aa~~<br>~~ss~~|TEMP_OUT_L<br>~~ss~~<br>~~aa~~<br>~~ss~~|READ<br>~~rs~~<br>~~rs~~|N<br>~~eG~~<br>~~eG~~|TEMP_OUT[7:0]<br>~~eG~~<br>~~eG~~||||||||
|43<br>~~a~~<br>~~a~~|67<br>~~ass~~|GYRO_XOUT_H<br>~~ss~~|READ<br>~~rs~~|N<br>~~eG~~|GYRO_XOUT[15:8]<br>~~eG~~||||||||
|44<br>~~a~~<br>~~a~~<br>~~a~~|68<br>~~ass~~<br>~~a~~<br>~~ss~~|GYRO_XOUT_L<br>~~ss ~~<br>~~ss~~|READ<br> ~~rs~~<br>~~rs~~|N<br>~~eG~~<br>~~eG~~|GYRO_XOUT[7:0]<br>~~eG~~<br>~~eG~~||||||||
|45<br>~~a~~|69<br>~~ss~~|GYRO_YOUT_H<br>~~ss~~|READ<br>~~rs~~|N<br>~~eG~~|GYRO_YOUT[15:8]<br>~~eG~~||||||||
|46<br>~~a ~~<br>~~aa~~<br><br>~~a~~|70<br> ~~ss~~<br>~~aa~~<br>~~ss~~|GYRO_YOUT_L<br>~~ss~~<br>~~aa~~<br>~~ss~~|READ<br>~~rs~~<br>~~rs~~|N<br>~~eG~~<br>~~eG~~|GYRO_YOUT[7:0]<br>~~eG~~<br>~~eG~~||||||||
|47<br>~~a~~<br>~~a~~|71<br>~~ass~~|GYRO_ZOUT_H<br>~~ss~~|READ<br>~~rs~~|N<br>~~eG~~|GYRO_ZOUT[15:8]<br>~~eG~~||||||||
|48<br>~~a~~<br>~~a~~<br>~~a~~|72<br>~~ass~~<br>~~a~~<br>~~a~~|GYRO_ZOUT_L<br>~~ss ~~<br>~~ss~~<br>~~ee~~|READ<br> ~~rs~~<br>~~ss~~<br>~~ee~~|N<br>~~eG~~<br>~~ee~~|GYRO_ZOUT[7:0]<br>~~eG~~<br>~~eeeeeses ee~~<br>~~ee~~||||||||
|68<br>~~a~~<br>~~a~~|104<br>~~a~~<br>~~a~~|SIGNAL_PATH_RESET<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee ee~~|N<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~es~~|-<br>~~es~~|-<br>~~es ee~~|-<br>~~ee~~|-<br>~~ee~~|ACCEL<br>_RST|TEMP<br>_RST|
|69<br>~~a ~~<br>~~a~~<br>~~a~~|105<br> ~~a~~<br>~~a~~<br>~~a~~|ACCEL_INTEL_CTRL<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|ACCEL_INTE<br>L_EN<br>~~ee ~~<br>~~ee~~<br>~~ee~~|ACCEL_INTEL<br>_MODE<br> ~~ee ~~<br>~~es~~<br>~~ee~~|-<br> ~~es es ee~~<br>~~eeee~~||-<br>~~ee~~<br>~~ee~~<br>~~eeee~~||--|--|
|6A<br>~~a~~<br>~~a~~<br>~~a~~|106<br>~~a~~<br>~~a~~<br>~~a~~|USER_CTRL<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~|FIFO_EN<br>~~es~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|I2C_IF<br>_DIS<br>~~ee~~|-<br>~~ee~~|FIFO<br>_RST<br>~~ee~~|-|SIG_COND<br>_RST|
|6B<br>~~a~~<br>~~a~~<br>~~a~~|107<br>~~a~~<br>~~a~~<br>~~a~~|PWR_MGMT_1<br>~~ee~~<br>~~ee~~<br>~~ee~~|READ/<br>WRITE<br>~~ee ~~<br>~~ee~~<br>~~ee es~~|Y<br> ~~ee~~<br>~~ee~~<br>~~es~~|DEVICE_RES<br>ET<br>~~ee ~~<br>~~ee~~<br>~~ee~~|SLEEP<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|CYCLE<br> ~~ee ~~<br>~~ee~~<br>~~ee~~|GYRO_<br>STANDBY<br> ~~ee ~~<br>~~es~~|TEMP_DIS<br> ~~ee ~~<br>~~ee~~|CLKSEL[2:0]<br> ~~ee~~<br>~~es~~|||
|6C<br>~~a~~<br>~~a~~<br>~~a~~|108<br>~~a~~<br>~~a~~<br>~~a~~|PWR_MGMT_2<br>~~ee~~<br>~~ee~~<br>~~Ge~~|READ/<br>WRITE<br>~~ee ~~<br>~~ee es~~<br>~~Ge re~~|Y<br> ~~ee~~<br>~~es~~<br>~~re~~|FIFO_LP_EN<br>~~ee ~~<br>~~ee~~|-<br> ~~ee ~~<br>~~ee~~|STBY_XA<br> ~~ee~~<br>~~ee~~|STBY_YA<br>~~es~~|STBY_ZA<br>~~ee~~|STBY_XG<br>~~es~~|STBY_YG|STBY_ZG|
|72<br>~~a~~<br>~~a~~<br>~~a~~|114<br>~~a~~<br>~~a~~<br>~~ss~~|FIFO_COUNTH<br>~~ee~~<br>~~Ge~~<br>~~ss~~|READ<br>~~ee es~~<br>~~Ge re~~<br>~~re~~|Y<br>~~es ~~<br>~~re~~|-<br> ~~ee ee ee ~~|||FIFO_COUNT[12:8]<br> ~~es ee~~<br>~~es~~|||||
|73<br>~~a~~<br>~~a~~<br>~~a~~|115<br>~~a~~<br>~~ss~~<br>~~a~~|FIFO_COUNTL<br>~~Ge~~<br>~~ss~~<br>~~ee~~|READ<br>~~Ge re~~<br>~~re~~<br>~~ee ee~~|Y<br>~~re~~<br>~~ee~~|FIFO_COUNT[7:0]||||||||
|74<br>~~a ~~<br>~~a~~<br>~~a~~|116<br> ~~ss~~<br>~~a~~<br>~~se~~|FIFO_R_W<br>~~ss ~~<br>~~ee~~<br>~~se~~|READ/<br>WRITE<br> ~~re~~<br>~~ee ee~~<br>~~rs~~|Y<br>~~ee~~<br>~~Ge~~|FIFO_DATA[7:0]||||||||
|75<br>~~a ~~<br>~~a~~<br>~~a~~|117<br> ~~a~~<br>~~se~~<br>~~a~~|WHO_AM_I<br>~~ee~~<br>~~se~~<br>~~ie~~|READ<br>~~ee ee~~<br>~~rs~~<br>~~ie ee~~|N<br>~~ee~~<br>~~Ge~~<br>~~ee~~|WHOAMI[7:0]||||||||
|77<br>~~a ~~<br>~~a~~<br>~~a~~|119<br> ~~se~~<br>~~a~~<br>~~a~~|XA_OFFSET_H<br>~~se ~~<br>~~ie~~<br>~~ie~~|READ/<br>WRITE<br> ~~rs~~<br>~~ie ee~~<br>~~ie ee~~|N<br>~~Ge~~<br>~~ee~~<br>~~ee~~|XA_OFFS [14:7]||||||||
|78<br>~~a ~~<br>~~a~~<br>~~a~~|120<br> ~~a~~<br>~~a~~<br>~~a~~|XA_OFFSET_L<br>~~ie~~<br>~~ie~~<br>~~a~~|READ/<br>WRITE<br>~~ie ee~~<br>~~ie ee~~<br>~~i~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|XA_OFFS [6:0]|||||||-|
|7A<br>~~a ~~<br>~~a~~<br>~~a~~|122<br> ~~a~~<br>~~a~~<br>~~a~~|YA_OFFSET_H<br>~~ie~~<br>~~a~~<br>~~ie~~|READ/<br>WRITE<br>~~ie ee~~<br>~~i~~<br>~~ie~~|N<br>~~ee~~<br>~~ee~~<br>~~ee~~|YA_OFFS [14:7]||||||||
|7B<br>~~a ~~<br>~~a~~<br>~~a~~|123<br> ~~a ~~<br>~~a~~<br>~~a~~|YA_OFFSET_L<br> ~~a~~<br>~~ie~~<br>~~i~~|READ/<br>WRITE<br>~~i ~~<br>~~ie~~<br>~~i~~|N<br> ~~ee~~<br>~~ee~~<br>~~ee~~|YA_OFFS [6:0]|||||||-|
|7D<br>~~a ~~<br>~~a~~|125<br> ~~a~~<br>~~a~~|ZA_OFFSET_H<br>~~ie~~<br>~~i~~|READ/<br>WRITE<br>~~ie ~~<br>~~i~~|N<br> ~~ee~~<br>~~ee~~|ZA_OFFS [14:7]||||||||
|7E<br>~~a ~~<br>~~a ~~|126<br> ~~a~~<br> ~~a~~|ZA_OFFSET_L<br>~~i~~<br>~~ee~~|READ/<br>WRITE<br>~~i ~~<br>~~ee~~|N<br> ~~ee~~<br>~~ee~~|ZA_OFFS [6:0]<br>~~ee~~|||||||-<br>~~ee~~|



## **Table 17. ICG-20660 register map** 

**Note:** Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value. 

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_**ICG-20660**_ 

In the detailed register tables that follow, register names are in capital letters, while register values are in capital letters and italicized.  For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most significant bits, _ACCEL_XOUT_ [15:8], of the 16-bit X-Axis accelerometer measurement, _ACCEL_XOUT_ . 

The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-programmed values and will not be 0x00 after reset. 

- Register 107 (0x01) Power Management 1 

- Register 117 (0x91) WHO_AM_I 

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_**ICG-20660**_ 

## _**12 REGISTER DESCRIPTIONS**_ 

This section describes the function and contents of each register within the ICG-20660. 

**Note:** The device will come up in active mode upon power-up. 

## **12.1 REGISTERS 0 TO 2 – GYROSCOPE SELF-TEST REGISTERS** 

**Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO Type: READ/WRITE Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)** 

|**REGISTER**|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|---|
|SELF_TEST_X_GYRO|[7:0]|XG_ST_DATA[7:0]|The value in this register indicates the self-test output<br>generated during manufacturing tests.  This value is to be<br>used to check against subsequent self-test outputs<br>performed by the end user.|
|SELF_TEST_Y_GYRO|[7:0]|YG_ST_DATA[7:0]|The value in this register indicates the self-test output<br>generated during manufacturing tests.  This value is to be<br>used to check against subsequent self-test outputs<br>performed by the end user.|
|SELF_TEST_Z_GYRO|[7:0]|ZG_ST_DATA[7:0]|The value in this register indicates the self-test output<br>generated during manufacturing tests.  This value is to be<br>used to check against subsequent self-test outputs<br>performed by the end user.|



The equation to convert self-test codes in OTP to factory self-test measurement is: 

**==> picture [210 x 13] intentionally omitted <==**

where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the SelfTest value (ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation: 

**==> picture [256 x 30] intentionally omitted <==**

## **12.2 REGISTER 4 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER** 

**Register Name: XG_OFFS_TC_H** 

**Register Type: READ/WRITE Register Address: 04 (Decimal); 04 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:2]**|-|Reserved|
|**[1:0]**|XG_OFFS_TC_H[9:8]|Bits 9 and 8 of the 10-bit offset of X gyroscope (2’s complement)|



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_**ICG-20660**_ 

## **12.3 REGISTER 5 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER Register Name: XG_OFFS_TC_L** 

**Type: READ/WRITE Register Address: 05 (Decimal); 05 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|XG_OFFS_TC_L[7:0]]|Bits 7 to 0 of the 10-bit offset of X gyroscope (2’s complement)|



**Description:** 

The temperature compensation (TC) registers are used to reduce gyro offset variation due to temperature change. The TC feature is always enabled. However the compensation only happens when a TC coefficient is programed during factory trim which gets loaded into these registers at power up or after a _DEVICE_RESET_ . If these registers contain a value of zero, temperature compensation has no effect on the offset of the chip. The TC registers have a 10-bit magnitude and sign adjustment in all full scale modes with a resolution of 2.52 mdps/C steps. 

If these registers contain a non-zero value after power up, the user may write zeros to them to see the offset values without TC with temperature variation. Note that doing so may result in offset values that exceed data sheet “Initial ZRO Tolerance” in other than normal ambient temperature (~25 °C). The TC coefficients maybe restored by the user with a power up or a _DEVICE_RESET_ . 

The above description also applies to registers 7-8 and 10-11. 

- **12.4 REGISTER 07 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER** 

**Register Name: YG_OFFS_TC_H Register Type: READ/WRITE Register Address: 07 (Decimal); 07 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:2]**|-|Reserved|
|**[1:0]**|YG_OFFS_TC_H[9:8]|Bits 9 and 8 of the 10-bit offset of Y gyroscope (2’s complement)|



- **12.5 REGISTER 08 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER** 

**Register Name: YG_OFFS_TC_L** 

**Register Type: READ/WRITE Register Address: 08 (Decimal); 08 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|YG_OFFS_TC_L[7:0]]|Bits 7 to 0 of the 10-bit offset of Y gyroscope (2’s complement)|



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_**ICG-20660**_ 

- **12.6 REGISTER 10 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER Register Name: ZG_OFFS_TC_H Register Type: READ/WRITE Register Address: 10 (Decimal); 0A (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:2]**|-|Reserved|
|**[1:0]**|ZG_OFFS_TC_H[9:8]|Bits 9 and 8 of the 10-bit offset of Z gyroscope (2’s complement)|



- **12.7 REGISTER 11 – GYROSCOPE OFFSET TEMPERATURE COMPENSATION (TC) REGISTER** 

**Register Name: ZG_OFFS_TC_L** 

**Register Type: READ/WRITE Register Address: 11 (Decimal); 0B (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|ZG_OFFS_TC_L[7:0]]|Bits 7 to 0 of the 10-bit offset of Z gyroscope (2’s complement)|



- **12.8 REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS** 

**Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL Type: READ/WRITE** 

**Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)** 

|**REGISTER**|**BITS**|**NAME**|**FUNCTION**|
|---|---|---|---|
|SELF_TEST_X_ACCEL|[7:0]|XA_ST_DATA[7:0]|The value in this register indicates the self-test output generated<br>during manufacturing tests.  This value is to be used to check<br>against subsequent self-test outputs performed by the end user.|
|SELF_TEST_Y_ACCEL|[7:0]|YA_ST_DATA[7:0]|The value in this register indicates the self-test output generated<br>during manufacturing tests.  This value is to be used to check<br>against subsequent self-test outputs performed by the end user.|
|SELF_TEST_Z_ACCEL|[7:0]|ZA_ST_DATA[7:0]|The value in this register indicates the self-test output generated<br>during manufacturing tests.  This value is to be used to check<br>against subsequent self-test outputs performed by the end user.|



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_**ICG-20660**_ 

The equation to convert self-test codes in OTP to factory self-test measurement is: 

_ST_  OTP_  (2620 / 2 _FS_ ) *.101( _ST_  code_  1) (lsb) 

where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the SelfTest value (ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation: 

log( _ST_  FAC_ /(2620 / 2 _FS_ )) _ST_  code_  _round_ ( )  1 log(.101) 

## **12.9 REGISTERS 19 – GYRO OFFSET ADJUSTMENT REGISTER** 

**Register Name: XG_OFFS_USRH Register Type: READ/WRITE Register Address: 19 (Decimal); 13 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|X_OFFS_USR[15:8]|Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement).  This register is<br>used to remove DC bias from the sensor output.  The value in this register is<br>added to the gyroscope sensor value before going into the sensor register.|



## **12.10 REGISTERS 20 – GYRO OFFSET ADJUSTMENT REGISTER** 

**Register Name: XG_OFFS_USRL Register Type: READ/WRITE Register Address: 20 (Decimal); 14 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|X_OFFS_USR[7:0]|Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement).  This register is<br>used to remove DC bias from the sensor output.  The value in this register is<br>added to the gyroscope sensor value before going into the sensor register.|



## **12.11 REGISTERS 21 – GYRO OFFSET ADJUSTMENT REGISTER** 

**Register Name: YG_OFFS_USRH Register Type: READ/WRITE Register Address: 21 (Decimal); 15 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|Y_OFFS_USR[15:8]|Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement).  This register is<br>used to remove DC bias from the sensor output.  The value in this register is<br>added to the gyroscope sensor value before going into the sensor register.|



## **12.12 REGISTERS 22 – GYRO OFFSET ADJUSTMENT REGISTER** 

**Register Name: YG_OFFS_USRL Register Type: READ/WRITE Register Address: 22 (Decimal); 16 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|Y_OFFS_USR[7:0]|Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement).  This register is<br>used to remove DC bias from the sensor output.  The value in this register is<br>added to the gyroscope sensor value before going into the sensor register.|



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_**ICG-20660**_ 

## **12.13 REGISTERS 23 – GYRO OFFSET ADJUSTMENT REGISTER** 

**Register Name: ZG_OFFS_USRH Register Type: READ/WRITE Register Address: 23 (Decimal); 17 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|Z_OFFS_USR[15:8]|Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement). This register is<br>used to remove DC bias from the sensor output. The value in this register is<br>added to the gyroscope sensor value before going into the sensor register.|



## **12.14 REGISTER 24 – GYRO OFFSET ADJUSTMENT REGISTER** 

**Register Name: ZG_OFFS_USRL Register Type: READ/WRITE Register Address: 24 (Decimal); 18 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|Z_OFFS_USR[7:0]|Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s complement). This register is<br>used to remove DC bias from the sensor output. The value in this register is<br>added to the gyroscope sensor value before going into the sensor register.|



## **12.15 REGISTER 25 – SAMPLE RATE DIVIDER** 

**Register Name: SMPLRT_DIV Register Type: READ/WRITE Register Address: 25 (Decimal); 19 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|[7:0]|SMPLRT_DIV[7:0]|Divides the internal sample rate (see register CONFIG) to generate the sample rate that<br>controls sensor data output rate, FIFO sample rate.  NOTE: This register is only effective<br>when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7).<br>This is the update rate of the sensor register:<br>SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)<br>Where INTERNAL_SAMPLE_RATE = 1 kHz|



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_**ICG-20660**_ 

## **12.16 REGISTER 26 – CONFIGURATION** 

**Register Name: CONFIG Register Type: READ/WRITE Register Address: 26 (Decimal); 1A (Hex)** 

|**BIT**<br>~~a~~<br>~~a~~|**NAME**<br>~~es~~<br>~~es~~|**FUNCTION**|
|---|---|---|
|[7]<br>~~a~~<br>~~a~~|-<br>~~es~~<br>~~es~~|Reserved.|
|[6]<br>~~a~~|FIFO_MODE<br>~~es~~|When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.<br>When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO, replacing<br>the oldest data.|
|[5:3]|EXT_SYNC_SET[2:0]|Enables the FSYNC pin data to be sampled.<br>**EXT_SYNC_SET**<br>**FSYNC bit location**<br>0<br>function disabled<br>1<br>TEMP_OUT_L[0]<br>2<br>GYRO_XOUT_L[0]<br>3<br>GYRO_YOUT_L[0]<br>4<br>GYRO_ZOUT_L[0]<br>5<br>ACCEL_XOUT_L[0]<br>6<br>ACCEL_YOUT_L[0]<br>7<br>ACCEL_ZOUT_L[0]<br>FSYNC will be latched to capture short strobes.  This will be done such that if FSYNC toggles, the<br>latched value toggles, but won’t toggle again until the new latched value is captured by the<br>sample rate strobe.|
|[2:0]|DLPF_CFG[2:0]|For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.<br>See the table below.|



The DLPF is configured by _DLPF_CFG,_ when _FCHOICE_B_ [1:0] = 2b’00. The gyroscope and temperature sensor are filtered according to the value of _DLPF_CFG_ and _FCHOICE_B_ as shown in the table below. 

|FCHOICE_B|FCHOICE_B|DLPF_CFG<br>~~nn~~|Gyroscope|Gyroscope|Gyroscope|Gyroscope|Temperature<br>Sensor|
|---|---|---|---|---|---|---|---|
|<1><br>~~ee~~|<0><br>~~nn~~||3-dB BW<br>(Hz)<br>~~nD~~|Noise BW<br>(Hz)<br>~~I~~|Rate<br>(kHz)|Delay<br>(ms)|3-dB BW (Hz)|
|X<br>~~ee~~<br>~~ee Rs~~|1<br>~~nn~~<br>~~Rs es~~|X<br>~~nn~~<br>~~es~~|8173<br>~~nD~~<br>~~I~~|8595.1<br>~~I~~<br>~~I~~|32<br>~~I~~|0.064<br>~~I~~|4000|
|1<br>~~ee~~<br>~~ee Rs~~<br>~~es~~|0<br>~~nn~~<br>~~Rs es~~<br>~~es~~|X<br>~~nn~~<br>~~es~~<br>~~es~~|3281<br>~~nD ~~<br>~~I~~<br>~~nD~~|3451.0<br> ~~I~~<br>~~I~~<br>~~I~~|32<br>~~I~~|0.11<br>~~I~~|4000|
|0<br>~~ee Rs~~<br>~~es~~<br>~~es~~|0<br>~~Rs es~~<br>~~es~~<br>~~es~~|0<br>~~es ~~<br>~~es~~<br>~~es~~|250<br> ~~I ~~<br>~~nD~~<br>~~I~~|306.6<br> ~~I~~<br>~~I~~<br>~~I~~|8<br>~~I ~~<br>~~I~~|0.97<br> ~~I~~|4000|
|0<br>~~es~~<br>~~es~~<br>~~ee~~|0<br>~~es~~<br>~~es~~<br>~~ey~~|1<br>~~es~~<br>~~es~~<br>~~ey~~|176<br>~~nD ~~<br>~~I~~<br>~~nN I~~|177.0<br> ~~I~~<br>~~I~~<br>~~I~~|1<br>~~I~~|2.9|188|
|0<br>~~es~~<br>~~ee~~<br>~~a~~|0<br>~~es~~<br>~~ey~~<br>~~nD~~|2<br>~~es ~~<br>~~ey~~<br>~~nD~~|92<br> ~~I ~~<br>~~nN I~~<br>~~I~~|108.6<br> ~~I~~<br>~~I~~|1<br>~~I~~|3.9|98|
|0<br>~~ee~~<br>~~a~~|0<br>~~ey~~<br>~~nD~~|7<br>~~ey ~~<br>~~nD~~|3281<br> ~~nN I~~<br>~~I~~|3451.0<br>~~I~~|8|0.17|4000|



Page 43 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **12.17 REGISTER 27 – GYROSCOPE CONFIGURATION** 

**Register Name: GYRO_CONFIG Register Type: READ/WRITE Register Address: 27 (Decimal); 1B (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|XG_ST|X Gyro self-test|
|**[6]**|YG_ST|Y Gyro self-test|
|**[5]**|ZG_ST|Z Gyro self-test|
|**[4:3]**|FS_SEL[1:0]|Gyro Full Scale Select:<br>00 = ±125 dps<br>01 = ±250 dps<br>10 = ±500 dps|
|**[2]**|-|Reserved|
|**[1:0]**|FCHOICE_B[1:0]|Used to bypass DLPF as shown in table 1 above.|



## **12.18 REGISTER 28 – ACCELEROMETER CONFIGURATION** 

**Register Name: ACCEL_CONFIG Register Type: READ/WRITE Register Address: 28 (Decimal); 1C (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|XA_ST|X Accel self-test|
|**[6]**|YA_ST|Y Accel self-test|
|**[5]**|ZA_ST|Z Accel self-test|
|**[4:3]**|ACCEL_FS_SEL[1:0]|Accel Full Scale Select:<br>±2g (00), ±4g (01), ±8g (10), ±16g (11)|
|**[2:0]**|-|Reserved|



Page 44 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **12.19 REGISTER 29 – ACCELEROMETER CONFIGURATION 2** 

**Register Name: ACCEL_CONFIG2 Register Type: READ/WRITE Register Address: 29 (Decimal); 1D (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:6]**|FIFO_SIZE[1:0]|Specifies FIFO size according to the following:<br>0 = 512 Bytes|
|**[5:4]**|DEC2_CFG[1:0]|Averaging filter settings for Low Power Accelerometer mode:<br>0 = Average 4 samples<br>1 = Average 8 samples<br>2 = Average 16 samples<br>3 = Average 32 samples|
|**[3]**|ACCEL_FCHOICE_B|Used to bypass DLPF as shown in the table below.|
|**[2:0]**|A_DLPF_CFG|Accelerometer low pass filter setting as shown in table 2 below.|



**Accelerometer Data Rates and Bandwidths (Low-Noise Mode)** 

|ACCEL_FCHOICE_B<br>~~a~~<br>~~pO~~|A_DLPF_CFG<br>~~ee~~|Accelerometer<br>~~ee~~|Accelerometer<br>~~ee~~|Accelerometer<br>~~ee~~|
|---|---|---|---|---|
|||3-dB BW<br>(Hz)<br>~~ee~~|Noise BW<br>(Hz)<br>~~ee~~|Rate<br>(kHz)<br>~~ee~~|
|1<br>~~a ~~<br>~~pO~~|X<br> ~~ee~~|1046.0<br>~~ee~~|1100.0<br>~~ee~~|4<br>~~ee~~|
|0<br>~~pO~~<br>~~po~~<br>~~pO~~|0<br>~~po~~|218.1<br>~~po~~|235.0<br>~~po~~|1<br>~~po~~|
|0<br>~~pO~~|1|218.1|235.0|1|
|0<br>~~pO~~<br>~~po~~<br>~~pO~~|2<br>~~po~~|99.0<br>~~po~~|121.3<br>~~po~~|1<br>~~po~~|
|0<br>~~po~~<br>~~pO~~|3<br>~~po~~|44.8<br>~~po~~|61.5<br>~~po~~|1<br>~~po~~|
|0<br>~~pO~~<br>~~pO~~<br>~~pO~~|4<br>~~pO~~|21.2<br>~~pO~~|31.0<br>~~pO~~|1<br>~~pO~~|
|0<br>~~pO~~<br>~~pO~~|5|10.2|15.5|1|
|0<br>~~pO~~<br>~~pO~~|6|5.1|7.8|1|
|0<br>~~pO~~<br>~~po~~|7<br>~~po~~|420.0<br>~~po~~|441.6<br>~~po~~|1<br>~~po~~|



The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz): 

3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K 

The following table lists the approximate accelerometer filter bandwidths available in the low-power mode of operation for some example ODRs. 

In the low-power mode of operation, the accelerometer is duty-cycled. The following table shows some example configurations for accelerometer low power mode. 

Page 45 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **Accelerometer Data Rates and Bandwidths (Low-Power Mode)** 

|~~a~~|~~a~~|~~rt~~|~~ns GR~~|~~GR~~|||
|---|---|---|---|---|---|---|
|ACCEL_FCHOICE_B<br>~~a~~<br>~~a~~||1<br>~~rt~~<br>~~tn~~|0<br>~~ns GR~~<br>~~ns~~|0<br>~~GR~~|0|0|
|A_DLPF_CFG<br>~~a~~<br>~~a~~<br>~~a~~||x<br>~~rt~~<br>~~tn~~<br>~~tn~~|7<br>~~ns GR~~<br>~~ns~~<br>~~ns~~|7<br>~~GR~~|7|7|
|DEC2_CFG<br>~~a~~<br>~~a~~||x<br>~~tn~~<br>~~tn~~|0<br>~~ns~~<br>~~ns~~<br>~~ns~~|1|2|3|
|Averages<br>~~a~~<br>~~tn~~||1x<br>~~tn~~<br>~~tn~~<br>~~I~~|4x<br>~~ns~~<br>~~tn~~<br>~~ns~~<br>~~I~~|8x<br>~~tn~~|16x<br>~~tn~~|32x<br>~~tn~~|
|Ton(ms)<br>~~ny~~||1.084<br>~~ny~~<br>~~I~~|1.84<br>~~ns~~<br>~~ny~~<br>~~I~~|2.84<br>~~ny~~<br>~~Ge~~|4.84<br>~~ny~~|8.84<br>~~ny~~|
|Noise BW(Hz)<br>~~ts~~||1100.0<br>~~I~~<br>~~ts~~|441.6<br>~~I~~<br>~~ts~~|235.4<br>~~ts~~<br>~~Ge~~|121.3<br>~~ts~~|61.5<br>~~ts~~|
|3-dB BW(Hz)<br>~~ns~~<br>~~es~~||1046.0<br>~~ns~~|420.0<br>~~ns~~|218.0<br>~~Ge~~<br>~~ns~~|110.0<br>~~ns~~|55.3<br>~~ns~~|
|SMPLRT_DIV<br>~~es~~<br>~~es~~|ODR(Hz)|~~ts~~|||||
|255<br>~~es~~<br>~~es~~<br>~~es~~|3.9<br>~~rs~~|Valid<br>~~ts~~<br>~~ns~~|Valid<br>~~ts~~<br>~~(UU~~|Valid<br>~~(UU~~|Valid|Valid|
|127<br>~~es~~<br>~~es~~<br>~~es~~|7.8<br>~~rs~~<br>~~rt~~|Valid<br>~~ts~~<br>~~ns~~<br>~~es~~|Valid<br>~~ts~~<br>~~(UU~~<br>~~es~~|Valid<br>~~(UU~~|Valid|Valid|
|99<br>~~es~~<br>~~es~~<br>~~es~~|10.0<br>~~rs~~<br>~~rt~~|Valid<br>~~ns~~<br>~~es~~<br>~~ns~~|Valid<br>~~(UU~~<br>~~es~~<br>~~ns~~|Valid<br>~~(UU~~|Valid|Valid|
|63<br>~~es~~<br>~~es~~<br>~~es~~|15.6<br>~~rt~~<br>~~es~~|Valid<br>~~es~~<br>~~ns~~<br>~~es~~|Valid<br>~~es~~<br>~~ns~~<br>~~Gs~~|Valid|Valid|Valid|
|31<br>~~es~~<br>~~es~~<br>~~a~~|31.3<br>~~es~~<br>~~re~~|Valid<br>~~ns~~<br>~~es~~<br>~~ss~~|Valid<br>~~ns~~<br>~~Gs~~<br>~~ss~~|Valid|Valid|Valid|
|19<br>~~es~~<br>~~a~~<br>~~a~~|50.0<br>~~es ~~<br>~~re~~<br>~~re~~|Valid<br> ~~es~~<br>~~ss~~<br>~~ss~~|Valid<br>~~Gs~~<br>~~ss~~<br>~~ss~~|Valid|Valid|Valid|
|15<br>~~a~~<br>~~a~~<br>~~es~~|62.5<br>~~re ~~<br>~~re~~<br>~~ns~~|Valid<br> ~~ss~~<br>~~ss~~<br>~~ns~~|Valid<br>~~ss~~<br>~~ss~~<br>~~ns~~|Valid<br>~~ns~~|Valid<br>~~ns~~|Valid<br>~~ns~~|
|9<br>~~a~~<br>~~es~~<br>~~es~~|100.0<br>~~re ~~<br>~~ns~~|Valid<br> ~~ss~~<br>~~ns~~|Valid<br>~~ss~~<br>~~ns~~|Valid<br>~~ns~~|Valid<br>~~ns~~|Valid<br>~~ns~~|
|7<br>~~es~~<br>~~es~~<br>~~es~~|125.0<br>~~ns~~<br>~~rs~~|Valid<br>~~ns~~<br>~~rn~~|Valid<br>~~ns~~|Valid<br>~~ns~~|Valid<br>~~ns~~|N/A<br>~~ns~~|
|4<br>~~es~~<br>~~es~~|200.0<br>~~rs~~<br>~~ee~~|Valid<br>~~rn~~<br>~~ee~~|Valid|Valid|Valid||
|3<br>~~es~~<br>~~es~~|250.0<br>~~rs ~~<br>~~es~~<br>~~ee~~<br>~~ee~~|Valid<br> ~~rn~~<br>~~es~~<br>~~ee~~|Valid<br>~~es~~|Valid<br>~~es~~|N/A||
|1<br>~~es~~<br>~~es~~|500.0<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|Valid<br>~~es~~<br>~~ee~~<br>~~es~~|Valid<br>~~es~~<br>~~es~~|N/A<br>~~es~~|||



## **12.20 REGISTER 30 – LOW POWER MODE CONFIGURATION** 

**Register Name: LP_MODE_CFG Register Type: READ/WRITE Register Address: 30 (Decimal); 1E (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:4]**|-|Reserved|
|**[3:0]**|LPOSC_CLKSEL|Sets the frequency of waking up the chip to take a sample of accel data – the<br>low power accel Output Data Rate<br>**LPOSC_CLKSEL**<br>**Output Frequency (Hz)**<br>0<br>0.24<br>1<br>0.49<br>2<br>0.98<br>3<br>1.95<br>4<br>3.91<br>5<br>7.81<br>6<br>15.63<br>7<br>31.25<br>8<br>62.50<br>9<br>125<br>10<br>250<br>11<br>500<br>12-15<br>Reserved|



Page 46 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **12.21 REGISTER 31 – WAKE-ON MOTION THRESHOLD (ACCELEROMETER)** 

**Register Name: ACCEL_WOM_THR Register Type: READ/WRITE Register Address: 31 (Decimal); 1F (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|WOM_THR[7:0]|This register holds the threshold value for the Wake on Motion Interrupt for accelerometer.|



## **12.22 REGISTER 35 – FIFO ENABLE** 

**Register Name: FIFO_EN Register Type: READ/WRITE Register Address: 35 (Decimal); 23 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|TEMP_FIFO_EN|1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate; If enabled,<br>buffering of data occurs even if data path is in standby.<br>0 – Function is disabled.|
|**[6]**|XG_FIFO_EN|1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate; If enabled,<br>buffering of data occurs even if data path is in standby.<br>0 – Function is disabled.|
|**[5]**|YG_FIFO_EN|1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate; If enabled,<br>buffering of data occurs even if data path is in standby.<br>0 – Function is disabled.<br>Note: Enabling any one of the bits corresponding to the Gyros or Temp data paths, data is<br>buffered into the FIFO even though that datapath is not enabled.|
|**[4]**|ZG_FIFO_EN|1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate; If enabled,<br>buffering of data occurs even if data path is in standby.<br>0 – Function is disabled.|
|**[3]**|ACCEL_FIFO_EN|1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H,<br>and ACCEL_ZOUT_L to the FIFO at the sample rate.<br>0 – Function is disabled.|
|**[2:0]**|-|Reserved.|



## **12.23 REGISTER 54 – FSYNC INTERRUPT STATUS** 

**Register Name: FSYNC_INT Register Type: READ to CLEAR Register Address: 54 (Decimal); 36 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|FSYNC_INT|This bit automatically sets to 1 when a FSYNC interrupt has been generated.  The bit<br>clears to 0 after the register has been read.|



Page 47 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

**12.24 REGISTER 55 – INT PIN / BYPASS ENABLE CONFIGURATION Register Name: INT_PIN_CFG Register Type: READ/WRITE Register Address: 55 (Decimal); 37 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|INT_LEVEL|1 – The logic level for INT pin is active low.<br>0 – The logic level for INT pin is active high.|
|**[6]**|INT_OPEN|1 – INT pin is configured as open drain.<br>0 – INT pin is configured as push-pull.|
|**[5]**|LATCH_INT_EN|1 – INT pin level held until interrupt status is cleared.<br>0 – INT pin indicates interrupt pulse’s width is 50us.|
|**[4]**|INT_RD_CLEAR|1 – Interrupt status is cleared if any read operation is performed.<br>0 – Interrupt status is cleared only by reading INT_STATUS register|
|**[3]**|FSYNC_INT_LEVEL|1 – The logic level for the FSYNC pin as an interrupt is active low.<br>0 – The logic level for the FSYNC pin as an interrupt is active high.|
|**[2]**|FSYNC_INT_MODE_EN|When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions<br>to the level specified by F_SYNC_INT_LEVEL_. When this bit is equal to 0, the FSYNC pin<br>is disabled from causingan interrupt.|
|**[1]**|-|Reserved.|
|**[0]**|-|Reserved.|



## **12.25 REGISTER 56 – INTERRUPT ENABLE** 

**Register Name: INT_ENABLE Register Type: READ/WRITE Register Address: 56 (Decimal); 38 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:5]**|WOM_EN|‘111’  – Enable WoM interrupt<br>‘000’  – Disable WoM interrupt – This is the default setting.|
|**[4]**|FIFO_OFLOW_EN|1 – Enables a FIFO buffer overflow to generate an interrupt.<br>0 – Function is disabled.|
|**[3]**|-|Reserved.|
|**[2]**|-|Reserved.|
|**[1]**|-|Reserved.|
|**[0]**|DATA_RDY_INT_EN|Data ready interrupt enable.|



Page 48 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **12.26 REGISTER 58 – INTERRUPT STATUS** 

**Register Name: INT_STATUS Register Type: READ to CLEAR Register Address: 58 (Decimal); 3A (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|WOM_X_INT|X-axis accelerometer WoM interrupt status. Cleared on Read.|
|**[6]**|WOM_Y_INT|Y-axis accelerometer WoM interrupt status. Cleared on Read.|
|**[5]**|WOM_Z_INT|Z-axis accelerometer WoM interrupt status. Cleared on Read.|
|**[4]**|FIFO_OFLOW_INT|This bit automatically sets to 1 when a FIFO buffer overflow has been generated.  The bit<br>clears to 0 after the register has been read.|
|**[3]**|-|Reserved.|
|**[2]**|-|Reserved.|
|**[1]**|-|Reserved.|
|**[0]**|DATA_RDY_INT|This bit automatically sets to 1 when a Data Ready interrupt is generated.  The bit clears<br>to 0 after the register has been read.|



## **12.27 REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS** 

**Register Name: ACCEL_XOUT_H Register Type: READ only Register Address: 59 (Decimal); 3B (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|ACCEL_XOUT_H[15:8]|High byte of accelerometer x-axis data.|



**Register Name: ACCEL_XOUT_L Register Type: READ only Register Address: 60 (Decimal); 3C (Hex)** 

||**BIT**|**NAME**|**FUNCTION**|
|---|---|---|---|
||**[7:0]**|ACCEL_XOUT_L[7:0]|Low byte of accelerometer x-axis data.|
|**Register Name: ACCEL_YOUT_H**||||
|**Register Type: READ only**||||
|**Register Address: 61 (Decimal); 3D (Hex)**||||



||**BIT**|**NAME**||**FUNCTION**|
|---|---|---|---|---|
||**[7:0]**|ACCEL_YOUT_H[15:8]||High byte of accelerometer y-axis data.|
|**Register Name: ACCEL_YOUT_L**|||||
|**Register Type: READ only**|||||
|**Register Address: 62 (Decimal); 3E (Hex)**||||**Register Address: 62 (Decimal); 3E (Hex)**|



|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|ACCEL_YOUT_L[7:0]|Low byte of accelerometer y-axis data.|



Page 49 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

**Register Name: ACCEL_ZOUT_H Register Type: READ only Register Address: 63 (Decimal); 3F (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|ACCEL_ZOUT_H[15:8]|High byte of accelerometer z-axis data.|



**Register Name: ACCEL_ZOUT_L Register Type: READ only Register Address: 64 (Decimal); 40 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|ACCEL_ZOUT_L[7:0]|Low byte of accelerometer z-axis data.|



## **12.28 REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT** 

**Register Name: TEMP_OUT_H Register Type: READ only Register Address: 65 (Decimal); 41 (Hex)** 

|**BIT**<br>**NAME**|**FUNCTION**|
|---|---|
|**[7:0]**<br>TEMP_OUT[15:8]|High byte of the temperature sensor output.|
|**Register Name: TEMP_OUT_L**||
|**Register Type: READ only**||
|**Register Address: 66 (Decimal); 42 (Hex)**<br>**BIT**<br>**NAME**<br>**[7:0]**<br>TEMP_OUT[7:0]<br>~~1~~|**Register Address: 66 (Decimal); 42 (Hex)**<br>**FUNCTION**<br>Low byte of the temperature sensor output.<br>**TEMP_degC**<br>= ((TEMP_OUT –<br>RoomTemp_Offset)/Temp_Sensitivity) +<br>25degC<br>~~a~~|
|**12.29 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS**||
|**Register Name: GYRO_XOUT_H**||
|**Register Type: READ only**||
|**Register Address: 67 (Decimal); 43 (Hex)**|**Register Address: 67 (Decimal); 43 (Hex)**|
|**BIT**<br>**NAME**|**FUNCTION**|
|**[7:0]**<br>GYRO_XOUT[15:8]|High byte of the X-Axis gyroscope output.|



**Register Name: TEMP_OUT_L Register Type: READ only Register Address: 66 (Decimal); 42 (Hex)** 

## **12.29 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS** 

**Register Name: GYRO_XOUT_H Register Type: READ only Register Address: 67 (Decimal); 43 (Hex)** 

**Register Name: GYRO_XOUT_L Register Type: READ only Register Address: 68 (Decimal); 44 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|GYRO_XOUT[7:0]|Low byte of the X-Axis gyroscope output.<br>**GYRO_XOUT =**<br>Gyro_Sensitivity * X_angular_rate<br>Nominal<br>Conditions<br>FS_SEL = 0<br>Gyro_Sensitivity = 131 LSB/(º/s)|



Page 50 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

**Register Name: GYRO_YOUT_H Register Type: READ only Register Address: 69 (Decimal); 45 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|GYRO_YOUT[15:8]|High byte of the Y-Axis gyroscope output.|



**Register Name: GYRO_YOUT_L Register Type: READ only Register Address: 70 (Decimal); 46 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|GYRO_YOUT[7:0]|Low byte of the Y-Axis gyroscope output.<br>**GYRO_YOUT =**<br>Gyro_Sensitivity * Y_angular_rate<br>Nominal<br>Conditions<br>FS_SEL = 0<br>Gyro_Sensitivity = 131 LSB/(º/s)|



**Register Name: GYRO_ZOUT_H Register Type: READ only Register Address: 71 (Decimal); 47 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|GYRO_ZOUT[15:8]|High byte of the Z-Axis gyroscope output|



**Register Name: GYRO_ZOUT_L Register Type: READ only Register Address: 72 (Decimal); 48 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|GYRO_ZOUT[7:0]|Low byte of the Z-Axis gyroscope output.<br>**GYRO_ZOUT =**<br>Gyro_Sensitivity * Z_angular_rate<br>Nominal<br>Conditions<br>FS_SEL = 0<br>Gyro_Sensitivity = 131 LSB/(º/s)|



## **12.30 REGISTER 104 – SIGNAL PATH RESET** 

**Register Name: SIGNAL_PATH_RESET Register Type: READ/WRITE Register Address: 104 (Decimal); 68 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:2]**|-|Reserved.|
|**[1]**|ACCEL_RST|Reset accel digital signal path.  Note:  Sensor registers are not cleared.<br>Use SIG_COND_RST to clear sensor registers.|
|**[0]**|TEMP_RST|Reset temp digital signal path.  Note:  Sensor registers are not cleared.<br>Use SIG_COND_RST to clear sensor registers.|



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_**ICG-20660**_ 

## **12.31 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL** 

**Register Name: ACCEL_INTEL_CTRL Register Type: READ/WRITE Register Address: 105 (Decimal); 69 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|ACCEL_INTEL_EN|This bit enables the Wake-on-Motion detection logic.|
|**[6]**|ACCEL_INTEL_MODE|0 – Do not use.<br>1 – Compare the current sample with the previous sample.|
|**[5:1]**|-|Reserved|
|**[0]**|WOM_TH_MODE|0 – Set WoM interrupt on the OR of all enabled accelerometer thresholds.<br>1 – Set WoM interrupt on the AND of all enabled accelerometer thresholds.<br>Default setting is 0.|



## **12.32 REGISTER 106 – USER CONTROL** 

**Register Name: USER_CTRL Register Type: READ/WRITE Register Address: 106 (Decimal); 6A (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|-|Reserved.|
|**[6]**|FIFO_EN|1 – Enable FIFO operation mode.<br>0 – Disable FIFO access from serial interface.  To disable FIFO writes by DMA, use FIFO_EN<br>register.  -|
|**[5]**|-|Reserved|
|**[4]**|I2C_IF_DIS|1 – Reset I2C Slave module and put the serial interface in SPI mode only.  This bit auto clears<br>after one clock cycle of the internal 20 MHz clock.|
|**[3]**|-|Reserved.|
|**[2]**|FIFO_RST|1 – Reset FIFO module. Reset is asynchronous.  This bit auto clears after one clock cycle of<br>the internal 20 MHz clock.|
|**[1]**|-|Reserved.|
|**[0]**|SIG_COND_RST|1 – Reset all gyro digital signal path, accel digital signal path, and temp digital signal path.<br>This bit also clears all the sensor registers.|



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_**ICG-20660**_ 

## **12.33 REGISTER 107 – POWER MANAGEMENT 1** 

**Register Name: PWR_MGMT_1 Register Type: READ/WRITE Register Address: 107 (Decimal); 6B (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|DEVICE_RESET|1 – Reset the internal registers and restores the default settings.  The bit automatically clears<br>to 0 once the reset is done.|
|**[6]**|SLEEP|When set to 1, the chip is set to sleep mode.|
|**[5]**|CYCLE|When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep<br>and taking a single accelerometer sample at a rate determined by SMPLRT_DIV.<br>**Note:**When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled,<br>the chip will wake up at the rate determined by the respective registers above, but will not take any<br>samples.|
|**[4]**|GYRO_STANDBY|When set, the gyro drive and pll circuitry are enabled, but the sense paths are disabled.  This<br>is a low power mode that allows quick enabling of the gyros.|
|**[3]**|TEMP_DIS|When set to 1, this bit disables the temperature sensor.|
|**[2:0]**|CLKSEL[2:0]|**Code**<br>**Clock Source**<br>0<br>Internal 20 MHz oscillator<br>1<br>Auto selects the best available clock source – PLL if ready, else use the Internal<br>oscillator<br>2<br>Auto selects the best available clock source – PLL if ready, else use the Internal<br>oscillator<br>3<br>Auto selects the best available clock source – PLL if ready, else use the Internal<br>oscillator<br>4<br>Auto selects the best available clock source – PLL if ready, else use the Internal<br>oscillator<br>5<br>Auto selects the best available clock source – PLL if ready, else use the Internal<br>oscillator<br>6<br>Internal 20 MHz oscillator<br>7<br>Stops the clock and keeps timing generator in reset|



**Note:** The default value of CLKSEL[2:0] is 000.  It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance. 

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Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **12.34 REGISTER 108 – POWER MANAGEMENT 2** 

**Register Name: PWR_MGMT_2 Register Type: READ/WRITE Register Address: 108 (Decimal); 6C (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7]**|**[7]**|FIFO_LP_EN|
|**[6]**|-|Reserved.|
|||1 – X accelerometer is disabled.|
|**[5]**|STBY_XA||
|||0 – X accelerometer is on.|
|||1 – Y accelerometer is disabled.|
|**[4]**|STBY_YA||
|||0 – Y accelerometer is on.|
|||1 – Z accelerometer is disabled.|
|**[3]**|STBY_ZA||
|||0 – Z accelerometer is on.|
|||1 – X gyro is disabled.|
|**[2]**|STBY_XG||
|||0 – X gyro is on.|
|||1 – Y gyro is disabled.|
|**[1]**|STBY_YG||
|||0 – Y gyro is on.|
|||1 – Z gyro is disabled.|
|**[0]**|STBY_ZG||
|||0 – Z gyro is on.|



## **12.35 REGISTER 114 AND 115 – FIFO COUNT REGISTERS** 

**Register Name: FIFO_COUNTH Register Type: READ Only Register Address: 114 (Decimal); 72 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:5]**|-|Reserved.|
|**[4:0]**|FIFO_COUNT[12:8]|High Bits, count indicates the number of written bytes in the FIFO.<br>Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.|



**Register Name: FIFO_COUNTL Register Type: READ Only Register Address: 115 (Decimal); 73 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|FIFO_COUNT[7:0]|Low Bits, count indicates the number of written bytes in the FIFO.  NOTE:  Must read<br>FIFO_COUNTH to latch new data for both FIFO_COUNTH and FIFO_COUNTL.|



## **12.36 REGISTER 116 – FIFO READ WRITE** 

**Register Name: FIFO_R_W Register Type: READ/WRITE Register Address: 116 (Decimal); 74 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|FIFO_DATA[7:0]|Read/Write command provides Read or Write operation for the FIFO.|



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Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## **Description:** 

This register is used to read and write data from the FIFO buffer. 

Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are enabled, the contents of registers 59 through 72 will be written in order at the Sample Rate. 

The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when their corresponding FIFO enable flags are set to 1 in FIFO_EN (Register 35). 

If the FIFO buffer has overflowed, the status bit _FIFO_OFLOW_INT_ is automatically set to 1. This bit is located in INT_STATUS (Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO unless register 26 CONFIG, bit[6] FIFO_MODE = 1. 

If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data is available. Normal data is precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty. 

## **12.37 REGISTER 117 – WHO AM I** 

**Register Name: Register Type: READ only Register Address: 117 (Decimal); 75 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|WHO_AM_I|Register to indicate to user which device is being accessed.|



This register is used to verify the identity of the device. The contents of _WHO_AM_I_ is an 8-bit device ID. The default value of the register is 0x91. This is different from the I[2] C address of the device as seen on the slave I[2] C controller by the applications processor. The I[2] C address of the ICG-20660 is 0x68 or 0x69 depending upon the value driven on AD0 pin. 

## **12.38 REGISTERS 119, 120, 122, 123, 125, 126 ACCELEROMETER OFFSET REGISTERS** 

**Register Name: XA_OFFSET_H Register Type: READ/WRITE Register Address: 119 (Decimal); 77 (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|XA_OFFS[14:7]|Upper bits of the X accelerometer offset cancellation.  +/- 16g Offset cancellation in all Full<br>Scale modes, 15 bit 0.98-mg steps.|
|**Register Name: XA_OFFSET_L**||**Register Name: XA_OFFSET_L**|
|**Register Type: READ/WRITE**|||
|**Register Address: 120 (Decimal); 78 (Hex)**|||



|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:1]**|XA_OFFS[6:0]|Lower bits of the X accelerometer offset cancellation.  +/- 16g Offset cancellation in all Full<br>Scale modes, 15 bit 0.98-mg steps.|
|**[0]**|-|Reserved.|



|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|YA_OFFS[14:7]|Upper bits of the Y accelerometer offset cancellation.  +/- 16g Offset cancellation in all Full<br>Scale modes, 15 bit 0.98-mg steps.|



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_**ICG-20660**_ 

**Register Name: YA_OFFSET_L Register Type: READ/WRITE Register Address: 123 (Decimal); 7B (Hex)** 

|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:1]**|YA_OFFS[6:0]|Lower bits of the Y accelerometer offset cancellation.  +/- 16g Offset cancellation in all Full<br>Scale modes, 15 bit 0.98-mg steps.|
|**[0]**|-|Reserved.|



|**BIT**|**NAME**|**FUNCTION**|
|---|---|---|
|**[7:0]**|ZA_OFFS[14:7]|Upper bits of the Z accelerometer offset cancellation.  +/- 16g Offset cancellation in all Full<br>Scale modes, 15 bit 0.98-mg steps.|
|**Register Name: ZA_OFFSET_L**|||
|**Register Type: READ/WRITE**|||
|**Register Address: 126 (Decimal); 7E (Hex)**|||
|**BIT**|**NAME**|**FUNCTION**|
|**[7:1]**|ZA_OFFS[6:0]|Lower bits of the Z accelerometer offset cancellation.  +/- 16g Offset cancellation in all Full<br>Scale modes, 15 bit 0.98-mg steps.|
|**[0]**|-|Reserved.|



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Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

## _**13 REVISION HISTORY**_ 

|**Revision Date**|**Revision**|**Description**|
|---|---|---|
|05/27/2016|1.0|Initial Draft|
|09/20/2016|1.1|Removed preliminary, formatting updates|



Page 57 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016 

_**ICG-20660**_ 

This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights. 

Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment, transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment. 

©2016 InvenSense, Inc. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, Digital Motion Processor, AAR, and the InvenSense logo are trademarks of InvenSense, Inc. Other company and product names may be trademarks of the respective companies with which they are associated. 

©2016 InvenSense, Inc. All rights reserved. 

Page 58 of 58 

Document Number: DS-000135 Revision: 1.1 Rev Date: 09/20/2016
Updated at April 17, 2026
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