# Power MOSFET, N Channel, 80 V, 28 A, 0.023 ohm, TDSON, Surface Mount

![Product image](https://novapart.co/image/farnell:3577311/)

**URL**: https://novapart.co/products/IAUC28N08S5L230ATMA1/power-mosfet-n-channel-80-v-28-a-0023-ohm-tdson
**SKU**: IAUC28N08S5L230ATMA1
**Manufacturer**: INFINEON
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.3400
**Stock**: 1000+
**Lead Time**: 190 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | OptiMOS 5 |
| Qualification | AEC-Q101 |
| Power Dissipation | 38W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TDSON |
| Drain Source Voltage Vds | 80V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 28A |
| Drain Source On State Resistance | 0.023ohm |
| Gate Source Threshold Voltage Max | 1.6V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3577311/)

**IAUC28N08S5L230** 

**==> picture [470 x 231] intentionally omitted <==**

**----- Start of picture text -----**<br>
OptiMOS™-5 Power-Transistor<br>-—L> Product Summary<br>V DS 80 V<br>Features<br>R 23 mW<br>DS(on)<br>• OptiMOS™ - power MOSFET for automotive applications<br>I D 28 A<br>• N-channel - Enhancement mode - Logic Level ~ °- —ae<br>• MSL1 up to 260°C peak reflow PG-TDSON-8<br>• 175°C operating temperature<br>• Green product (RoHS compliant)<br>• 100% Avalanche tested<br>1<br>Quality Features<br>• Infineon Automotive Quality<br>1<br>**----- End of picture text -----**<br>


- Extended qualification beyond AEC Q101 

- Enhanced testing 

- Advanced adhesion against delamination 

- Complementary testing for board level reliability 

|™,<br>Advanced<br>adhesion|@ Robust|Enhanced<br>tested|
|---|---|---|
||||
|**Type**|**Package**|**Marking**|
||||
|IAUC28N08S5L230|PG-TDSON-8|5N08L230|



**Maximum ratings,** at _T_ j=25 °C, unless otherwise specified 

|**Maximum ratings,**at_T_j=25 °C, unless otherwise specified=25 °C, unless otherwise specified|j=25 °C, unless otherwise specified=25 °C, unless otherwise specified|j=25 °C, unless otherwise specified=25 °C, unless otherwise specified|||
|---|---|---|---|---|
|**Parameter**|**Symbol**|**Conditions**|**Value**|**Unit**|
|Continous drain current|_I_D|_T_C=25°C,_V_GS=10V|28|A|
|||_T_C=100 °C,<br>_V_GS=10 V1)|20||
|Pulsed drain current1)|_I_D,pulse|_T_C=25°C|112||
|Avalanche energy, single pulse1)|_E_AS|_I_D=14 A|28|mJ|
|Avalanche current, single pulse|_I AS_|_-_|14|A|
|Gate source voltage|_V_GS|-|±20|V|
|Power dissipation|_P_tot|_T_C=25 °C|38|W|
|Operating and storage temperature|_T_j,_T_stg|-|-55 ... +175|°C|
|IEC climatic category; DIN IEC 68-1|-|-|55/175/56||



Rev. 1.0 

page 1 

2019-10-04 

**Parameter Symbol Conditions Values Unit min. typ. max.** ~~ee ee~~ **Thermal characteristics[1)]** Thermal resistance, junction - case _R_ thJC - - - 3.9 K/W Thermal resistance, _R_ thJA - - 28.5 - junction - ambient[2)] ~~Teer~~ 

**Electrical characteristics,** at _T_ j=25 °C, unless otherwise specified 

|**Static characteristics**|||||||
|---|---|---|---|---|---|---|
|Drain-source breakdown voltage|_V_(BR)DSS|_V_GS=0 V,<br>_I_D=1 mA|80|-|-|V|
|Gate threshold voltage|_V_GS(th)|_V_DS=_V_GS,_I_D=11 µA|1.2|1.6|2.0||
|Zero gate voltage drain current|_I_DSS|_V_DS=80 V,_V_GS=0 V,<br>_T_j=25 °C|-|-|1|µA|
|||_V_DS=80 V,_V_GS=0 V,<br>_T_j=85 °C1)|-|-|100||
|Gate-source leakage current|_I_GSS|_V_GS=20 V,_V_DS=0 V|-|-|100|nA|
|Drain-source on-state resistance|R_DS(on)_|_V_GS=4.5 V,_I_D=14 A|-|21|28|mΩ|
|||_V_GS=10 V,_I_D=14 A|-|15|23||
|Gate resistance1)|_R_G|-|-|0.9|-|W|



|**Parameter**<br>~~ee ~~|**Parameter**<br>~~ee ~~|**Symbol**<br>**Conditions**<br> ~~ee~~|**Symbol**<br>**Conditions**<br> ~~ee~~|**min.**|**typ.**<br>**Values**|**max.**|**Unit**|
|---|---|---|---|---|---|---|---|
||**Dynamic characteristics1)**|||||||
||Input capacitance|_C_iss||-|667|867|pF|
||Output capacitance|_C_oss|_V_GS=0 V,_V_DS=40 V,<br>_f_=1 MHz|-|118|153||
||Reverse transfer capacitance|Crss||-|9.3|14||
||Turn-on delay time|_t_d(on)||-|2|-|ns|
||Rise time|_t_r|_V_DD=40 V,_V_GS=10 V,|-|1|-||
||Turn-off delay time|_t_d(off)|_I_D=28 A,_R_G=3.5W|-|6|-||
||Fall time|_t_f||-|4|-||
||**Gate Charge Characteristics1)**|||||||
||Gate to source charge|_Q_gs||-|2.1|2.7|nC|
||Gate to drain charge|_Q_gd|_V_DD=40 V,_I_D=14 A,|-|2.5|3.7||
||Gate charge total|_Q_g|_V_GS=0 to 10 V|-|11.6|15.1||
||Gate plateau voltage|_V_plateau||-|3.1|-|V|
||**Reverse Diode**|||||||
||Diode continous forward current1)|_I_S||-|-|28|A|
||||_T_C=25 °C|||||
||Diode pulse current1)|_I_S,pulse||-|-|70||
||Diode forward voltage|_V_SD|_V_GS=0 V,_I_F=14 A,<br>_T_j=25 °C|-|0.9|1.2|V|
||Reverse recovery time1)|_t_rr|_V_R=40 V,_I_F=28A,|-|30|-|ns|
||Reverse recovery charge1)|_Q_rr|d_i_F/d_t_=100 A/µs|-|22|-|nC|



1) The parameter is not subject to production test - verified by design/chracterization. 

2) Device on four layer 2s2p PCB defined in accordance with JEDEC standards (JESD51-5-7). PCB is vertical in still air. 

Rev. 1.0 

page 3 

2019-10-04 

## **1 Power dissipation** 

_P_ tot = f( _T_ C); _V_ GS ≥ 6 V 

## **2 Drain current** 

_I_ D = f( _T_ C); _V_ GS ≥ 6 V 

**==> picture [482 x 644] intentionally omitted <==**

**----- Start of picture text -----**<br>
45 30<br>40<br>25<br>35<br>30 20<br>25<br>15<br>20<br>15 10<br>10<br>5<br>5<br>0 0<br>0 50 100 150 200 0 50 100 150 200<br>T C [°C] T C [°C]<br>3 Safe operating area 4 Max. transient thermal impedance<br>I  D = f( V  DS);  T  C = 25 °C;  D  = 0 Z  thJC = f( t  p)<br>parameter:  t  p parameter:  D  = t  p/ T<br>1000 10 [1]<br>0.5<br>100 10 [0]<br>1 µs<br>0.1<br>ee<br>10 µs 0.05<br>100 µs<br>0.01<br>150 µs<br>10 10 [-1]<br>single pulse<br>1 At 10 [-2]<br>0.1 1 10 100 10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1       ] 10 [0]<br>V DS [V] t p [s]<br>Rev. 1.0 page 4 2019-10-04<br> [W]<br> [A]<br>P tot I D<br> [A]  [K/W]<br>I D<br>thJC<br>Z<br>**----- End of picture text -----**<br>


Rev. 1.0 

## **5 Typ. output characteristics** 

## **6 Typ. drain-source on-state resistance** 

**==> picture [457 x 654] intentionally omitted <==**

**----- Start of picture text -----**<br>
I  D = f( V  DS);  T  j = 25 °C R  DS(on) = ( I  D);  T  j = 25 °C<br>parameter:  V  GS parameter:  V  GS<br>90<br>10 V<br>120 80<br>7 V 3 V<br>3.5 V<br>100 70 4 V 4.5 V<br>60<br>80<br>4.5 V<br>50<br>60<br>4 V 40<br>40<br>30<br>3.5 V 7 V<br>20 20<br>3 V<br>10 V<br>0 fa 10 l<br>0 40 80 120<br>0 1 2 3 4 5 6 7<br>V DS [V] I D [A]<br>7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance<br>I  D = f( V  GS);  V  DS = 6V R  DS(on) = f( T  j);  I  D = 14 A;  V  GS = 10 V<br>parameter:  T  j<br>140 40<br>120 25 °C 35<br>-55 °C<br>100 30<br>175 °C<br>80 25<br>60 20<br>40 15<br>20 10<br>0 5<br>1.5 3 4.5 6 -55 -15 25 65 105 145<br>V GS [V] T j [°C]<br>]W<br> [m<br> [A]<br>I D<br>DS(on)<br>R<br>]<br>W<br> [m<br> [A]<br>I D<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


Rev. 1.0 

2019-10-04 

page 5 

**==> picture [475 x 715] intentionally omitted <==**

**----- Start of picture text -----**<br>
                       IAUC28N08S5L230<br>9 Typ. gate threshold voltage 10 Typ. capacitances<br>V  GS(th) = f( T  j);  V  GS =  V  DS C  = f( V  DS);  V  GS = 0 V;  f  = 1 MHz<br>parameter:  I  D<br>2.5 10 [3]<br>Ciss<br>2<br>10 [2]<br>110 µA<br>1.5 Coss<br>11 µA<br>1<br>10 [1]<br>Crss<br>0.5<br>N& 0<br>-60 -20 20 60 100 140 180 0 20 40 60 80<br>T j [°C] V DS [V]<br>11 Typical forward diode characteristicis 12 Typ. avalanche characteristics<br>IF = f(VSD) I  AS = f( t  AV)<br>parameter:  T  j parameter: Tj(start)<br>10 [3] 100<br>10 [2] 10<br>25 °C<br>175 °C 100 °C<br>25 °C 150 °C<br>10 [1] 1<br>10 [0] 0.1<br>0 0.2 0.4 0.6 0.8 1 1.2 1.4 1 10 100 1000<br>V SD [V] t AV [µs]<br> [V]<br> [pF]<br>GS(th) C<br>V<br> [A]  [A]<br>I F I AV<br>**----- End of picture text -----**<br>


Rev. 1.0 

page 6 

2019-10-04 

**IAUC28N08S5L230** 

**==> picture [470 x 671] intentionally omitted <==**

**----- Start of picture text -----**<br>
13 Typical avalanche energy 14 Drain-source breakdown voltage<br>E  AS = f( T  j) V  BR(DSS) = f( T  j);  I  D_typ = 1 mA<br>parameter:  I  D<br>120 87<br>86<br>100 3.5 A 85<br>84<br>80<br>83<br>82<br>60<br>81<br>7 A<br>80<br>40<br>79<br>14 A 78<br>20<br>77<br>0 : [\] e 76<br>25 75 125 175 -60 -20 20 60 100 140 180<br>T j [°C] T j [°C]<br>15 Typ. gate charge 16 Gate charge waveforms<br>V  GS = f( Q  gate);  I  D = 14 A pulsed<br>parameter:  V  DD<br>10<br>9 Un V GS<br>8 Vf Q g<br>7 16 V 4<br>64 V<br>40 V<br>6<br>5 Y<br>4<br>3<br>2<br>Q  gate<br>1<br>Q gs Q gd<br>[-<br>0<br>0 5 10<br>Q gate [nC]<br> [V]<br> [mJ]<br>AS BR(DSS)<br>E V<br> [V]<br>GS<br>V<br>**----- End of picture text -----**<br>


Rev. 1.0 

2019-10-04 

page 7 

## **PG-TDSON-8: Outline** 

## **Footprint** 

Dimensions in mm **Packaging** 

Rev. 1.0 

page 8 

2019-10-04 

**IAUC28N08S5L230** 

## **Published by Infineon Technologies AG 85579 Neubiberg, Germany** 

## **© Infineon Technologies AG 2019 All Rights Reserved.** 

## **Legal Disclaimer** 

The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. 

## **Information** 

For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). 

## **Warnings** 

Due to technical requirements, components may contain dangerous substances. 

For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 

Rev. 1.0 

page 9 

2019-10-04 



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- [Supplier page](https://es.farnell.com/infineon/iauc28n08s5l230atma1/mosfet-n-ch-80v-28a-tdson/dp/3577311)
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