# Power MOSFET, N Channel, 100 V, 75 A, 6700 µohm, TO-247, Through Hole ![Product image](https://novapart.co/image/farnell:2453451/) **URL**: https://novapart.co/products/HUF75652G3/power-mosfet-n-channel-100-v-75-a-6700-ohm-to-247 **SKU**: HUF75652G3 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €4.0100 **Stock**: 10+ ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:75A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.0067ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 515W | | Transistor Mounting | Through Hole | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-247 | | Drain Source Voltage Vds | 100V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 75A | | Drain Source On State Resistance | 6700µohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2453451/) ## MOSFET – Power, N-Channel, Ultrafet 100 V, 75 A, 8 m ~~:~~ ## HUF75652G3 ## **Features** - Ultra Low On−Resistance **www.onsemi.com** - ♦ rDS(ON) = 0.008 Q , VGS = 10 V - Simulation Models - ♦ Temperature Compensated PSPICE™ and SABER™ Electrical Models - ♦ Spice and SABER Thermal Impedance Models - ♦ www.onsemi.com - Peak Current vs Pulse Width Curve **==> picture [37 x 67] intentionally omitted <==** **----- Start of picture text -----**
D
G
S
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- UIS Rating Curve - This Device is Pb−Free, Halogen Free/BFR Free and is RoHS Compliant ## **Packing** **==> picture [50 x 17] intentionally omitted <==** **----- Start of picture text -----**
TO−247−3LD
CASE 340CK
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GATE
MARKING DIAGRAMS
2
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Figure 1.
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$Y&Z&3&K
75652G
DY Dp
$Y = ON Semiconductor Logo
&Z = Assembly Plant Code
&3 = Data Code (Year & Week)
&K = Lot
75652G = Specific Device Code
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## **ORDERING INFORMATION** |**Part Number**|**Package**|**Brand**| |---|---|---| |HUF75652G3|TO−247−3LD|75652G| Publication Order Number: **HUF75652G3/D** **1** © Semiconductor Components Industries, LLC, 2001 **March, 2020 − Rev. 3** ## **HUF75652G3** ## **ABSOLUTE MAXIMUM RATINGS** TC = 25 ° C unless otherwise specified |**ABSOLUTE MAXIMUM RATINGS**TC= 25°C unless|otherwise specified||| |---|---|---|---| |**Description**|**Symbol**|**Ratings**|**Units**| |Drain to Source Voltage (Note 1)|VDSS|100|V| |Drain to Gate Voltage (RGS= 20 k�) (Note 1)|VDGR|100|V| |Gate to Source Voltage|VGS|+20|V| |Drain Current
− Continuous (TC= 25°C, VGS= 10 V) (Figure 2)
−Continuous (TC= 100°C, VGS= 10 V) (Figure 2)
− Pulsed Drain Current|ID
ID
IDM|75
75
Figure 4|A
A| |Pulsed Avalanche Rating|UIS|Figures 6|| |Power Dissipation
− Derate Above 25°C|PD|515
3.44|W
W/°C| |Operating and Storage Temperature|TJ, TSTG|−55 to 175|°C| |Maximum Temperature for Soldering
− Leads at 0.063 in (1.6 mm) from Case for 10 s
− Package Body for 10 s, See Techbrief TB334|TL
Tpkg|300
260|°C
°C| Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. TJ = 25 ° C to 150 ° C. **www.onsemi.com** **2** **HUF75652G3** **ELECTRICAL SPECIFICATIONS** TC = 25 ° C unless otherwise noted |**SYMBOL**|**PARAMETER**|**TEST CONDITIONS**|**TEST CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**| |---|---|---|---|---|---|---|---| |**OFF STATE**|**SPECIFICATIONS**||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250�A, VGS= 0 V (Figure 11)||100|−|−|V| |IDSS|Zero Gate Voltage Drain Current|VDS= 95 V, VGS= 0 V||−|−|1|�A| |||VDS= 90 V, VGS= 0 V, TC= 150°C||−|−|250|�A| |IGSS|Gate to Source Leakage Current|VGS=±20 V||−|−|±100|nA| |**ON STATE SPECIFICATIONS**|||||||| |VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250�A (Figure 10)||2|−|4|V| |rDS(ON)|Drain to Source On Resistance|ID= 75 A, VGS= 10 V (Figure 9)||−|0.0067|0.008|�| |**THERMAL SPECIFICATIONS**|||||||| |RθJC|Thermal Resistance Junction to Case|TO−247||−|−|0.29|°C/W| |RθJA|Thermal Resistance Junction to Ambient|||−|−|30|°C/W| |**SWITCHING SPECIFICATIONS**(VGS= 10 V)|||||||| |tON|Turn−On Time|VDD= 50 V, ID≅ 75 A, VGS= 10 V,
RGS= 2.0�||−|−|320|ns| |td(ON)|Turn−On Delay Time|||−|18.5|−|ns| |tr|Rise Time|||−|195|−|ns| |td(OFF)|Turn−Off Delay Time|||−|80|−|ns| |tf|Fall Time|||−|190|−|ns| |tOFF|Turn−Off Time|||−|−|410|ns| |**GATE CHARGE SPECIFICATIONS**|||||||| |Qg(TOT)|Total Gate Charge|VGS= 0 V to 20 V|VDD= 50 V, ID= 75 A,
Ig(REF)= 1.0 mA
(Figures 13)|−|393|475|nC| |Qg(10)|Gate Charge at 10 V|VGS= 0 V to 10 V||−|211|255|nC| |Qg(TH)|Threshold Gate Charge|VGS= 0 V to 2 V||−|14|16.5|nC| |Qgs|Gate to Source Gate Charge|||−|26|−|nC| |Qgd|Gate to Drain “Miller” Charge|||−|74|−|nC| |**CAPACITANCE SPECIFICATIONS**|||||||| |CISS|Input Capacitance|VDS= 25 V, VGS= 0 V,
f = 1 MHz
(Figure 12)||−|7585|−|pF| |COSS|Output Capacitance|||−|2345|−|pF| |CRSS|Reverse Transfer Capacitance|||−|630|−|pF| ## **SOURCE TO DRAIN DIODE SPECIFICATIONS** |**SYMBOL**|**PARAMETER**|**TEST CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**| |---|---|---|---|---|---|---| |VSD
|Source to Drain Diode Voltage

|ISD= 75 A|−|−|1.25|V| |||ISD= 35 A|−|−|1.00|V| |trr
|Reverse Recovery Time
|ISD= 75 A, dISD/dt = 100 A/�s|−|−|150|ns| |QRR
|Reverse Recovered Charge
|ISD= 75 A, dISD/dt = 100 A/�s|−|−|490|nC| **www.onsemi.com** **3** **HUF75652G3** ## **TYPICAL PERFORMANCE CURVES** **==> picture [477 x 573] intentionally omitted <==** **----- Start of picture text -----**
1.2 80
1.0
60
0.8 VGS = 10V
0.6 40
0.4
20
0.2
0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC, CASE TEMPERATURE ( � C) TC, CASE TEMPERATURE ( � C)
Figure 1. NORMALIZED POWER DISSIPATION vs Figure 2. MAXIMUM CONTINUOUS DRAIN
CASE TEMPERATURE CURRENT vs CASE TEMPERATURE
2
DUTY CYCLE − DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
0.1
PDM
NOTES:
SINGLE PULSE DUTY FACTOR: D = t 1 /t 2 t1
PEAK TJ = PDM � Z � JC � R � JC + TC t2
0.01
10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
TC = 25 � C
FOR TEMPERATURES
1000 ABOVE 25 � C DERATE PEAK
VGS = 10V CURRENT AS FOLLOWS:
VGS = 20V I = I 25 175 − T C
150
TRANSCONDUCTANCE
100 MAY LIMIT CURRENT
IN THIS REGION
50
10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
JC
Z �
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
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**Figure 4. PEAK CURRENT CAPABILITY** **www.onsemi.com** **4** **HUF75652G3** ## **TYPICAL PERFORMANCE CURVES** (continued) **==> picture [215 x 150] intentionally omitted <==** **----- Start of picture text -----**
1000
100 100 � s
1ms
OPERATION IN THIS
10 AREA MAY BELIMITED BY rDS(ON)DS(ON)
LIMITED BY rDS(ON)DS(ON) 10ms
SINGLE PULSE
TJ = MAX RATEDJ = MAX RATED= MAX RATED
TC = 25C = 25= 25 � C
1
1 10 100 5000
VDS , DRAIN TO SOURCE VOLTAGE (V)DS , DRAIN TO SOURCE VOLTAGE (V) , DRAIN TO SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
IDD
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1000 1000
If R = 0
tAV = (L)(IAS)/(1.3 � RATED BVDSS − VDD)
If R � 0
tAV = (L/R)ln[(IAS � R)/(1.3 � RATED BVDSS − VDD) +1]
100 100 � s
100 STARTING T J = 25 � C
1ms
OPERATION IN THIS
10 AREA MAY BELIMITED BY rDS(ON)DS(ON) 10ms STARTING TJ = 150 � C
SINGLE PULSE
TJ = MAX RATEDJ = MAX RATED= MAX RATED
TC = 25C = 25= 25 � C
1 10
1 10 100 5000 0.01 0.1 1 10
VDS , DRAIN TO SOURCE VOLTAGE (V)DS , DRAIN TO SOURCE VOLTAGE (V) , DRAIN TO SOURCE VOLTAGE (V) tAV , TIME IN AVALANCHE (ms)
Figure 5. FORWARD BIAS SAFE OPERATING AREA Figure 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
200 200
PULSE DURATION = 80 � s VGS = 20V VGS = 7V
DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 6V
VDD = 15V
150 150 VGS =5V
100 100
T J = 175 � C
50 TJ = 25 � C 50
PULSE DURATION = 80 � s
DUTY CYCLE = 0.5% MAX
0 T J = −55 � C 0 TC = 25 � C
2 3 4 5 6 0 1 2 3 4
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. TRANSFER CHARACTERISTICS Figure 8. SATURATION CHARACTERISTICS
2.5 1.2
PULSE DURATION = 80 � s VGS = VDS, ID = 250 � A
DUTY CYCLE = 0.5% MAX
2.0 1.0
1.5 0.8
1.0 0.6
VGS = 10V, I D = 75A
0.5 0.4
−80 −40 0 40 80 120 160 200 −80 −40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( � C) TJ, JUNCTION TEMPERATURE ( � C)
, DRAIN CURRENT (A)
IDD , AVALANCHE CURRENT (A)
IAS
DRAIN CURRENT (A) , DRAIN CURRENT (A)
ID, ID
ON RESISTANCE NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
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**Figure 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATU** **Figure 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE** **www.onsemi.com** **5** **HUF75652G3** ## **TYPICAL PERFORMANCE CURVES** (continued) **==> picture [480 x 163] intentionally omitted <==** **----- Start of picture text -----**
1.2 20000
ID = 250 � A CISS = CGS + CGD
10000
C RSS = C GD
1.1
1000
1.0 COSS � CDS + CGD
VGS = 0V, f = 1MHz
0.9 100
−80 −40 0 40 80 120 160 200 0.1 1.0 10 100
TJ, JUNCTION TEMPERATURE ( � C) VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
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**Figure 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE** **Figure 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE** **==> picture [232 x 164] intentionally omitted <==** **----- Start of picture text -----**
10
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2
ID = 75A
ID = 35A
0
0 50 100 150 200 250
Qg, GATE CHARGE (nC)
, GATE TO SOURCE VOLTAGE (V)
GS
V
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**Figure 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT** **www.onsemi.com** **6** **HUF75652G3** ## **TEST CIRCUITS AND WAVEFORMS** **==> picture [227 x 148] intentionally omitted <==** **----- Start of picture text -----**
VDS
L
VARY t P TO OBTAIN +
REQUIRED PEAK IAS RG VDD
VGS −
DUT
tP
0V IAS
0.01 �
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BVDSS
tP
VDS
IAS
VDD
0
tAV
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**Figure 14. UNCLAMPED ENERGY TEST CIRCUIT** **Figure 15. UNCLAMPED ENERGY WAVEFORMS** **==> picture [197 x 149] intentionally omitted <==** **----- Start of picture text -----**
VDS
RL
VGS +
VDD
−
DUT
IG(REF)
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VDD Qg(TOT)
VDS
VGS = 20V
Qg(10)
VGS VGS = 10V
VGS = 2V
0
Qg(TH)
Qgs Qgd
Ig(REF)
0
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**Figure 16. GATE CHARGE TEST CIRCUIT** **Figure 17. GATE CHARGE WAVEFORM** **==> picture [463 x 149] intentionally omitted <==** **----- Start of picture text -----**
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
VDD 10% 10%
− 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 0 10%
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**Figure 18. SWITCHING TIME TEST CIRCUIT** **Figure 19. SWITCHING TIME WAVEFORM** **www.onsemi.com** **7** **HUF75652G3** ## _**PSPICE Electrical Model**_ .SUBCKT HUF75652 2 1 3 ; rev 11 May 1999 CA 12 8 11.0e−9 CB 15 14 11.4e−9 CIN 6 8 6.95e−9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD **==> picture [493 x 307] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DBREAK 5 11 DBREAKMOD
DPLCAP 5 DRAIN
DPLCAP 10 5 DPLCAPMOD
2
10
RLDRAIN
EBREAK 11 7 17 18 117.5 RSLC1
EDS 14 8 5 8 1 51 DBREAK
EGS 13 8 6 8 1 RSLC2
ESG 6 10 6 8 1 ESLC 11
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1 − 50 +
6 RDRAIN 17 DBODY
ESG EBREAK 18
IT 8 17 1 + 8 EVTHRES 16 −
LDRAIN 2 5 1.0e−9 LGATE EVTEMP + 198 − 21 MWEAK
LGATE 1 9 5.74e−9 GATE RGATE + 18 − 6
LSOURCE 3 7 4.65e−9 1 22 MMED
9 20
MSTRO
MMED 16 6 8 8 MMEDMOD RLGATE
MSTRO 16 6 8 8 MSTROMOD LSOURCE
MWEAK 16 21 8 8 MWEAKMOD CIN 8 7 SOURCE3
RBREAK 17 18 RBREAKMOD 1 RSOURCE
RLSOURCE
RDRAIN 50 16 RDRAINMOD 2.80e−3
RGATE 9 20 0.85 S1A S2A
RLDRAIN 2 5 10 12 13 14 15 RBREAK
17 18
RLGATE 1 9 57.4 8 13
RLSOURCE 3 7 46.5
S1B S2B RVTEMP
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3 CA 13 CB 19
RSOURCE 8 7 RSOURCEMOD 2.50e−3 + + 14 IT —_ −
RVTHRES 22 8 RVTHRESMOD 1 6 5 VBAT
RVTEMP 18 19 RVTEMPMOD 1 EGS 8 EDS 8 +
S1A 6 12 13 8 S1AMOD − − 8 22
S1B 13 12 13 8 S1BMOD
RVTHRES
+
−
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MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.80e−3 RGATE 9 20 0.85 RLDRAIN 2 5 10 RLGATE 1 9 57.4 RLSOURCE 3 7 46.5 RSLC1 5 51 RSLCMOD 1e−6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.50e−3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD ## VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51) /ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*455),2))} .MODEL DBODYMOD D (IS = 6.55e−12 IKF = 30 RS = 1.69e−3 TRS1= 1.95e−3 TRS2 = 1.05e−6 CJO = 8.71e−9 TT = 7.81e−8 M = 0.50) .MODEL DBREAKMOD D (RS = 1.45e−1TRS1 = 1.02e−4TRS2 = 1.11e−7) .MODEL DPLCAPMOD D (CJO = 1.00e−8IS = 1e−3 0N = 1 M = 0.85) .MODEL MMEDMOD NMOS (VTO = 2.91 KP = 6.50 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.85) .MODEL MSTROMOD NMOS (VTO = 3.37 KP = 205 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.56 KP = 0.10 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.5 ) .MODEL RBREAKMOD RES (TC1 = 1.09e−3TC2 = 1.04e−7) .MODEL RDRAINMOD RES (TC1 = 1.38e−2 TC2 = 3.75e−5) .MODEL RSLCMOD RES (TC1 = 1.05e−4 TC2 = 2.13e−7) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = −2.92e−3 TC2 = −1.48e−5) .MODEL RVTEMPMOD RES (TC1 = −3.0e−3TC2 = 1.21e−6) .MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −5.0 VOFF= −3.0) .MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −3.0 VOFF= −5.0) .MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −2.0 VOFF= 0.0) .MODEL S2BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.0 VOFF= −2.0) .ENDS NOTE: For further discussion of the PSPICE model, consult **A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank W heatley. **www.onsemi.com** **8** **HUF75652G3** ## _**SABER Electrical Model**_ REV 11 May 1999 template ta75652 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 6.55e−12, cjo = 8.71e−9, tt = 7.81e−8, m = 0.50) d..model dbreakmod = () d..model dplcapmod = (cjo = 1.0e−8, is = 1e−30, n=1, m = 0.85 ) m..model mmedmod = (type=_n, vto = 2.91, kp = 6.5, is = 1e−30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.37, kp = 205, is = 1e−30, tox = 1) **==> picture [493 x 289] intentionally omitted <==** **----- Start of picture text -----**
m..model mweakmod = (type=_n, vto = 2.56, kp = 0.1, is = 1e−30, tox = 1) LDRAIN
sw_vcsp..model s1amod = (ron = 1e−5, roff = 0.1, von = −5, voff = −3) DPLCAP 5 DRAIN
sw_vcsp..model s1bmod = (ron =1e−5, roff = 0.1, von = −3, voff = −5) 2
sw_vcsp..model s2amod = (ron = 1e−5, roff = 0.1, von = −2, voff = 0) 10
sw_vcsp..model s2bmod = (ron = 1e−5, roff = 0.1, von = 0, voff = −2) RSLC1 RLDRAIN
51 RDBREAK
c.ca n12 n8 = 11.0e−9 RSLC2
c.cb n15 n14 = 11.4e−9 ISCL 72 RDBODY
c.cin n6 n8 = 6.95e−9
d.dbody n7 n71 = model=dbodymod − 50 DBREAK
d.dbreak n72 n11 = model=dbreakmod ESG 6 RDRAIN 11 71
d.dplcap n10 n5 = model=dplcapmod + 8 EVTHRES 16
i.it n8 n17 = 1 LGATE EVTEMP + 198 − 21 MWEAK DBODY
l.lgate n1 n9 = 5.74e−9l.lsource n3 n7 = 4.65e−9m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1ul.ldrain n2 n5 = 1e−9 GATE1 RLGATE 9RGATE20+ 1822 Ll − 6 CIN MSTRO8 MMED EBREAK+−1718 7 LSOURCE SOURCE3
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u RSOURCE
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RLSOURCE
S1A S2A
res.rbreak n17 n18 = 1, tc1 = 1.09e−3, tc2 = 1.04e−7res.rdbody n71 n5 = 1.69e−3, tc1 = 1.95e−3, tc2 = 1.05e−6res.rdbody n71 n5 = 1.69e−3, tc1 = 1.95e−3, tc2 = 1.05e−6 12 138 1314 15 17 RBREAK 18
res.rdbreak n72 n5 = 1.45e−1, tc1 = 1.02e−4, tc2 = 1.11e−7
res.rdrain n50 n16 = 2.80e−3, tc1 = 1.38e−2, tc2 = 3.75e−5 S1B S2B RVTEMP
res.rgate n9 n20 = 0.85res.rldrain n2 n5 = 10res.rlgate n1 n9 = 57.4res.rlsource n3 n7 = 46.5res.rldrain n2 n5 = 10res.rlgate n1 n9 = 57.4res.rlsource n3 n7 = 46.5res.rlgate n1 n9 = 57.4res.rlsource n3 n7 = 46.5res.rlsource n3 n7 = 46.5 CA EGS13+68 EDSCB+58 14 IT +−19VBAT
res.rslc2 n5 n50 = 1e3res.rslc1 n5 n51 = 1e−6, tc1 = 1.05e−4, tc2 = 2.13e−7res.rslc1 n5 n51 = 1e−6, tc1 = 1.05e−4, tc2 = 2.13e−7 − − 8
22
res.rsource n8 n7 = 2.50e−3, tc1 = 0, tc2 = 0 RVTHRES
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res.rbreak n17 n18 = 1, tc1 = 1.09e−3, tc2 = 1.04e−7res.rdbody n71 n5 = 1.69e−3, tc1 = 1.95e−3, tc2 = 1.05e−6res.rdbody n71 n5 = 1.69e−3, tc1 = 1.95e−3, tc2 = 1.05e−6 res.rdbreak n72 n5 = 1.45e−1, tc1 = 1.02e−4, tc2 = 1.11e−7 res.rdrain n50 n16 = 2.80e−3, tc1 = 1.38e−2, tc2 = 3.75e−5 res.rgate n9 n20 = 0.85res.rldrain n2 n5 = 10res.rlgate n1 n9 = 57.4res.rlsource n3 n7 = 46.5res.rldrain n2 n5 = 10res.rlgate n1 n9 = 57.4res.rlsource n3 n7 = 46.5res.rlgate n1 n9 = 57.4res.rlsource n3 n7 = 46.5res.rlsource n3 n7 = 46.5 res.rslc2 n5 n50 = 1e3res.rslc1 n5 n51 = 1e−6, tc1 = 1.05e−4, tc2 = 2.13e−7res.rslc1 n5 n51 = 1e−6, tc1 = 1.05e−4, tc2 = 2.13e−7 res.rsource n8 n7 = 2.50e−3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = −3.0e−3, tc2 = 1.21e−6 res.rvthres n22 n8 = 1, tc1 = −2.92e−3, tc2 = −1.48e−5 spe.ebreak n11 n7 n17 n18 = 117.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/455))** 2)) } } **www.onsemi.com** **9** **HUF75652G3** ## _**SPICE Thermal Model**_ REV 1April 1999 HUF75652T CTHERM1 th 6 9.75e−3 CTHERM2 6 5 3.90e−2 CTHERM3 5 4 2.50e−2 CTHERM4 4 3 2.95e−2 CTHERM5 3 2 6.55e−2 CTHERM6 2 tl 12.55 RTHERM1 th 6 1.96e−3 RTHERM2 6 5 4.89e−3 RTHERM3 5 4 1.38e−2 RTHERM4 4 3 7.73e−2 RTHERM5 3 2 1.17e−1 RTHERM6 2 tl 1.55e−2 ## _**SABER Thermal Model**_ SABER thermal model HUF75652T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 9.75e−3 ctherm.ctherm2 6 5 = 3.90e−2 ctherm.ctherm3 5 4 = 2.50e−2 ctherm.ctherm4 4 3 = 2.95e−2 ctherm.ctherm5 3 2 = 6.55e−2 ctherm.ctherm6 2 tl = 12.55 rtherm.rtherm1 th 6 = 1.96e−3 rtherm.rtherm2 6 5 = 4.89e−3 rtherm.rtherm3 5 4 = 1.38e−2 rtherm.rtherm4 4 3 = 7.73e−2 rtherm.rtherm5 3 2 = 1.17e−1 rtherm.rtherm6 2 tl = 1.55e−2 } **==> picture [161 x 489] intentionally omitted <==** **----- Start of picture text -----**
th JUNCTION
RTHERM1 CTHERM1
6
RTHERM2 CTHERM2
5
RTHERM3 CTHERM3
4
RTHERM4 CTHERM4
3
RTHERM5 CTHERM5
2
RTHERM6 CTHERM6
tl CASE
**----- End of picture text -----**
PSPICE is a trademark of MicroSim Corporation. Saber is a registered trademark of Sabremark Limited Partnership. **www.onsemi.com** **10** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [116 x 29] intentionally omitted <==** **----- Start of picture text -----**
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
**----- End of picture text -----**
DATE 31 JAN 2019 A P1 | A E A2 @ P 0) D2 ~~1 + _~~ Q E2 ) ! S C ~~R OG )~~ D1 D B E1 2 1 2 3 ~~|~~ Oo | ~~N77~~ L1 A1 b4 L c (3X) b (2X) b2 0.25[M] B A[M] MILLIMETERS (2X) e DIM MIN NOM MAX A ~~eee~~ A 4.58 4.70 4.82 NOTES: UNLESS OTHERWISE SPECIFIED. ~~|~~ A1 2.20 2.40 2.60 A. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD ~~a~~ A2 1.40 ~~ee~~ 1.50 ~~ee~~ 1.60 ~~ee~~ b 1.17 1.26 1.35 ©. FLASH,DRAWING ANDCONFORMS TIE BAR EXTRUSIONS.TO ASME Y14.5 - 2009. ~~eeee~~ b2 1.53 ~~ee~~ 1.65 ~~ee~~ 1.77 D. DIMENSION A1 TO BE MEASURED IN THE REGION DEFINED BYL1. ~~[—~~ b4 ~~[|~~ 2.42 2.54 ~~ss~~ 2.66 c 0.51 0.61 0.71 E. LEAD FINISH IS UNCONTROLLED IN THE REGION DEFINED BY L1. ~~ee ee ee eee~~ **GENERIC** D 20.32 20.57 20.82 **MARKING DIAGRAM*** ~~ee ee ee ee~~ D1 13.08 ~ ~ ~~ee ee eee eee~~ AYWWZZ ~~ee~~ D2 ~~ee~~ 0.51 0.93 1.35 XXXXXXX ~~a~~ E ~~ee~~ 15.37 15.62 15.87 ~~eee~~ XXXXXXX ~~a~~ E1 ~~ee~~ 12.81 ~ ~~eee~~ ~ ~~a~~ E2 ~~ee~~ 4.96 5.08 ~~eee~~ 5.20 XXXX = Specific Device Code ~~a~~ e ~~ee~~ ~ 5.56 ~~eee~~ ~ A = Assembly Location Y = Year ~~ee~~ L ~~ee~~ 15.75 16.00 ~~**eee**~~ 16.25 WW = Work Week L1 3.69 3.81 3.93 ZZ = Assembly Lot Code P 3.51 3.58 3.65 *This information is generic. Please refer to ~~po |~~ ~~**|**~~ P1 6.60 6.80 7.00 device data sheet for actual part marking. ~~fo |~~ ~~**|**~~ Pb−Free indicator, “G” or microdot “ . ”, may ~~a~~ Q ~~ee~~ 5.34 5.46 5.58 or may not be present. Some products may not follow the Generic Marking. ~~a~~ S ~~ee~~ 5.34 5.46 eee 5.58 ~~ee~~ Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON13851G** Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. ## **DOCUMENT NUMBER: 98AON13851G** **DESCRIPTION: TO−247−3LD SHORT LEAD** **PAGE 1 OF 1** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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