# Power MOSFET, N Channel, 80 V, 75 A, 8200 µohm, TO-263AB, Surface Mount ![Product image](https://novapart.co/image/farnell:2454177RL/) **URL**: https://novapart.co/products/HUF75545S3ST/power-mosfet-n-channel-80-v-75-a-8200-ohm-to-263ab **SKU**: HUF75545S3ST **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.0900 **Stock**: 10+ **Lead Time**: 2 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:75A; Drain Source Voltage Vds:80V; On Resistance Rds(on):0.0082ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 270W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 270W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.0082ohm | | Transistor Case Style | TO-263AB | | Drain Source Voltage Vds | 80V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 75A | | Drain Source On State Resistance | 8200µohm | | Automotive Qualification Standard | - | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2454177RL/) ## **ON Semiconductor** ## **Is Now** **==> picture [390 x 69] intentionally omitted <==** **To learn more about onsemi™, please visit our website at www.onsemi.com** **onsemi** and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as-is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. _**HUF75545P3, HUF75545S3S**_ ## _**Data Sheet October 2013**_ ~~es~~ _**N-Channel UltraFET P**_ ~~_**o**_~~ _**wer MOSFET 80 V, 75 A, 10 mΩ**_ ## _**Features**_ ## _**Packaging**_ - Ultra Low On-Resistance - rDS(ON) = 0.010Ω, VGS = 10V **==> picture [207 x 107] intentionally omitted <==** **----- Start of picture text -----**
JEDEC TO-220AB JEDEC TO-263AB
DRAIN
SOURCE
DRAIN (FLANGE)
GATE
GATE
SOURCE
» DRAIN a’
(FLANGE)
HUF75545P3 HUF75545S3ST
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- Simulation Models - Temperature Compensated PSPICE® and SABER™ Electrical Models - Spice and SABER Thermal Impedance Models - www.onsemi.com - Peak Current vs Pulse Width Curve - UIS Rating Curve ## _**Symbol**_ **==> picture [63 x 72] intentionally omitted <==** **----- Start of picture text -----**
D
G
3 S
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## _**Ordering Information**_ |**PART NUMBER**
**PACKAGE**
HUF75545P3
TO-220AB
HUF75545S3ST
TO-263AB
~~—~~|**BRAND**
75545P
75545S| |---|---| ## **Absolute Maximum Ratings** TC = 25[o] C, Unless Otherwise Specified |**Absolute Maximum Ratings**
TC = 25C = 25= 25[o]C, Unless Otherwise Specified||| |---|---|---| ||**HUF75545P3,**|| ||**HUF75545S3ST**|**UNITS**| |Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS|80|V| |Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR|80|V| |Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS|±20|V| |Drain Current||| |Continuous (TC= 25oC, VGS= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID|75|A| |Continuous (TC= 100oC, VGS= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID|73|A| |Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM|Figure 4|| |Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS|Figure 6|| |Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD|270|W| |Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .|1.8|W/oC| |Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG|-55 to 175|oC| |Maximum Temperature for Soldering||| |Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL|300|oC| |Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg|260|oC| |NOTES:||| |1. TJ= 25oC to 150oC.||| _**CAUTION:** Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied._ Publication Order Number: ©2002 Semiconductor Components Industries, LLC. October-2017, Rev. 3 HUF75545S3S/D _**HUF75545P3, HUF75545S3S**_ ## **Electrical Specifications** TC = 25[o] C **,** Unless Otherwise Specified |**Electrical Specifications**
TC=|25oC**,**Unless|Otherwise Specified|Otherwise Specified||||| |---|---|---|---|---|---|---|---| |**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**||**MIN**|**TYP**|**MAX**|**UNITS**| |**OFF STATE SPECIFICATIONS**|||||||| |Drain to Source Breakdown Voltage|BVDSS|ID= 250µA, VGS= 0V (Figure 11)||80|-|-|V| |Zero Gate Voltage Drain Current|IDSS|VDS= 75V, VGS= 0V||-|-|1|µA| |||VDS= 70V, VGS= 0V, TC= 150oC||-|-|250|µA| |Gate to Source Leakage Current|IGSS|VGS=±20V||-|-|±100|nA| |**ON STATE SPECIFICATIONS**|||||||| |Gate to Source Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250µA (Figure 10)||2|-|4|V| |Drain to Source On Resistance|rDS(ON)|ID= 75A, VGS= 10V (Figure 9)||-|0.0082|0.010|Ω| |**THERMAL SPECIFICATIONS**|||||||| |Thermal Resistance Junction to Case|RθJC|TO-220 and TO-263||-|-|0.55|oC/W| |Thermal Resistance Junction to
Ambient|RθJA|||-|-|62|oC/W| |**SWITCHING SPECIFICATIONS**(VGS= 10V)|||||||| |Turn-On Time|tON|VDD= 40V, ID= 75A
VGS =10V,
RGS= 2.5Ω||-|-|210|ns| |Turn-On Delay Time|td(ON)|||-|14|-|ns| |Rise Time|tr|||-|125|-|ns| |Turn-Off Delay Time|td(OFF)|||-|40|-|ns| |Fall Time|tf|||-|90|-|ns| |Turn-Off Time|tOFF|||-|-|195|ns| |**GATE CHARGE SPECIFICATIONS**|||||||| |Total Gate Charge|Qg(TOT)|VGS= 0V to 20V|VDD= 40V,
ID= 75A,
Ig(REF)= 1.0mA
(Figure 13)|-|195|235|nC| |Gate Charge at 10V|Qg(10)|VGS= 0V to 10V||-|105|125|nC| |Threshold Gate Charge|Qg(TH)|VGS= 0V to 2V||-|6.8|8.2|nC| |Gate to Source Gate Charge|Qgs|||-|15|-|nC| |Gate to Drain “Miller” Charge|Qgd|||-|43|-|nC| |**CAPACITANCE SPECIFICATIONS**|||||||| |Input Capacitance|CISS|VDS= 25V, VGS= 0V,
f = 1MHz
(Figure 12)||-|3750|-|pF| |Output Capacitance|COSS|||-|1100|-|pF| |Reverse Transfer Capacitance|CRSS|||-|350|-|pF| ## **Source to Drain Diode Specifications** |**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**| |---|---|---|---|---|---|---| |Source to Drain Diode Voltage|VSD|ISD= 75A|-|-|1.25|V| |||ISD= 35A|-|-|1.00|V| |Reverse Recovery Time|trr|ISD= 75A, dISD/dt = 100A/µs|-|-|100|ns| |Reverse Recovered Charge|QRR|ISD= 75A, dISD/dt = 100A/µs|-|-|300|nC| www.onsemi.com 2 _**HUF75545P3, HUF75545S3S**_ ## _**Typical Performance Curves**_ **==> picture [233 x 163] intentionally omitted <==** **----- Start of picture text -----**
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150 175
TC, CASE TEMPERATURE ( [o] C)
POWER DISSIPATION MULTIPLIER
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**==> picture [233 x 163] intentionally omitted <==** **----- Start of picture text -----**
80
60
VGS = 10V
40
20
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE ( [o] C)
, DRAIN CURRENT (A)
ID
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**FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE** **FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE** **==> picture [509 x 378] intentionally omitted <==** **----- Start of picture text -----**
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
TC = 25 [o] C
FOR TEMPERATURES
1000 ABOVE 25 [o] C DERATE PEAK
CURRENT AS FOLLOWS:
I = I25 175 - T C
150
VGS = 10V
100 TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
, NORMALIZED
JC
θ
Z
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
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**FIGURE 4. PEAK CURRENT CAPABILITY** www.onsemi.com 3 _**HUF75545P3, HUF75545S3S**_ ## _**Typical Performance Curves**_ **(Continued)** **==> picture [233 x 163] intentionally omitted <==** **----- Start of picture text -----**
600
100
100 µ s
OPERATION IN THIS 1ms
10 AREA MAY BE
LIMITED BY rDS(ON)
10ms
SINGLE PULSE
T J = MAX RATED
TC = 25 [o] C
1
1 10 100 200
VDS, DRAIN TO SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
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**FIGURE 5. FORWARD BIAS SAFE OPERATING AREA** **==> picture [233 x 162] intentionally omitted <==** **----- Start of picture text -----**
600
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25 [o] C
100
STARTING T J = 150 [o] C
10
0.001 0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
, AVALANCHE CURRENT (A)
IAS
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NOTE: Refer to ON Semiconductor Application Notes AN9321 and AN9322. **FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY** **==> picture [234 x 163] intentionally omitted <==** **----- Start of picture text -----**
150
PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
120 VDD = 15V
90
60
TJ = 175 [o] C
30
TJ = 25 [o] C TJ = -55 [o] C
0
2 3 4 5 6
VGS, GATE TO SOURCE VOLTAGE (V)
DRAIN CURRENT (A)
ID,
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**FIGURE 7. TRANSFER CHARACTERISTICS** **==> picture [233 x 163] intentionally omitted <==** **----- Start of picture text -----**
2.5
PULSE DURATION = 80 µ s VGS = 10V, ID = 75A
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C)
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
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**FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE** **==> picture [234 x 163] intentionally omitted <==** **----- Start of picture text -----**
150
VGS = 20V VG S = 7V
VGS = 10V VG S = 6V
120
90 V GS =5V
60
30 PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
TC = 25 [o] C
0
0 1 2 3 4
VDS, DRAIN TO SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
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**FIGURE 8. SATURATION CHARACTERISTICS** **==> picture [233 x 163] intentionally omitted <==** **----- Start of picture text -----**
1.2
VGS = VDS, ID = 250 µ A
1.0
0.8
0.6
0.4
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C)
NORMALIZED GATE
THRESHOLD VOLTAGE
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**FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE** www.onsemi.com 4 _**HUF75545P3, HUF75545S3S**_ ## _**Typical Performance Curves**_ **(Continued)** **==> picture [509 x 163] intentionally omitted <==** **----- Start of picture text -----**
1.2 10000
ID = 250 µ A
CISS = CGS + CGD
1.1
C OSS ≅ C DS + C GD
1.0 1000
0.9
C RSS = C GD
VGS = 0V, f = 1MHz
0.8 100
-80 -40 0 40 80 120 160 200 0.1 1 10 80
TJ, JUNCTION TEMPERATURE ( [o] C) VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
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**FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE** **FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE** **==> picture [233 x 164] intentionally omitted <==** **----- Start of picture text -----**
10
VDD = 40V
8
6
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 75A
ID = 35A
0
0 30 60 90 120
Qg, GATE CHARGE (nC)
, GATE TO SOURCE VOLTAGE (V)
GS
V
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**==> picture [272 x 20] intentionally omitted <==** **----- Start of picture text -----**
NOTE: Refer to ON Semiconductor Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE
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**CURRENT** www.onsemi.com 5 _**HUF75545P3, HUF75545S3S**_ ## _**Test Circuits and Waveforms**_ **==> picture [226 x 149] intentionally omitted <==** **----- Start of picture text -----**
VDS
L
VARY tP TO OBTAIN +
REQUIRED PEAK IAS RG VDD
VGS -
DUT
tP
0V IAS
0.01 Ω
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**FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT** **==> picture [196 x 148] intentionally omitted <==** **----- Start of picture text -----**
VDS
RL
VGS +
VDD
-
DUT
Ig(REF)
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**FIGURE 16. GATE CHARGE TEST CIRCUIT** **==> picture [220 x 143] intentionally omitted <==** **----- Start of picture text -----**
VDS
RL
VGS +
VDD
-
DUT
RGS
VGS
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**FIGURE 18. SWITCHING TIME TEST CIRCUIT** **==> picture [221 x 139] intentionally omitted <==** **----- Start of picture text -----**
BVDSS
tP
VDS
IAS
VDD
0
tAV
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**FIGURE 15. UNCLAMPED ENERGY WAVEFORMS** **==> picture [238 x 149] intentionally omitted <==** **----- Start of picture text -----**
VDD Qg(TOT)
VDS
VGS = 20V
Qg(10)
VGS VGS = 10V
VGS = 2V
0
Qg(TH)
Qgs Qgd
Ig(REF)
0
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**FIGURE 17. GATE CHARGE WAVEFORMS** **==> picture [220 x 149] intentionally omitted <==** **----- Start of picture text -----**
tON tOFF
td(ON) td(OFF)
tr tf
VDS
90% 90%
10% 10%
0
90%
VGS 50% 50%
PULSE WIDTH
10%
0
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**FIGURE 19. SWITCHING TIME WAVEFORM** www.onsemi.com 6 _**HUF75545P3, HUF75545S3S**_ ## _**PSPICE Electrical Model**_ .SUBCKT HUF75545 2 1 3 ; rev 21 May 1999 CA 12 8 5.4e-9 CB 15 14 5.3e-9 CIN 6 8 3.4e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD **==> picture [382 x 311] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
5
51 ESLC 11
- 50 +
ESG 6 RDRAIN EBREAK 1718 DBODY
+ 8 EVTHRES 16 -
+ 19 - 21 MWEAK
LGATE EVTEMP 8
GATE RGATE + 18 - 6
1 22 MMED
9 20
MSTRO
RLGATE
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 RBREAK
17 18
8 13
S1B S2B RVTEMP
13 CB 19
CA
+ + 14 IT -
6 5 VBAT
EGS 8 EDS 8 +
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
EBREAK 11 7 17 18 87.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.1e-9 LSOURCE 3 7 4.4e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4.80e-3 RGATE 9 20 0.87 RLDRAIN 2 5 10 RLGATE 1 9 51 RLSOURCE 3 7 44 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.6e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD ## VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320),3))} .MODEL DBODYMOD D (IS = 3.6e-12 RS = 2.1e-3 TRS1 = 1.5e-3 TRS2 = 5.1e-6 CJO = 4.6e-9 TT = 3.3e-8 M = 0.55) .MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 0 TRS2 = -1.8e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10 VJ = 1 M = 0.8) .MODEL MMEDMOD NMOS (VTO = 3.04 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.87) .MODEL MSTROMOD NMOS (VTO = 3.5 KP = 105 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.7 ) .MODEL RBREAKMOD RES (TC1 = 1.3e-3 TC2 = -1e-6) .MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2.8e-5) .MODEL RSLCMOD RES (TC1 = 1.53e-3 TC2 = 2e-5) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5) .MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0.5) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.5) .ENDS NOTE: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 7 _**HUF75545P3, HUF75545S3S**_ ## _**SABER Electrical Model**_ ## REV 21 may 1999 template huf75545 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.6e-12, cjo = 4.6e-9, tt = 3.3e-8, m = 0.55) d..model dbreakmod = () d..model dplcapmod = (cjo = 4.8e-9, is = 1e-30, vj=1.0, m = 0.8 ) m..model mmedmod = (type=_n, vto = 3.04, kp = 6, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.5) **==> picture [364 x 296] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 RDBREAK
RSLC2
ISCL 72 RDBODY
- 50 DBREAK
6 RDRAIN 71
ESG 11
8
+ EVTHRES 16
LGATE EVTEMP + 198 - 21 MWEAK DBODY
GATE1 9RGATE20+ 1822 - 6 MMED EBREAK+
RLGATE MSTRO 17
18
CIN 8 - 7 LSOURCE SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
13 CB 19
CA + + 14 IT -
6 5 VBAT
EGS 8 EDS 8 +
- - 8
22
RVTHRES
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c.ca n12 n8 = 5.4e-9 c.cb n15 n14 = 5.3e-9 c.cin n6 n8 = 3.4e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.4e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -1e-6 res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6 res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5 res.rdrain n50 n16 = 4.8e-3, tc1 = 9e-3, tc2 = 2.8e-5 res.rgate n9 n20 = 0.87 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51 res.rlsource n3 n7 = 44 res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 2e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7 res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5 spe.ebreak n11 n7 n17 n18 = 87.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3)) } } www.onsemi.com 8 _**HUF75545P3, HUF75545S3S**_ ## _**SPICE Thermal Model**_ REV 21 May 1999 HUF75545T CTHERM1 th 6 6.4e-3 CTHERM2 6 5 3.0e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.6e-2 CTHERM5 3 2 5.5e-2 CTHERM6 2 tl 1.5 RTHERM1 th 6 3.2e-3 RTHERM2 6 5 8.1e-3 RTHERM3 5 4 2.3e-2 RTHERM4 4 3 1.3e-1 RTHERM5 3 2 1.8e-1 RTHERM6 2 tl 3.8e-2 ## _**SABER Thermal Model**_ SABER thermal model HUF75545T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 6.4e-3 ctherm.ctherm2 6 5 = 3.0e-2 ctherm.ctherm3 5 4 = 1.4e-2 ctherm.ctherm4 4 3 = 1.6e-2 ctherm.ctherm5 3 2 = 5.5e-2 ctherm.ctherm6 2 tl = 1.5 rtherm.rtherm1 th 6 = 3.2e-3 rtherm.rtherm2 6 5 = 8.1e-3 rtherm.rtherm3 5 4 = 2.3e-2 rtherm.rtherm4 4 3 = 1.3e-1 rtherm.rtherm5 3 2 = 1.8e-1 rtherm.rtherm6 2 tl = 3.8e-2 } **==> picture [160 x 489] intentionally omitted <==** **----- Start of picture text -----**
th JUNCTION
RTHERM1 CTHERM1
6
RTHERM2 CTHERM2
5
RTHERM3 CTHERM3
4
RTHERM4 CTHERM4
3
RTHERM5 CTHERM5
2
RTHERM6 CTHERM6
tl CASE
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