# Power MOSFET, N Channel, 600 V, 1.9 A, 3.6 ohm, TO-251, Through Hole

![Product image](https://novapart.co/image/farnell:3368834/)

**URL**: https://novapart.co/products/FQU2N60CTU/power-mosfet-n-channel-600-v-19-a-36-ohm-to-251
**SKU**: FQU2N60CTU
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.5510
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | QFET |
| Power Dissipation | 44W |
| Transistor Mounting | Through Hole |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 44W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 3.6ohm |
| Transistor Case Style | TO-251 |
| Drain Source Voltage Vds | 600V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 1.9A |
| Drain Source On State Resistance | 3.6ohm |
| Gate Source Threshold Voltage Max | 4V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3368834/)

**DATA SHEET** ~~oe~~ **www.onsemi.com** 

## MOSFET – N-Channel, QFET 

QFET **VDSS RDS(ON) MAX ID MAX** 600 V 4.7  @ 10 V 1.9 A 600 V, 1.9 A, 4,7 D FQD2N60C / FQU2N60C This N−Channel enhancement mode power MOSFET is produced G using **onsemi** ’s proprietary planar stripe and DMOS technology. This advanced MOSFET technology has been especially tailored to reduce on−state resistance, and to provide superior switching performance ~~g~~ S and high avalanche energy strength. These devices are suitable for switched mode power supplies, active power factor correction (PFC), and electronic lamp ballasts. 

## 600 V, 1.9 A, 4,7 

## FQD2N60C / FQU2N60C 

## **Features** 

- 1.9 A, 600 V, RDS(on) = 4.7  (Max.) @ VGS = 10 V, ID = 0.95 A 

- Low Gate Charge (Typ. 8.5 nC) 

- Low Crss (Typ. 4.3 pF) 

- 100% Avalanche Tested 

- These Devices are Halid Free and are RoHS Compliant 

**DPAK3 (IPAK) DPAK3 (TO−252 3 LD) CASE 369AR CASE 369AS** 

**MAXIMUM RATINGS** (TC = 25 ° C unless otherwise noted) 

|**MAXIMUM RATINGS**|**MAXIMUM RATINGS**(TC = 25C = 25= 25°C unless otherwise noted)|C unless otherwise noted)||
|---|---|---|---|
|**Symbol**|**Rating**|**Value**|**Unit**|
|VDSS|Drain−Source Voltage|600|V|
|ID|Drain Current − Continuous (TC= 25°C)<br>− Continuous (TC= 100°C)|1.9<br>1.14|A|
|IDM|Drain Current − Pulsed<br>(Note 1)|7.6|A|
|VGSS|Gate−Source Voltage|±30|V|
|EAS|Single Pulsed Avalanche Energy (Note 2)|120|mJ|
|IAR|Avalanche Current<br>(Note 1)|1.9|A|
|EAR|Repetitive Avalanche Energy<br>(Note 1)|4.4|mJ|
|dv/dt|Peak Diode Recovery dv/dt<br>(Note 3)|4.5|V/ns|
|PD|Power Dissipation (TA= 25°C) *|2.5|W|
||Power Dissipation (TC= 25°C)<br>− Derate above 25°C|44<br>0.35|W<br>W/°C|
|TJ, TSTG|Operating and Storage Temperature<br>Range|−55 to<br>+150|°C|
|TL|Maximum Lead Temperature for<br>Soldering Purposes, 1/8”<br>(from case for 5 seconds)|300|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

**==> picture [142 x 63] intentionally omitted <==**

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MARKING DIAGRAMS<br>$Y&Z&3&K $Y&Z&3&K<br>FQU FQD<br>2N60C 2N60C<br>**----- End of picture text -----**<br>


FQD2N60C, FQU2N60C = Device Code $Y = **onsemi** Logo &Z = Assembly Location &3 = Date Code &K = Lot Run Traceability Code 

**ORDERING INFORMATION** 

**Device Package Shipping**[†] FQD2N60CTM DPAK3 2500 / (TO−252 3 LD) Tape & Reel (Pb−Free) FQU2N60CTU DPAK3 (IPAK) 70 Units / Tube (Pb−Free) ~~ee~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

Publication Order Number: **FQU2N60C/D** 

**1** 

© Semiconductor Components Industries, LLC, 2004 **April, 2022 − Rev. 3** 

**FQD2N60C / FQU2N60C** 

## **THERMAL CHARACTERISTICS** 

|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|R�JC|Thermal Resistance, Junction−to−Case, Max.|2.87|°C/W|
|R�JA|Thermal Resistance, Junction−to−Ambient(minimum pad of 2 oz copper), Max.|110|°C/W|
||Thermal Resistance, Junction−to−Ambient (* 1 in2pad of 2 oz copper), Max.|50||



## **ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise specified) 

|**ELECTRIC**|**AL CHARACTERISTICS**(TC= 25°C unles|s otherwise specified)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|BVDSS|Drain−to−Source Breakdown Voltage|ID= 250�A, VGS= 0 V|600|−|−|V|
|�BVDSS/<br>�TJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250�A, Referenced to 25°C|−|0.6|−|V/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 600 V, VGS= 0 V|−|−|1|�A|
|||VDS= 480 V, TC= 125°C|−|−|10||
|IGSSF|Gate−Body Leakage Current, Forward|VGS= 30 V, VDS= 0 V|−|−|100|nA|
|IGSSR|Gate−Body Leakage Current, Reverse|VGS= −30 V, VDS= 0 V|−|−|−100|nA|
|**ON CHARACTERISTICS**|||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= 250�A|2.0|−|4.0|V|
|RDS(on)|Static Drain−Source On Resistance|VGS= 10 V, ID= 0.95 A|−|3.6|4.7|�|
|gFS|Forward Transconductance|VDS= 40 V, ID= 0.95 A|−|5.0|−|S|
|**DYNAMIC CHARACTERISTICS**|||||||
|Ciss|Input Capacitance|VDS= 25 V, VGS= 0 V,<br>f = 1.0 MHz|−|180|235|pF|
|Coss|Output Capacitance||−|20|25||
|Crss|Reverse Transfer Capacitance||−|4.3|5.6||
|**SWITCHING CHARACTERISTICS**|||||||
|td(on)|Turn−On Delay Time|VDD= 300 V, ID= 2 A,<br>RG= 25�<br>(Note 4)|−|9|28|ns|
|tr|Turn−On Rise Time||−|25|60||
|td(off)|Turn−Off Delay Time||−|24|58||
|tf|Turn−Off Fall Time||−|28|66||
|Qg|Total Gate Charge|VDS= 480 V, ID= 2 A,<br>VGS= 10 V<br>(Note 4)|−|8.5|12|nC|
|Qgs|Gate−Source Charge||−|1.3|−||
|Qgd|Gate−Drain Charge||−|4.1|−||
|**DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**|||||||
|IS|Maximum Continuous Drain−Source Diode Forward Current||−|−|1.9|A|
|ISM|Maximum Pulsed Drain−Source Diode Forward Current||−|−|7.6|A|
|VSD|Drain−Source Diode Forward Voltage|VGS= 0 V, IS= 1.6 A|−|−|1.4|V|
|trr|Reverse Recovery Time|VGS= 0 V, IS= 2 A,<br>dIF/dt = 100 A/�s|−|230|−|ns|
|Qrr|Reverse Recovery Charge||−|1.0|−|�C|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

1. Repetitive Rating : Pulse width limited by maximum junction temperature. 

2. L = 56 mH, IAS = 2 A, VDD = 50 V, RG = 25 � , Starting TJ = 25 ° C. 

3. ISD ≤ 2.0 A, di/dt ≤ 200A/ � s, VDD ≤ BVDSS, Starting TJ = 25 ° C. 

4. Essentially independent of operating temperature. 

**www.onsemi.com** 

**2** 

**FQD2N60C / FQU2N60C** 

## **TYPICAL CHARACTERISTICS** 

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**----- Start of picture text -----**<br>
10 [0]<br>VGS<br>Top:  15.0 V<br>10.0 V<br>8.0 V<br>10 [−1] 7.0 V<br>6.5 V<br>6.0 V<br>*Notes: 5.5 V<br>1. 250  � s Pulse Test 5.0 V<br>10 [−2] 2. TC = 25 ° C Bottom: 4.5 V<br>10 [−1] 10 [0] 10 [1]<br>VDS, Drain−Source Voltage (V)<br>Figure 1. On−Region Characteristics<br>12<br>10<br>8 VGS = 10 V<br>6<br>4<br>VGS = 20 V<br>2<br>*Note: TJ = 25 ° C<br>0<br>0 1 2 3 4 5<br>ID, Drain Current (A)<br>, Drain Current (A)<br>ID<br>) �<br>, Drain−Source On−Resistance (<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance Variation vs. Drain Current and Gate Voltage** 

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10 [1]<br>150 ° C<br>10 [0] 25 ° C −55 ° C<br>*Notes:<br>1. VDS = 40 V<br>2. 250  � s Pulse Test<br>10 [−1]<br>2 4 6 8 10<br>VGS, Gate−Source Voltage (V)<br>Figure 2. Transfer Characteristics<br>10 [0] 150 ° C 25 ° C<br>*Notes:<br>1. V GS  = 0 V<br>2. 250  � s Pulse Test<br>10 [−1]<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4<br>VSD, Source−Drain Voltage (A)<br>, Drain Current (A)<br>ID<br>, Reverse Drain Current (A)<br>IDR<br>**----- End of picture text -----**<br>


**Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature** 

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500 12<br>C iss = C gs + C gd (C ds = shorted)<br>450 Coss = Cds + Cgd VDS = 120 V<br>400 C rss = C gd 10 VDS = 300 V<br>350 C iss 8 VDS = 480 V<br>300<br>250 6<br>200 Coss<br>4<br>150<br>100 *Notes: Crss 2<br>50 1. V GS  = 0 V<br>2. f = 1 MHz *Note: ID = 2 A<br>0 0<br>10 [−1] 10 [0] 10 [1] 0 2 4 6 8 10<br>VDS, Drain−Source Voltage (V) QG, Total Gate Charge (nC)<br>Capacitance (pF)<br>, Gate−Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 5. Capacitance Characteristics** 

**Figure 6. Gate Charge Characteristics** 

**www.onsemi.com** 

**3** 

**FQD2N60C / FQU2N60C** 

## **TYPICAL CHARACTERISTICS** (continued) 

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**----- Start of picture text -----**<br>
1.2<br>1.1<br>1.0<br>0.9<br>*Notes:<br>1. VGS = 0 VGS = 0 V = 0 V<br>2. ID = 250 D = 250  = 250  � s<br>0.8<br>−100 −50 0 50 100 150 200<br>TJ, Junction Temperature (J, Junction Temperature (, Junction Temperature ( ° C)<br>Breakdown Voltage<br>, (Normalized) Drain−Source<br>DSS<br>BV<br>**----- End of picture text -----**<br>


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3.0<br>2.5<br>2.0<br>1.5<br>1.0<br>*Notes: *Notes:<br>0.5<br>1. VGS = 0 VGS = 0 V = 0 V 1. VGS = 10 V<br>2. ID = 250 D = 250  = 250  � s 2. ID = 0.95 A<br>0.0<br>−50 0 50 100 150 200 −100 −50 0 50 100 150 200<br>TJ, Junction Temperature (J, Junction Temperature (, Junction Temperature ( ° C) TJ, Junction Temperature ( ° C)<br>Figure 7. Breakdown Voltage Variation Figure 8. On−Resistance Variation<br>vs. Temperature vs. Temperature<br>2.0<br>Operation This Area<br>is Limited by RDS(on)DS(on)<br>1.6<br>100  � s<br>1.2<br>1 ms<br>10 ms<br>0.8<br>100 ms<br>*Note:<br>1. TC = 25C = 25 = 25 ° C DC 0.4<br>2. TJ = 150J = 150 = 150 ° C<br>3. Single Pulse<br>0.0<br>[[0]] 10 [[1]] 10 [[2]] 10 [[3]] 25 50 75 100 125 150<br>VDS, Drain−Source Voltage (V)DS, Drain−Source Voltage (V), Drain−Source Voltage (V) TC, Case Temperature ( ° C)<br>Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case<br>Temperature<br>D = 0.5<br>10 [0]<br>0.2<br>0.1<br>P DM<br>0.05 t1<br>0.02<br>t2<br>10 [−1] 0.01 *Notes:<br>Single Pulse 1. Z � JC(t) = 2.87 ° C/W Max.<br>2. Duty Factor, D = t1/t2<br>3. T JM  − T C  = P DM ×  Z � JC (t)<br>10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]<br>t1, Square Wave Pulse Duration (s)<br>On−Resistance<br>, (Normalized) Drain−Source<br>DS(ON)<br>R<br>, Drain Current (A)<br>ID<br>C/W)<br>°<br>(t), Thermal Response (<br>JC<br>�<br>Z<br>**----- End of picture text -----**<br>


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Operation This Area<br>10 [1] is Limited by RDS(on)DS(on)<br>100  � s<br>10 [0] 1 ms<br>10 ms<br>100 ms<br>10 [−1] *Note:<br>1. TC = 25C = 25 = 25 ° C DC<br>2. TJ = 150J = 150 = 150 ° C<br>3. Single Pulse<br>10 [−2]<br>10 [[0]] 10 [[1]] 10 [[2]] 10 [[3]]<br>VDS, Drain−Source Voltage (V)DS, Drain−Source Voltage (V), Drain−Source Voltage (V)<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Transient Thermal Response Curve** 

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**4** 

**FQD2N60C / FQU2N60C** 

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**----- Start of picture text -----**<br>
Same Type VGS<br>as DUT<br>50 k �<br>12 V Qg<br>10V<br>200 nF 300 nF<br>VDS<br>VGS Qgs Qgd<br>DUT<br>IG = const.<br>Charge<br>**----- End of picture text -----**<br>


**Figure 12. Gate Charge Test Circuit & Waveform** 

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RL<br>VDS<br>VGS VDD<br>RG<br>DUT<br>VGS<br>**----- End of picture text -----**<br>


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VDS<br>90%<br>10%<br>VGS<br>td(on) td(off) tf<br>tr<br>ton toff<br>**----- End of picture text -----**<br>


**Figure 13. Resistive Switching Test Circuit & Waveforms** 

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**----- Start of picture text -----**<br>
VDS L EAS � [1] 2 LIAS2 BVDSSBV �DSSVDD<br>ID BVDSS<br>IAS<br>RG VDD<br>ID(t)<br>DUT<br>VGS VDD VDS(t)<br>tP tp Time<br>**----- End of picture text -----**<br>


**Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms** 

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**5** 

**FQD2N60C / FQU2N60C** 

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**----- Start of picture text -----**<br>
+<br>DUT<br>VDS<br>_<br>ISD<br>L<br>Driver<br>RG Same Type<br>as DUT VDD<br>VGS •  dv/dt controlled by RG<br>•  ISD controlled by pulse period<br>Gate Pulse Width<br>VGS D = Gate Pulse Period 10 V<br>(Driver)<br>IFM, Body Diode Forward Current<br>ISD<br>di/dt<br>(DUT)<br>IRM<br>Body Diode Reverse Current<br>VDS Body Diode Recovery dv/dt<br>(DUT)<br>VSD VDD<br>Body Diode<br>Forward Voltage Drop<br>**----- End of picture text -----**<br>


**Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms** 

QFET is a registered trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

**www.onsemi.com** 

**6** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**DPAK3 (IPAK)** CASE 369AR ISSUE O 

DATE 30 SEP 2016 

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Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON13815G Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: DPAK3 (IPAK) PAGE 1 OF 1<br>**----- End of picture text -----**<br>


**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2016 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **DPAK3 6.10x6.54x2.29, 4.57P** CASE 369AS ISSUE B 

## DATE 20 DEC 2023 

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GENERIC<br>{\ aL| I \! PLEASOLSREDEFEREN ERI D O NGWNC LA E O NDADMAMOUNNUTHEALT, IO N SOLDGS EM TER E ICRM CONH N/ I D.DQ U CE TORS MARKING DIAGRAM*<br>vA<br>XXXXXX<br>[S o .1 0 ]B} XXXXXX<br>AYWWZZ<br>XXXX = Specific Device Code<br>*This information is generic. Please refer to<br>device data sheet for actual part marking. A = Assembly Location<br>Pb−Free indicator, “G” or microdot “ = ”, may Y = Year<br>or may not be present. Some products may WW = Work Week<br>not follow the Generic Marking. ZZ = Assembly Lot Code<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98AON13810G Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: DPAK3 6.10x6.54x2.29, 4.57P PAGE 1 OF 1<br>**----- End of picture text -----**<br>


**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba onsemi **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2016 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

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 



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