# Power MOSFET, P Channel, 100 V, 6.6 A, 0.53 ohm, TO-252 (DPAK), Surface Mount ![Product image](https://novapart.co/image/farnell:3368810RL/) **URL**: https://novapart.co/products/FQD8P10TM-F085/power-mosfet-p-channel-100-v-66-a-053-ohm-to-252 **SKU**: FQD8P10TM-F085 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4850 **Stock**: 500+ **Lead Time**: 113 days (indicative) ## Specifications | Parameter | Value | |---|---| | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | P Channel | | Product Range | - | | Qualification | AEC-Q101 | | Power Dissipation | 44W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252 (DPAK) | | Drain Source Voltage Vds | 100V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 6.6A | | Drain Source On State Resistance | 0.53ohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3368810RL/) **==> picture [267 x 32] intentionally omitted <==** **----- Start of picture text -----**
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FQD8P10TM F085
100V P-Channel MOSFET Features
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• -6.6A, -100V, RDS(on) = 0.53Ω @VGS = -10 V
General Description •• Low gate charge ( typical 12 nC)Low Crss ( typical 30 pF)
These P-Channel enhancement mode power field effect • Fast switching
transistors are produced using ON Semiconductor’s • 100% avalanche tested
proprietary, planar stripe, DMOS technology. • Improved dv/dt capability
This advanced technology has been especially tailored to • Qualified to AEC Q101
minimize on-state resistance, provide superior switching • RoHS Compliant
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for low voltage applications such as audio amplifier,
high efficiency switching DC/DC converters, and DC motor
control.
D
D
ia
G
D-PAK
G S
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Symbol Pp Parameter Po Ratings Units
VDSS pO Drain-Source Voltage po -100 V
ID Drain Current - Continuous (TC = 25°C) po -6.6 A
- Continuous (TC = 100°C) -4.2 A
IDM eea Drain Current - Pulsed (Note 1) eee -26.4 A
VGSS a Gate-Source Voltage ± 30 V
EAS a Single Pulsed Avalanche Energy (Note 2) 150 mJ
IAR Avalanche Current (Note 1) -6.6 A
EAR Repetitive Avalanche Energy (Note 1) 4.4 mJ
dv/dt PO Peak Diode Recovery dv/dt (Note 3) -6.0 V/ns
PD po Power Dissipation (TA = 25°C) * po 2.5 W
Power Dissipation (TC = 25°C) po 44 W
- Derate above 25°C 0.35 W/°C
TJ, TSTG a Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
TL 1/8" from case for 5 seconds 300 °C
ee
Thermal Characteristics
Symbol Parameter Typ Max Units
RθJC Thermal Resistance, Junction-to-Case -- 2.84 °C / W
RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C / W
RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C / W
* When mounted on the minimum pad size recommended (PCB Mount)
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©2010 Semiconductor Components Industries, LLC. 1
September-2017, Rev. 3
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Publication Order Number:
FQD8P10TM-F085/D
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|**Electrical Characteristics**TC= 25°C|**Electrical Characteristics**TC= 25°C|unless otherwise noted||||| |---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Units**| |**Off Characteristics**||||||| |BVDSS|Drain-Source Breakdown Voltage|VGS= 0 V, ID= -250µA|-100|--|--|V| |∆BVDSS
/∆TJ|Breakdown Voltage Temperature
Coefficient|ID= -250µA, Referenced to 25°C|--|-0.1|--|V/°C| |IDSS|Zero Gate Voltage Drain Current|VDS= -100 V, VGS= 0 V|--|--|-1|µA| |||VDS= -80 V, TC= 125°C|--|--|-10|µA| |IGSSF|Gate-Body Leakage Current, Forward|VGS= -30 V, VDS= 0 V|--|--|-100|nA| |IGSSR|Gate-Body Leakage Current, Reverse|VGS= 30 V, VDS= 0 V|--|--|100|nA| |**On Characteristics**||||||| |VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= -250µA|-2.0|--|-4.0|V| |RDS(on)|Static Drain-Source
On-Resistance|VGS= -10 V, ID= -3.3 A|--|0.41|0.53|Ω| |gFS|Forward Transconductance|(Note 4)
VDS= -40 V, ID= -3.3 A|--|4.1|--|S| |**Dynamic Characteristics**||||||| |Ciss|Input Capacitance|VDS= -25 V, VGS= 0 V,
f = 1.0 MHz|--|360|470|pF| |Coss|Output Capacitance||--|120|155|pF| |Crss|Reverse Transfer Capacitance||--|30|40|pF| |**Switching Characteristics**||||||| |td(on)|Turn-On Delay Time|(Note 4, 5)
VDD= -50 V, ID= -8.0 A,
RG= 25Ω|--|11|30|ns| |tr|Turn-On Rise Time||--|110|230|ns| |td(off)|Turn-Off Delay Time||--|20|50|ns| |tf|Turn-Off Fall Time||--|35|80|ns| |Qg|Total Gate Charge|(Note 4, 5)
VDS= -80 V, ID= -8.0 A,
VGS= -10 V|--|12|15|nC| |Qgs|Gate-Source Charge||--|3.0|--|nC| |Qgd|Gate-Drain Charge||--|6.4|--|nC| |**Drain-Source Diode Characteristics and Maximum Ratings**||||||| |IS|Maximum Continuous Drain-Source Diode Forward Current||--|--|-6.6|A| |ISM|Maximum Pulsed Drain-Source Diode Forward Current||--|--|-26.4|A| |VSD|Drain-Source Diode Forward Voltage|VGS= 0 V, IS= -6.6 A|--|--|-4.0|V| |trr|Reverse Recovery Time|(Note 4)
VGS= 0 V, IS= -8.0 A,
dIF/ dt = 100 A/µs|--|98|--|ns| |Qrr|Reverse Recovery Charge||--|0.35|--|µC| ## **Notes:** 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 5.2mH, IAS = -6.6A, VDD = -25V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ -8.0A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature **www.onsemi.com** **2** ## **Typical Characteristics** **==> picture [422 x 566] intentionally omitted <==** **----- Start of picture text -----**
101 Top : -15.0 V V-10.0 VGS
-8.0 V 101
-7.0 V
-6.5 V
-5.5 V
100 Bottom : -4.5 V -5.0 V
150℃
100
25℃
10-1
-55℃
※ Notes : ※ Notes :
1. 250μ s Pulse Test 1. VDS = -40V
2. TC = 25℃ 2. 250μ s Pulse Test
10-210-1 100 101 10-1 2 4 6 8 10
-VDS, Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V]
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
1.5
1.2 VGS = - 10V 101
0.9 VGS = - 20V
0.6 100
150℃ 25℃
0.3 ※ Notes :
※ Note : TJ = 25℃ 1. V 2. 250GS = 0Vμ s Pulse Test
0.0 10-1
0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage Variation vs. Source Current
and Temperature
900 12
Ciss = Cgs + Cgd (Cds = shorted)
800 Coss CCossrss = C = Cgdds + Cgd 10 VDS = -20V
700 Ciss VDS = -50V
600 ※ Notes : 8 VDS = -80V
500 2. f = 1 MHz1. VGS = 0 V
6
400
Crss
300 4
200
2
100 ※ Note : ID = -8.0 A
0 0
10-1 100 101 0 2 4 6 8 10 12 14
-VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC]
, Drain Current [A]-ID , Drain Current [A]-ID
],
Ω
[
DS(on)
R
Drain-Source On-Resistance
, Reverse Drain Current [A]
DR
-I
Capacitance [pF]
, Gate-Source Voltage [V]
GS
-V
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**Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics** **www.onsemi.com** **3** **==> picture [428 x 602] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics (Continued)
1.2 3.0
2.5
1.1
2.0
1.0 1.5
1.0
0.9 ※ Notes :
1. V 2. IDGS = -250 = 0 Vμ A 0.5 ※ 2. I 1. V Notes :DGS = -3.3 A = -10 V
0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
TJ, Junction Temperature [oC] TJ, Junction Temperature [oC]
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
102 7
Operation in This Area
is Limited by R DS(on) 6
100 µs 5
101 1 ms
4
10 ms
DC
3
100
2
※ Notes :
1. T 3. Single Pulse 2. TCJ = 150 = 25 oCoC 1
10-1100 101 102 025 50 75 100 125 150
-VDS, Drain-Source Voltage [V] TC, Case Temperature [℃]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
D = 0 .5
1 0 0 ※ N o te s :
0 .2 1 . Z θ J C [(t) = 2 .8 4 ][℃] [/W] [ M a x .]
0 .1 2 . D u ty F a c to r, D = t 3 . T J M - T C = P D M * Z 1θ/t 2J C [(t)]
0 .0 5
1 0 -1 0 .0 2 PDM
0 .0 1 s in g le p u ls e t1 t2
1 0 -5 1 0 -4 1 0 -3 1 0 -2 1 0 -1 1 0 0 1 0 1
t 1 , S q u a re W a v e P u ls e D u ra tio n [s e c ]
Figure 11. Transient Thermal Response Curve
, (Normalized) , (Normalized)
DSS DS(ON)
-BV R
Drain-Source On-Resistance
Drain-Source Breakdown Voltage
, Drain Current [A]-ID , Drain Current [A]-ID
(t), T h e rm a l R e s p o n s eJ C
Z θ
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Gate Charge Test Circuit & Waveform
VGS
Same Type
50KΩ as DUT Qg
12V 200nF 300nF -10V
VGS VDS Qgs Qgd
DUT
-3mA
Charge
Resistive Switching Test Circuit & Waveforms
RL
VDS t on t off
RG VGS VDD VGS 10% td(on) tr td(off) tf
DUT
-10V
VDS 90%
Unclamped Inductive Switching Test Circuit & Waveforms
VDS L EAS = ----12 L IAS2 --------------------BVBVDSSDSS- VDD
t p Time
I D
RG VDD VDD VDS (t)
ID (t)
-10V DUT
IAS
t p BVDSS
FQD8P10TM
-
F085 100V P-Channel MOSFET
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Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
VDS
DUT
_
I SD
L
Driver
RG
Compliment of DUT
(N-Channel) VDD
VGS • dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
VGS D = --------------------------Gate Pulse Period 10V
( Driver )
Body Diode Reverse Current
I SD
( DUT ) IRM
di/dt
IFM , Body Diode Forward Current
VDS VSD
( DUT )
Body Diode VDD
Forward Voltage Drop
Body Diode Recovery dv/dt
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