# Dual MOSFET, Complementary N and P Channel, 30 V, 30 V, 6.4 A, 6.4 A, 0.021 ohm ![Product image](https://novapart.co/image/farnell:4319711/) **URL**: https://novapart.co/products/FDS8958B./dual-mosfet-complementary-n-and-p-channel-30-v-64 **SKU**: FDS8958B. **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Dual MOSFETs **Price**: €0.2540 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 8Pins | | Channel Type | Complementary N and P Channel | | Product Range | - | | Qualification | - | | Transistor Case Style | SOIC | | Operating Temperature Max | 150°C | | Power Dissipation N Channel | 2W | | Power Dissipation P Channel | 2W | | Drain Source Voltage Vds N Channel | 30V | | Drain Source Voltage Vds P Channel | 30V | | Continuous Drain Current Id N Channel | 6.4A | | Continuous Drain Current Id P Channel | 6.4A | | Drain Source On State Resistance N Channel | 0.021ohm | | Drain Source On State Resistance P Channel | 0.021ohm | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:4319711/) ## **ON Semiconductor** ## **Is Now** **==> picture [390 x 69] intentionally omitted <==** **To learn more about onsemi™, please visit our website at www.onsemi.com** **onsemi** and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as-is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. ## **FDS8958B** ## **Dual N & P-Channel PowerTrench[®] MOSFET Q1-N-Channel: 30 V, 6.4 A, 26 m** Ω **Q2** - **P-Channel: -30 V, -4.5 A, 51 m** Ω ## **Features** Q1: N-Channel Max rDS(on) = 26 mΩ at VGS = 10 V, ID = 6.4 A Max rDS(on) = 39 mΩ at VGS = 4.5 V, ID = 5.2 A Q2: P-Channel - Max rDS(on) = 51 mΩ at VGS = -10 V, ID = -4.5 A Max rDS(on) = 80 mΩ at VGS = -4.5 V, ID = -3.3 A HBM ESD protection level > 3.5 kV (Note 3) ## **General Description** These dual N- and P-Channel enhancement mode power field effect transistors are produced using ON Semiconductor's advanced PowerTrench[®] process th at has been especially tailored to minimize on-state resistan ce and yet maintain superior switching performance. These devices are well suite d for low voltage and battery powered applications where low in-line power loss and fast switching are required. ## **Application** DC-DC Conversion |Pin 1
**D1**
**D1**
**D2**
**D2**
**S2**
**S1**
**G1**
RoHS Compliant
~~2~~|**G2**|**G2**|**Q1**
**Q2**
**D1**
**D1**
**D2**
**D2**
**1**
**2**
**3**
**4**
**8**
**7**
**6**
**5**
BLU and motor drive inverter
~~oe~~|**Q1**
**Q2**
**D1**
**D1**
**D2**
**D2**
**1**
**2**
**3**
**4**
**8**
**7**
**6**
**5**
BLU and motor drive inverter
~~oe~~|**Q1**
**Q2**
**D1**
**D1**
**D2**
**D2**
**1**
**2**
**3**
**4**
**8**
**7**
**6**
**5**
BLU and motor drive inverter
~~oe~~|**Q1**
**Q2**
**D1**
**D1**
**D2**
**D2**
**1**
**2**
**3**
**4**
**8**
**7**
**6**
**5**
BLU and motor drive inverter
~~oe~~|**S1**
**G1**
**S2**
**G2**|| |---|---|---|---|---|---|---|---|---| |**SO-8**||||||||| |**MOSFET Maximum Ratings **TC= 25 °C unless otherwise noted|= 25 °C unless otherwise noted|||||||| |**Symbol**||**Parameter**||||**Q1**|**Q2**|**Units**| |VDS
Drain to Source Voltage||||||30|-30|V| |VGS
Gate to Source Voltage||||||±20|±25|V| |ID
Drain Current - Continuous
- Pulsed|||TA= 25 °C|||6.4
30|-4.5
-30|A| |Power Dissipation for Dual Operation||||||2.0||| |PD
Power Dissipation for Single Operation|||TA= 25 °C|= 25 °C(Note 1a)||1.6||W| ||||TA= 25 °C|= 25 °C(Note 1b)||0.9||| |EAS
Single Pulse Avalanche Energy||||(Note 4)||18|5|mJ| |TJ, TSTG
Operatingand Storage Junction Temperature Ran|e Junction Temperature Range|||||-55 to +150|-55 to +150|°C| |**Thermal Characteristics**||||||||| |RθJC
Thermal Resistance, Junction to Case
(Note 1)
40
°C/W
RθJA
Thermal Resistance, Junction to Ambient
(Note 1a)
78
~~ee~~||||||||| |**Package Marking and Ordering Information**||||||||| |**Device Marking**
**Device**
FDS8958B
FDS8958B
~~[_~~|||**Package**
**Reel Size**
SO-8
13 ”|||**Tape Width**
**Quantity**
12 mm
2500 units||| ©2008 Semiconductor Components Industries, LLC. Publication Order Number: FDS8958B/D October-2017,Rev.3 **Electrical Characteristics** TJ = 25 °C unless otherwise noted |**Symbol**|**Parameter**|**Test Conditions**|**Test Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**| |---|---|---|---|---|---|---|---|---| |**Off Characteristics**||||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250µA, VGS= 0 V
ID= -250µA, VGS= 0 V||Q1
Q2|30
-30|||V| |∆BVDSS
∆TJ|Breakdown Voltage Temperature
Coefficient|ID= 250µA, referenced to 25 °C
ID= -250µA, referenced to 25 °C||Q1
Q2||24
-21||mV/°C| |IDSS|Zero Gate Voltage Drain Current|VDS= 24 V, VGS= 0 V
VDS= -24 V, VGS= 0 V||Q1
Q2|||1
-1|µA| |IGSS|Gate to Source Leakage Current|VGS= ±20 V, VDS= 0 V
VGS= ±25 V, VDS= 0 V||Q1
Q2|||±100
±10|nA
µA| |**On Characteristics**||||||||| |VGS(th)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250µA
VGS= VDS, ID= -250µA||Q1
Q2|1.0
-1.0|2.0
-1.9|3.0
-3.0|V| |∆VGS(th)
∆TJ|Gate to Source Threshold Voltage
Temperature Coefficient|ID= 250µA, referenced to 25 °C
ID= -250µA, referenced to 25 °C||Q1
Q2||-6
5||mV/°C| |rDS(on)|Static Drain to Source On Resistance|VGS= 10 V, ID= 6.4 A
VGS= 4.5 V, ID= 5.2 A
VGS= 10 V, ID= 6.4A, TJ= 125 °C||Q1||21
29
31|26
39
39|mΩ| |||VGS= -10 V, ID= -4.5 A
VGS= -4.5 V, ID= -3.3 A
VGS= -10 V, ID= -4.5 A, TJ= 125 °C||Q2||38
60
53|51
80
72|| |gFS|Forward Transconductance|VDD= 5 V, ID= 6.4 A
VDD= -5 V, ID= -4.5 A||Q1
Q2||20
10||S| |**Dynamic Characteristics**||||||||| |Ciss|Input Capacitance|Q1
VDS= 15 V, VGS= 0 V, f = 1 MHZ
Q2
VDS= -15 V, VGS= 0 V, f = 1 MHZ||Q1
Q2||405
570|540
760|pF| |Coss|Output Capacitance|||Q1
Q2||75
115|100
155|pF| |Crss|Reverse Transfer Capacitance|||Q1
Q2||55
100|80
150|pF| |Rg|Gate Resistance|||Q1
Q2||2.4
4.4||Ω| |**Switching Characteristics**||||||||| |td(on)|Turn-On Delay Time|Q1
VDD= 15 V, ID= 6.4 A,
VGS= 10 V, RGEN= 6Ω
Q2
VDD= -15 V, ID= -4.5 A,
VGS= -10 V, RGEN= 6Ω||Q1
Q2||4.3
6.0|10
12|ns| |tr|Rise Time|||Q1
Q2||2.0
6.0|10
12|ns| |td(off)|Turn-Off Delay Time|||Q1
Q2||12
17|22
30|ns| |tf|Fall Time|||Q1
Q2||2.0
7.0|10
14|ns| |Qg(TOT)|Total Gate Charge|VGS= 10 V
VGS= -10 V|Q1
VDD= 15 V,
ID= 6.4 A
Q2
VDD= -15 V,
ID= -4.5 A|Q1
Q2||8.3
14|12
19|nC| |Qg(TOT)|Total Gate Charge|VGS= 4.5 V
VGS= -4.5 V||Q1
Q2||4.1
7.0|5.8
9.6|nC| |Qgs|Gate to Source Charge|||Q1
Q2||1.3
1.9||nC| |Qgd|Gate to Drain “Miller” Charge|||Q1
Q2||1.7
3.6||nC| **www.onsemi.com** **2** **==> picture [471 x 176] intentionally omitted <==** **----- Start of picture text -----**
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
Q1 0.8 1.2
VSD Source to Drain Diode Forward Voltage V [V][GS ] GS [= 0 V, I] = 0 V, I [S ] S = -1.3 A [= 1.3 A (Note 2)] (Note 2) Q2 -0.8 -1.2 V
Q1 Q1 17 30
trr Reverse Recovery Time IF = 6.4 A, di/dt = 100 A/µs Q2 20 36 ns
Q2 Q1 6 12
eetiee Qrr Reverse Recovery Charge IF = -4.5 A, di/dt = 100 A/µs Q2 8 16 nC
NOTES:
1. RθJA is determined with the device mounted on a 1 in [2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a) 78 °C/W when b) 135 °C/W when
mounted on a 1 in [2] mounted on a
pad of 2 oz copper minimun pad
**----- End of picture text -----**
2. Pulse Test: Pulse Width < 30 0 µs, Duty cycle < 2.0%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 4. UIL condition: Starting TJ = 25 °C, L = 1 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V . (Q1) Starting TJ = 25 °C, L = 1 mH, IAS = -4 A, VDD = -27 V, VGS = -10 V. (Q2) **www.onsemi.com** **3** ## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted **==> picture [467 x 590] intentionally omitted <==** **----- Start of picture text -----**
30 3.0
VGS = 10 V VGS = 3.5 V
24 VGS = 6 V 2.5 VGS = 4 V
VGS = 4.5 V
18 VGS = 4 V 2.0 VGS = 4.5 V
12 1.5
VGS = 6 V
VGS = 3.5 V
6 1.0
PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s VGS = 10 V
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
0 0.5
0 0.5 1.0 1.5 2.0 2.5 3.0 0 6 12 18 24 30
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.8 75
ID = 6.4 A PULSE DURATION = 80 µ s
1.6 VGS = 10 V DUTY CYCLE = 0.5% MAX
60
1.4
ID = 3.2 A
1.2
45
1.0
TJ = 125 [ o] C
0.8
30
0.6
TJ = 25 [ o] C
0.4 15
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
30 30
PULSE DURATION = 80 µ s VGS = 0 V
25 DUTY CYCLE = 0.5% MAX 10
20 VDS = 5 V TJ = 125 [ o] C
1
15
TJ = 25 [o] C
10 TJ = 125 [o] C 0.1
TJ = 25 [o] C
5
TJ = -55 [ o] C TJ = -55 [o] C
0 0.01
1 2 3 4 5 6 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
NORMALIZED
DRAIN CURRENT (A)
,
ID
DRAIN TO SOURCE ON-RESISTANCE
)
Ω
m
(
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
**Figure 5. Transfer Characteristics** **Figure 6. Source to Drain Diode Forward Voltage vs Source Current** **www.onsemi.com** **4** ## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted **==> picture [470 x 599] intentionally omitted <==** **----- Start of picture text -----**
10 1000
ID = 6.4 A Ciss
8
VDD = 10 V
6
VDD = 15 V 100 Coss
4
VDD = 20 V
Crss
2
f = 1 MHz
VGS = 0 V
0 10
0 2 4 6 8 10 0.1 1 10 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain
to Source Voltage
9 100
8 THIS AREA IS
7 LIMITED BY r
6 DS(on)
5 10 0.1 ms
4
TJ = 25 [o] C 1 ms
3 1
10 ms
2 SINGLE PULSE 100 ms
0.1 TJ = MAX RATED 1 s
TJ = 125 [o] C R θ JA = 135 [o] C/W 10 s
TA = 25 [o] C DC
1 0.01
0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (ms) VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Unclamped Inductive Figure 10. Forward Bias Safe
Switching Capability Operating Area
500
100 VGS = 10 V
SINGLE PULSE
R θ JA = 135 [o] C/W
10 TA = 25 [o] C
1
0.5
10-4 10-3 10-2 10-1 1 10 100 1000
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
, DRAIN CURRENT (A)
ID
, AVALANCHE CURRENT (A)
IAS
, PEAK TRANSIENT POWER (W)
(PK)
P
**----- End of picture text -----**
**www.onsemi.com** **5** **==> picture [469 x 199] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1 0.1
0.05 PDM
0.02
0.01
t1
0.01 t2
SINGLE PULSE NOTES:
R θ JA = 135 [o] C/W DUTY FACTOR: D = tPEAK TJ = PDM x Z θJA 1 x R/t2 θJA + TA
0.001
10-4 10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
ZJA θ
IMPEDANCE,
NORMALIZED THERMAL
**----- End of picture text -----**
**Figure 12. Junction-to-Ambient Transient Thermal Response Curve** **www.onsemi.com** **6** ## **Typical Characteristics (Q2 P-Channel)** TJ = 25 °C unless otherwise noted **==> picture [468 x 602] intentionally omitted <==** **----- Start of picture text -----**
30 4.5
VGS = -10 V VGS = -6 V 4.0 VGS = -3.5 V
24 VGS = -4 V
PULSE DURATION = 80 µ s 3.5 VGS = -4.5 V
DUTY CYCLE = 0.5% MAX
18 3.0 PULSE DURATION = 80 µ s
VGS = -4.5 V 2.5 DUTY CYCLE = 0.5%MAX
12 VGS = -4 V 2.0 VGS = -6 V
1.5
6
VGS = -3.5 V 1.0
VGS = -10 V
0 0.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 6 12 18 24 30
-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)
Figure 15. On- Region Characteristics Figure 16. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6 200
ID = -4.5 A PULSE DURATION = 80 µ s
VGS = -10 V DUTY CYCLE = 0.5% MAX
1.4 160
ID = -2.3 A
1.2 120
1.0 80
TJ = 125 [o] C
0.8 40
TJ = 25 [o] C
0.6 0
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. Normalized On-Resistance Figure 18. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
30 30
PULSE DURATION = 80 µ s VGS = 0 V
DUTY CYCLE = 0.5% MAX 10
25
VDS = -5 VDS = -5 V= -5 V TJ = -55 J = -55 = -55 [[o]] C TJ = 25 J = 25 = 25 [[o]] C
20
TJ = 125 [o] C
TJ = 125J = 125 = 125 [[ o]] C
15
TJ = 25 [o] C
10
0.1
5
TJ = -55 [o] C
0 0.01
1 2 3 4 5 6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
-VGS, GATE TO SOURCE VOLTAGE (V)GS, GATE TO SOURCE VOLTAGE (V), GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)
DRAIN CURRENT (A), NORMALIZED
D
-I
DRAIN TO SOURCE ON-RESISTANCE
)
Ω
m
(
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
D
-I
, REVERSE DRAIN CURRENT (A)
S
-I
**----- End of picture text -----**
**==> picture [204 x 173] intentionally omitted <==** **----- Start of picture text -----**
30
PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
25
VDS = -5 VDS = -5 V= -5 V TJ = -55 J = -55 = -55 [[o]] C TJ = 25 J = 25 = 25 [[o]] C
20
TJ = 125J = 125 = 125 [[ o]] C
15
10
5
0
1 2 3 4 5 6
-VGS, GATE TO SOURCE VOLTAGE (V)GS, GATE TO SOURCE VOLTAGE (V), GATE TO SOURCE VOLTAGE (V)
Figure 19. Transfer Characteristics
, DRAIN CURRENT (A)
D
-I
**----- End of picture text -----**
**Figure 20. Source to Drain Diode Forward Voltage vs Source Current** **www.onsemi.com** **7** ## **Typical Characteristics (Q2 P-Channel)** TJ = 25 °C unless otherwise noted **==> picture [467 x 581] intentionally omitted <==** **----- Start of picture text -----**
10 2000
ID = -4.5 A
1000
8 Ciss
VDD = -10 V
6
VDD = -15 V
4 Coss
VDD = -20 V
100
2 Crss
f = 1 MHz
VGS = 0 V
0 30
0 3 6 9 12 15 0.1 1 10 30
Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 21. Gate Charge Characteristics Figure 22. Capacitance vs Drain
to Source Voltage
8 10-2
7
6 10-3 VGS = 0V
5
10-4
4
TJ = 25 [o] C 10-5
3 TJ = 125 [o] C
10-6
2 10-7
TJ = 125 [o] C
10-8 TJ = 25 [o] C
1 10-9
0.01 0.1 1 10 0 5 10 15 20 25 30 35
tAV, TIME IN AVALANCHE (ms) -VGS, GATE TO SOURCE VOLTAGE(V)
Figure 23. Unclamped Inductive
Figure 24. Ig vs Vgs
Switching Capability
100 200
THIS AREA IS 100 VGS = -10 V
LIMITED BY r
DS(on)
10
0.1 ms SINGLE PULSE
R θ JA = 135 [o] C/W
1 ms
1 10 TA = 25 [o] C
10 ms
SINGLE PULSE 100 ms
0.1 TJ = MAX RATED 1 s
R θ JA = 135 [o] C/W 10 s
TA = 25 [o] C DC 1
0.01 0.5
0.01 0.1 1 10 100 10-4 10-3 10-2 10-1 1 10 100 1000
-VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
-V
, AVALANCHE CURRENT (A) GATE LEAKAGE CURRENT(A)
-IAS -Ig,
, DRAIN CURRENT (A)
D
-I
PEAK TRANSIENT POWER (W)
P)(PK,
**----- End of picture text -----**
**Figure 25. Forward Bias Safe Operating Area** **Figure 26. Single Pulse Maximum Power Dissipation** **www.onsemi.com** **8** **==> picture [469 x 198] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
2
1 DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.1 0.05 PDM
0.02
0.01
t1
t2
0.01 SINGLE PULSE NOTES:
R θ JA = 135 [o] C/W DUTY FACTOR: D = tPEAK TJ = PDM x Z θJA 1 x R/t2 θJA + TA
0.002
10-4 10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
Z JA θ
IMPEDANCE,
NORMALIZED THERMAL
**----- End of picture text -----**
**Figure 27. Junction-to-Ambient Transient Thermal Response Curve** **www.onsemi.com** **9** **==> picture [438 x 442] intentionally omitted <==** **----- Start of picture text -----**
Physical Dimensions
0.65
4.90±0.10 A
(0.635)
8 5
B
1.75
6.00±0.20
3. 90±0.10 5.60
PIN ONE 1 4
INDICATOR
1.27
1.27
0.25 C B A LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.175±0.75
0.22±0.30
1.75 MAX C
0.10
0.42±0.09 OPTION A - BEVEL EDGE
(0.86) x 45°
R0.10 GAGE PLANE
R0.10 OPTION B - NO BEVEL EDGE
0.36
8° NOTES: UNLESS OTHERWISE SPECIFIED
0° A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
SEATING PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.
0.65±0.25
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
(1.04) D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
DETAIL A E) DRAWING FILENAME: M08Arev15
SCALE: 2:1 F) FAIRCHILD SEMICONDUCTOR.
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