# Power MOSFET, N Channel, 30 V, 15 A, 6000 µohm, SOIC, Surface Mount

![Product image](https://novapart.co/image/farnell:2322618/)

**URL**: https://novapart.co/products/FDS8896/power-mosfet-n-channel-30-v-15-a-6000-ohm-soic
**SKU**: FDS8896
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2880
**Stock**: 1000+
**Lead Time**: 141 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:15A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.0049ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.2V; Pow

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 2.5W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 15A |
| Drain Source On State Resistance | 6000µohm |
| Gate Source Threshold Voltage Max | 1.2V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2322618/)

## **Is Now Part of** 

**To learn more about ON Semiconductor, please visit our website at www.onsemi.com** 

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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ee<br>FAIRCHILD<br>eee April 2007<br>FDS8896 tm<br>N-Channel PowerTrench [® ] MOSFET<br>30V, 15A, 6.0m Ω<br>Features General  Description<br>| rDS(on) = 6.0mΩ, VGS = 10V, ID = 15A This N-Channel MOSFET has been designed specifically to<br>improve the overall efficiency of DC/DC converters using<br>| rDS(on) = 7.3mΩ, VGS = 4.5V, ID = 14A either synchronous or conventional switching PWM<br>controllers.  It has been optimized for low gate charge, low<br>| High performance trench technology for extremely low  rDS(on) and fast switching speed.<br>rDS(on)<br>| Low gate charge Applications<br>i | DC/DC converters<br>| High power and current handling capability<br>RoHS Compliant<br>Branding Dash<br>5 4<br>5 6 3<br>1 7 2<br>2 M | p a f fe) F7<br>3<br>4 a 8 | |7 1<br>SO-8<br>FDS8896 N-Channel PowerTrench<br>®<br>MOSFET<br>**----- End of picture text -----**<br>


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©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**MOSFET Maximum Ratings** TA = 25°C unless otherwise noted 

|**MOSFET**|**Maximum Ratings  **TA= 25°C unless otherwise noted|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Ratings**|**Units**|
|VDSS|Drain to Source Voltage|30|V|
|VGS|Gate to Source Voltage|±20|V|
|ID|Drain Current<br>Continuous(TA= 25oC, VGS= 10V, RθJA= 50oC/W)|15|A|
||Continuous(TA= 25oC, VGS= 4.5V, RθJA= 50oC/W)|14|A|
||Pulsed|110|A|
|EAS|Single Pulse Avalanche Energy (Note 1)|196|mJ|
|PD|Power dissipation|2.5|W|
||Derate above 25oC|20|mW/oC|
|TJ, TSTG|Operating and Storage Temperature|-55 to 150|oC|
|**Thermal**|**Characteristics**|||
|RθJC|Thermal Resistance, Junction to Case (Note 2)|25|oC/W|
|RθJA|Thermal Resistance, Junction to Ambient(Note 2a)|50|oC/W|
|RθJA|Thermal Resistance, Junction to Ambient (Note 2b)|125|oC/W|



## **Package Marking and Ordering Information** 

|**Device Marking**|**Device Marking**|**Device**|**Package**|**Package**|**Reel Size**|**Reel Size**|**Tape Width**|**Tape Width**|**Quantity**|**Quantity**|
|---|---|---|---|---|---|---|---|---|---|---|
|FDS8896||FDS8896|SO-8||330mm||12mm||2500 units||
|**Electrical Characteristics**TJ= 25°C unless otherwise noted|||||||||||
|**Symbol**|**Parameter**|||**Test Conditions**|||**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**|||||||||||
|BVDSS|Drain to Source Breakdown Voltage|||ID= 250µA, VGS||= 0V|30|-|-|V|
|IDSS|Zero Gate Voltage Drain Current|||VDS= 24V<br>VGS= 0V|||-|-|1|µA|
|||||||TJ= 150oC|-|-|250||
|IGSS|Gate to Source Leakage Current|||VGS= ±20V|||-|-|±100|nA|
|**On Characteristics**|||||||||||
|VGS(TH)|Gate to Source Threshold Voltage|||VGS= VDS, ID= 250µA|||1.2|-|2.5|V|
|rDS(on)|Drain to Source On Resistance|||ID= 15A, VGS= 10V|||-|4.9|6.0|mΩ|
|||||ID= 14A, VGS= 4.5V|||-|5.8|7.3||
|||||ID= 15A, VGS= 10V,<br>TJ= 150oC|||-|7.8|10.1||
|**Dynamic Characteristics**|||||||||||
|CISS|Input Capacitance|||VDS= 15V, VGS= 0V,<br>f = 1MHz|||-|2525|-|pF|
|COSS|Output Capacitance||||||-|490|-|pF|
|CRSS|Reverse Transfer Capacitance||||||-|300|-|pF|
|RG|Gate Resistance|||VGS= 0.5V, f = 1MHz|||0.6|2.4|4.2|Ω|
|Qg(TOT)|Total Gate Charge at 10V|||VGS= 0V to 10V|||-|50|67|nC|
|Qg(5)|Total Gate Charge at 5V|||VGS= 0V to 5V|||-|28|36|nC|
|Qg(TH)|Threshold Gate Charge|||VGS= 0V to 1V|||-|2.5|3.2|nC|
|Qgs|Gate to Source Gate Charge||||||-|7.0|-|nC|
|Qgs2|Gate Charge Threshold to Plateau||||||-|4.5|-|nC|
|Qgd|Gate to Drain “Miller” Charge||||||-|11|-|nC|



©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**2** 

|**Switching Characteristics**(VGS= 10V)|**Switching Characteristics**(VGS= 10V)||||||
|---|---|---|---|---|---|---|
|tON|Turn-On Time|VDD= 15V, ID= 14A<br>VGS= 10V, RGS= 6.2Ω|-|-|68|ns|
|td(ON)|Turn-On DelayTime||-|8|-|ns|
|tr|Rise Time||-|37|-|ns|
|td(OFF)|Turn-Off DelayTime||-|60|-|ns|
|tf|Fall Time||-|24|-|ns|
|tOFF|Turn-Off Time||-|-|126|ns|
|**Drain-Source Diode Characteristics**|||||||
|VSD|Source to Drain Diode Voltage|ISD= 15A|-|-|1.25|V|
|||ISD= 2.1A|-|-|1.0|V|
|trr|Reverse Recovery Time|ISD= 15A, dISD/dt = 100A/µs|-|-|29|ns|
|QRR|Reverse Recovered Charge|ISD= 15A, dISD/dt = 100A/µs|-|-|15|nC|



## **Notes:** 

- **1:** Starting TJ = 25°C, L = 1mH, IAS = 19.8A, VDD = 30V, VGS = 10V. 

- **2:** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.  RθJC is guaranteed by design while RθJA  is determined by the user’s board design. 

- a) 50°C/W when mounted on a 1in[2  ] pad of 2 oz copper. 

- b) 125°C/W when mounted on a minimum pad. 

©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**3** 

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**----- Start of picture text -----**<br>
Typical Characteristics  TJ = 25°C unless otherwise noted<br>1.2 20<br>1.0<br>15<br>0.8<br>VGS = 4.5V V GS  = 10V<br>0.6 10<br>0.4<br>5<br>0.2<br>R θ JA =50 [o] C/W<br>0 0<br>0 25 50 75 100 125 150 25 50 75 100 125 150<br>TA, AMBIENT TEMPERATURE ( [o] C) TA, AMBIENT TEMPERATURE ( [o] C)<br>Figure 1.  Normalized Power Dissipation vs  Figure 2.  Maximum Continuous Drain Current vs<br>Ambient Temperature Ambient Temperature<br>2<br>1 DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>      0.1<br>0.1<br>      0.05<br>      0.02<br>      0.01<br>0.01<br>SINGLE PULSE<br>0.001 R θ JA = 125 [o] C/W<br>0.0005<br>10-4 10-3 10-2 10-1 100 101 102 103<br>t, RECTANGULAR PULSE DURATION (s)<br>, DRAIN CURRENT (A)<br>ID<br>POWER DISSIPATION MULTIPLIER<br>ZJA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 3.  Normalized Maximum Transient Thermal Impedance** 

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2000<br>1000 VGS = 10V SINGLE PULSE<br>R θ JA = 125 [o] C/W<br>TA = 25 [o] C<br>100<br>10<br>1<br>0.5<br>10-4 10-3 10-2 10-1 100 101 102 103<br>t, PULSE WIDTH (s)<br>Figure 4.  Single Pulse Maximum Power Dissipation<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**4** 

## **Typical Characteristics** TJ = 25°C unless otherwise noted 

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**----- Start of picture text -----**<br>
100 50<br>tIf R = 0If RtAVAV = (L)(I =  ≠  0(L/RAS)ln)/(1.3[(IAS ** RRATED BV)/(1.3 * RATED BVDSS - VDDDSS)  - VDD) +1] 40 PULSE DURATION = 80DUTY CYCLE = 0.5%MAX µ s<br>VDS = 5V<br>30<br>STARTING TJ = 25 [o] C<br>10<br>20<br>TJ = 150 [o] C TJ = 25 [o] C<br>STARTING TJ = 150 [o] C 10<br>TJ = -55 [o] C<br>1 0<br>1.5 2.0 2.5 3.0 3.5<br>0.1 1 10 100<br>tAV, TIME IN AVALANCHE (ms) VGS, GATE TO SOURCE VOLTAGE (V)<br>NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6.  Transfer Characteristics<br>Figure 5.  Unclamped Inductive Switching Unclamped Inductive Switching<br>Capability<br>50 14<br>VGS = 10V VGS = 5V PULSE DURATION = 80 µ s<br>ID = 15A DUTY CYCLE = 0.5% MAX<br>40 VGS = 4V 12<br>30 10<br>VGS = 3V<br>20 8<br> TA = 25 [o] C<br>10 PULSE DURATION = 80 µ s 6<br>DUTY CYCLE = 0.5% MAX<br>VGS = 2.5V<br>0 4<br>0 0.1 0.2 0.3 0.4 0.5 2 4 6 8 10<br>VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 7.  Saturation Characteristics Figure 8.  Drain to Source On Resistance vs Gate<br>Voltage and Drain Current<br>1.6 1.2<br>PULSE DURATION = 80 µ s VGS = VDS, ID = 250 µ A<br>DUTY CYCLE = 0.5% MAX<br>1.4<br>1.0<br>1.2<br>1.0<br>0.8<br>0.8<br>VGS = 10V, ID = 15A<br>0.6 0.6<br>-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160<br>TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)<br>Figure 9.  Normalized Drain to Source On  Figure 10.  Normalized Gate Threshold Voltage vs<br>Resistance vs Junction Temperature Junction Temperature<br>, AVALANCHE CURRENT (A) , DRAIN CURRENT (A)<br>IAS ID<br>) Ω<br>, DRAIN CURRENT (A)ID , DRAIN TO SOURCE ON RESISTANCE (m<br>rDS(on)<br>ON RESISTANCE<br>NORMALIZED GATE<br>THRESHOLD VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 **Figure 5.  Unclamped Inductive Switching Unclamped Inductive Switching Capability** 

©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**5** 

## **Typical Characteristics** TJ = 25°C unless otherwise noted 

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1.10 5000<br>ID = 250 µ A C ISS  =  C GS  + C GD<br>C OSS  ≅  C DS  + C GD<br>1.05<br>1000<br>1.00<br>C RSS  =  C GD<br>0.95<br>VGS = 0V, f = 1MHz<br>0.90 100<br>-80 -40 0 40 80 120 160<br>0.1 1 10 30<br>TJ, JUNCTION TEMPERATURE ( [o] C) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 11.  Normalized Drain to Source  Figure 12.  Capacitance vs Drain to Source<br>Breakdown Voltage vs Junction Temperature Voltage<br>10 200<br>VDD = 15V 100<br>100us<br>8<br>10<br>1ms<br>6<br>10ms<br>1 THIS AREA IS<br>4 LIMITED BY rDS(on) 100ms<br>SINGLE PULSE 1s<br>2 WAVEFORMS INDESCENDING ORDER: 0.1 TRJ θ JA= MAX RATED= 125 [o] C/W 10s<br>IIDD = 15A = 1A 0.01 TA = 25 [o] C DC<br>0 0.01 0.1 1 10 100<br>0 10 20 30 40 50<br>VDS, DRAIN to SOURCE VOLTAGE (V)<br>Qg, GATE CHARGE (nC)<br>Figure 13.  Gate Charge Waveforms for Constant  Figure 14.  Forward Bias Safe Operating Area<br>Gate Currents<br>BREAKDOWN VOLTAGE C, CAPACITANCE (pF)<br>NORMALIZED DRAIN TO SOURCE<br>, DRAIN CURRENT (A)<br>D<br> I<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**6** 

## **Test Circuits and Waveforms** 

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VDS BVDSS<br>tP<br>L VDS<br>IAS<br>VARY tP TO OBTAIN + VDD<br>REQUIRED PEAK IAS RG VDD<br>VGS -<br>DUT<br>tP<br>0V IAS 0<br>0.01 Ω<br>tAV<br>Figure 15.  Unclamped Energy Test Circuit Figure 16.  Unclamped Energy Waveforms<br>VDS<br>VDD Qg(TOT)<br>VDS VGS<br>L<br>VGS = 10V<br>Qg(5)<br>VGS + VDD Qgs2 VGS = 5V<br>-<br>DUT VGS = 1V<br>Ig(REF) 0<br>Qg(TH)<br>Qgs Qgd<br>Ig(REF)<br>0<br>Figure 17.  Gate Charge Test Circuit Figure 18.  Gate Charge Waveforms<br>VDS tON tOFF<br>td(ON) td(OFF)<br>RL tr tf<br>VDS<br>90% 90%<br>+<br>VGS<br>VDD 10% 10%<br>- 0<br>DUT 90%<br>RGS<br>VGS 50% 50%<br>PULSE WIDTH<br>VGS 0 10%<br>Figure 19.  Switching Time Test Circuit Figure 20.  Switching Time Waveforms<br>**----- End of picture text -----**<br>


©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**7** 

## _**Thermal Resistance vs. Mounting Pad Area**_ 

The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance RθJA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. 

**==> picture [189 x 22] intentionally omitted <==**

In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 

1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 

2. The number of copper layers and the thickness of the board. 

3. The use of external heat sinks. 

thermal impedance curve. 

Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2.  The area, in square inches is the top copper area including the gate and source pads. 

**==> picture [190 x 18] intentionally omitted <==**

The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. 

Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 

4. The use of thermal vias. 

5. Air flow and board orientation. 

6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. 

Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient 

**==> picture [191 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
200<br>R θ JA = 64 + 26/(0.23+Area)<br>150<br>100<br>50<br>0.001 0.01 0.1 1 10<br>AREA, TOP COPPER AREA (in [2] )<br>Figure 21.  Thermal Resistance vs Mounting<br>Pad Area<br>oC/W)( RJA  θ<br>**----- End of picture text -----**<br>


**==> picture [408 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
150<br>COPPER BOARD AREA - DESCENDING ORDER<br>0.04 in [2]<br>120 0.28 in [2]<br>0.52 in [2]<br>0.76 in [2]<br>90 1.00 in [2]<br>60<br>30<br>0<br>10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, RECTANGULAR PULSE DURATION (s)<br>Figure 22.  Thermal Impedance vs Mounting Pad Area<br>oC/W)<br>, THERMAL<br>ZJA θ<br>IMPEDANCE (<br>**----- End of picture text -----**<br>


©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**8** 

## _**PSPICE Electrical Model**_ 

.SUBCKT FDS8896 2 1 3 ;  rev February 2004 Ca 12 8 1.8e-9 Cb 15 14 1.8e-9 Cin 6 8 2.2e-9 

Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD 

**==> picture [319 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
LDRAIN<br>DPLCAP 5 DRAIN<br>2<br>10<br>RLDRAIN<br>RSLC1<br>51 DBREAK<br>RSLC2<br>515 ESLC 11<br>ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY<br>LGATE EVTEMP + 198 - 21 MWEAK<br>GATE RGATE + 18 - 6<br>1 9 20 22 MMED<br>RLGATE MSTRO<br>LSOURCE<br>CIN 8 7 SOURCE3<br>RSOURCE<br>RLSOURCE<br>S1A S2A<br>12 13 14 15 17 RBREAK 18<br>8 13<br>S1B S2B RVTEMP<br>CA 13+ CB+ 14 IT -19<br>EGS 68 EDS 58 + VBAT<br>- - 8<br>22<br>RVTHRES<br>+<br>-<br>**----- End of picture text -----**<br>


Ebreak 11 7 17 18 33.1 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 

It 8 17 1 

Lgate 1 9 1.5e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1e-9 

RLgate 1 9 15 RLdrain 2 5 10 RLsource 3 7 10 

Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD 

Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.52e-3 Rgate 9 20 2.4 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 

Vbat 22 19 DC 1 

ESLC 51 50  VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} 

.MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7 + CJO=8.8e-10 M=0.57 TT=1e-12 XTI=2.2) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=9e-10 IS=1e-30 N=10 M=0.39) 

.MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.4) .MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.63 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=24 RS=0.1) 

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-1e-6) .MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=7e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-1.3e-3 TC2=-7e-6) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7) 

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2) 

.ENDS 

Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 

©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**9** 

## _**SABER Electrical Model**_ 

REV February 2004 template FDS8896 n2,n1,n3 electrical n2,n1,n3 { var i iscl 

dp..model dbodymod =  (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-12,xti=2.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) 

dp..model dplcapmod =  (cjo=9e-10,isl=10e-30,nl=10,m=0.39) 

m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1) 

m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1) 

m..model mweakmod = (type=_n,vto=1.63,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod =  (ron=1e-5,roff=0.1,von=-4,voff=-3) sw_vcsp..model s1bmod =  (ron=1e-5,roff=0.1,von=-3,voff=-4) sw_vcsp..model s2amod =  (ron=1e-5,roff=0.1,von=-2,voff=-0.5) **10** sw_vcsp..model s2bmod =  (ron=1e-5,roff=0.1,von=-0.5,voff=-2) c.ca n12 n8 = 1.8e-9 c.cb n15 n14 = 1.8e-9 **RSLC2** c.cin n6 n8 = 2.2e-9 

**==> picture [432 x 258] intentionally omitted <==**

**----- Start of picture text -----**<br>
LDRAIN<br>sw_vcsp..model s1bmod =  (ron=1e-5,roff=0.1,von=-3,voff=-4) DPLCAP 5 DRAIN<br>sw_vcsp..model s2amod =  (ron=1e-5,roff=0.1,von=-2,voff=-0.5) 10 2<br>sw_vcsp..model s2bmod =  (ron=1e-5,roff=0.1,von=-0.5,voff=-2) RLDRAIN<br>c.ca n12 n8 = 1.8e-9 RSLC1<br>c.cb n15 n14 = 1.8e-9 RSLC2 51<br>c.cin n6 n8 = 2.2e-9<br>ISCL<br>dp.dbody n7 n5 = model=dbodymoddp.dbreak n5 n11 = model=dbreakmod - 6 RDRAIN50 DBREAK<br>dp.dplcap n10 n5 = model=dplcapmod ESG + 8 EVTHRES 16 11 DBODY<br>spe.ebreak n11 n7 n17 n18 = 33.1 LGATE EVTEMP + 198 - 21 MWEAK<br>spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1 GATE1 9RGATE20+ 1822 - 6 MMED EBREAK+<br>spe.esg n6 n10 n6 n8 = 1 RLGATE MSTRO 17<br>spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 CIN 8 -18 7 LSOURCE SOURCE3<br>i.it n8 n17 = 1 RSOURCE RLSOURCE<br>S1A S2A<br>l.lgate n1 n9 = 1.5e-9l.ldrain n2 n5 = 1.0e-9 12 138 1413 15 17 RBREAK 18<br>l.lsource n3 n7 = 1e-9<br>S1B S2B RVTEMP<br>res.rlgate n1 n9 = 15res.rldrain n2 n5 = 10res.rlsource n3 n7 = 10 CA EGS13+68 EDSCB+ 58 14 IT +-19VBAT<br>- - 8<br>m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u 22<br>RVTHRES<br>**----- End of picture text -----**<br>


m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 

res.rbreak n17 n18  = 1, tc1=8.3e-4,tc2=-1e-6 res.rdrain n50 n16  = 2.52e-3, tc1=1e-4,tc2=8e-6 res.rgate n9 n20 = 2.4 res.rslc1 n5 n51  = 1e-6, tc1=9e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7  = 2e-3, tc1=7e-3,tc2=1e-6 res.rvthres n22 n8  = 1, tc1=-1.3e-3,tc2=-7e-6 res.rvtemp n18 n19  = 1, tc1=-2.6e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod 

v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) 

} } 

©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**10** 

## _**SPICE Thermal Model**_ 

**==> picture [399 x 428] intentionally omitted <==**

**----- Start of picture text -----**<br>
th JUNCTION<br>REV February 2004<br>FDS8896T<br>Copper Area =1.0 in [2]<br>CTHERM1 TH 8 2.0e-3<br>CTHERM2 8 7 5.0e-3 RTHERM1 CTHERM1<br>CTHERM3 7 6 1.0e-2<br>CTHERM4 6 5 4.0e-2<br>CTHERM5 5 4 9.0e-2 8<br>CTHERM6 4 3 2e-1<br>CTHERM7 3 2 1<br>CTHERM8 2 TL 3 RTHERM2 CTHERM2<br>RTHERM1 TH 8 1e-1<br>7<br>RTHERM2 8 7 5e-1<br>RTHERM3 7 6 1<br>RTHERM4 6 5 5 RTHERM3 CTHERM3<br>RTHERM5 5 4 8<br>RTHERM6 4 3 12<br>RTHERM7 3 2 18 6<br>RTHERM8 2 TL 25<br>SABER Thermal Model RTHERM4 CTHERM4<br>Copper Area = 1.0 in [2] 5<br>template thermal_model th tl<br>thermal_c th, tl<br>{ RTHERM5 CTHERM5<br>ctherm.ctherm1 th 8 =2.0e-3<br>ctherm.ctherm2 8 7 =5.0e-3<br>ctherm.ctherm3 7 6 =1.0e-2 4<br>ctherm.ctherm4 6 5 =4.0e-2<br>ctherm.ctherm5 5 4 =9.0e-2<br>ctherm.ctherm6 4 3 =2e-1 RTHERM6 CTHERM6<br>ctherm.ctherm7 3 2 1<br>ctherm.ctherm8 2 tl 3<br>3<br>rtherm.rtherm1 th 8 =1e-1<br>rtherm.rtherm2 8 7 =5e-1<br>rtherm.rtherm3 7 6 =1 RTHERM7 CTHERM7<br>rtherm.rtherm4 6 5 =5<br>rtherm.rtherm5 5 4 =8 2<br>rtherm.rtherm6 4 3 =12<br>rtherm.rtherm7 3 2 =18<br>rtherm.rtherm8 2 tl  =25 RTHERM8 CTHERM8<br>}<br>tl CASE<br>**----- End of picture text -----**<br>


|**TABLE 1. THERMAL MODELS**|**TABLE 1. THERMAL MODELS**|**TABLE 1. THERMAL MODELS**|**TABLE 1. THERMAL MODELS**|**TABLE 1. THERMAL MODELS**|**TABLE 1. THERMAL MODELS**|
|---|---|---|---|---|---|
|**COMPONANT**|**0.04 in2**|**0.28 in2**|**0.52 in2**|**0.76 in2**|**1.0 in2**|
|CTHERM6|1.2e-1|1.5e-1|2.0e-1|2.0e-1|2.0e-1|
|CTHERM7|0.5|1.0|1.0|1.0|1.0|
|CTHERM8|1.3|2.8|3.0|3.0|3.0|
|RTHERM6|26|20|15|13|12|
|RTHERM7|39|24|21|19|18|
|RTHERM8|55|38.7|31.3|29.7|25|



©2007 Fairchild Semiconductor Corporation FDS8896 Rev. B 

www.fairchildsemi.com 

**11** 

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## **TRADEMARKS** 

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx[®] _i-Lo_ ™ Power-SPM™ 

|ACEx®<br>Across the board. Around the world™<br>ActiveArray™<br>Bottomless™<br>Build it Now™<br>CoolFET™<br>_CROSSVOLT_™<br>CTL™<br>Current Transfer Logic™<br>DOME™<br>E2CMOS™<br>EcoSPARK®<br>EnSigna™<br>FACT Quiet Series™<br>FACT®<br>FAST®<br>FASTr™<br>FPS™<br>FRFET®<br>GlobalOptoisolator**™**|_i-Lo_™<br>ImpliedDisconnect™<br>IntelliMAX™<br>ISOPLANAR™<br>MICROCOUPLER™<br>MicroPak™<br>MICROWIRE™<br>Motion-SPM™<br>MSX™<br>MSXPro™<br>OCX™<br>OCXPro™<br>OPTOLOGIC®<br>OPTOPLANAR®<br>PACMAN™<br>PDP-SPM™<br>POP™<br>Power220®<br>Power247®<br>PowerEdge™|Power-SPM™<br>PowerTrench®<br>Programmable Active Droop™<br>QFET®<br>QS™<br>QT Optoelectronics™<br>Quiet Series™<br>RapidConfigure™<br>RapidConnect™<br>ScalarPump™<br>SMART START™<br>SPM®<br>STEALTH™<br>SuperFET™<br>SuperSOT™-3<br>SuperSOT™-6<br>SuperSOT™-8<br>SyncFET™<br>TCM™<br>The Power Franchise®|TinyBoost™<br>TinyBuck™<br>TinyLogic®<br>TINYOPTO™<br>TinyPower™<br>TinyWire™<br>TruTranslation™<br>µSerDes™<br>UHC®<br>UniFET™<br>VCX™<br>Wire™|
|---|---|---|---|
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## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|<br>**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product  Status**|**Definition**|
|Advance Information|Formative or In Design|This datasheet contains the design specifications for product<br>development. Specifications may change in any manner<br>without notice.|
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