# Power MOSFET, N Channel, 30 V, 8.4 A, 0.022 ohm, SOIC, Surface Mount

![Product image](https://novapart.co/image/farnell:1467983/)

**URL**: https://novapart.co/products/FDS6612A/power-mosfet-n-channel-30-v-84-a-0022-ohm-soic
**SKU**: FDS6612A
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2670
**Stock**: 1000+
**Lead Time**: 2 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:8.4A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.019ohm; Rds(on) T; Available until stocks are exhausted Alternative available

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (23-Jan-2024) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 2.5W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | SOIC |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 8.4A |
| Drain Source On State Resistance | 0.022ohm |
| Gate Source Threshold Voltage Max | 1.9V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1467983/)

## **Is Now Part of** 

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## **FDS6612A** 

## **Single N-Channel, Logic-Level, PowerTrench[] MOSFET** 

**April 2007** tm 

**==> picture [423 x 495] intentionally omitted <==**

**----- Start of picture text -----**<br>
General Description  Features<br>This N-Channel Logic Level MOSFET is produced  • 8.4 A, 30 V.  RDS(ON)  = 22 mΩ @ VGS = 10 V<br>using  Fairchild  Semiconductor’s  advanced<br>PowerTrench process that has been especially tailored  RDS(ON)  = 30 mΩ @ VGS = 4.5 V<br>to minimize the on-state resistance and yet maintain<br>superior switching performance.  • Fast switching speed<br>These devices are well suited for low voltage and  • Low gate charge<br>battery powered applications where low in-line power<br>loss and fast switching are required.  • High performance trench technology for extremely<br>low RDS(ON)<br>• High power and current handling capability<br>D 5 4<br>DD [D]<br>DD<br>6 3<br>DD<br>7 2<br>SO-8 G<br>G 8 1<br>S<br>S [S]<br>Pin 1 Da SO-8 SS [S]<br>Absolute Maximum Ratings TA=25 [o] C unless otherwise noted<br>Symbol Parameter  Ratings  Units<br>VDSS Drain-Source Voltage   30  V<br>VGSS Gate-Source Voltage  ±20  V<br>ID Drain Current – Continuous  (Note 1a) 8.4  A<br>– Pulsed  40<br>PD Power Dissipation for Single Operation  (Note 1a) 2.5  W<br>(Note 1b) 1.0<br>EAS  Single Pulse Avalanche Energy (Note 3) 24  mJ<br>TJ, TSTG Operating and Storage Junction Temperature Range  –55 to +150  °C<br>Thermal Characteristics<br>RθJA Thermal Resistance, Junction-to-Ambient   (Note 1a)  50  °C/W<br>RθJA Thermal Resistance, Junction-to-Ambient  (Note 1b)  125<br>———=_—— RθJC Thermal Resistance, Junction-to-Case  (Note 1)  25<br>Package Marking and Ordering Information<br>Device Marking  Device  Reel Size  Tape width  Quantity<br>FDS6612A  FDS6612A  13’’  12mm   2500 units<br>ee<br>**----- End of picture text -----**<br>


2007 Fairchild Semiconductor Corporation 

FDS6612A  Rev D1 (W) 

|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>**Off Characteristics**<br>BVDSS<br>Drain–Source Breakdown Voltage<br>VGS= 0 V,<br>ID= 250µA<br>30<br>V<br>∆BVDSS<br>∆TJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250µA, Referenced to 25°C<br>26<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 24 V,<br>VGS= 0 V<br>1<br>µA<br>VDS= 24 V, VGS= 0 V, TJ=55°C<br>10<br>µA<br>IGSS<br>Gate–BodyLeakage<br>VGS=±20 V,<br>VDS= 0 V<br>±100<br>nA<br>**On Characteristics**<br>**(Note 2)**<br>VGS(th)<br>Gate Threshold Voltage<br>VDS= VGS,<br>ID= 250µA<br>1<br>1.9<br>3<br>V<br>∆VGS(th)<br> <br>∆TJ<br>Gate Threshold Voltage<br>Temperature Coefficient<br>ID= 250µA, Referenced to 25°C<br>–4.4<br>mV/°C<br>RDS(on)<br>Static Drain–Source<br>On–Resistance<br>VGS= 10 V,<br>ID= 8.4 A<br>VGS= 4.5 V,<br>ID= 7.2 A<br>VGS= 10 V, ID= 8.4 A, TJ=125°C<br>19<br>24<br>25<br>22<br>30<br>37<br>mΩ<br>ID(on)<br>On–State Drain Current<br>VGS= 10 V,<br>VDS= 5 V<br>20<br>A<br>gFS<br>Forward Transconductance<br>VDS= 15 V,<br>ID= 8.4 A<br>30<br>S<br>**Dynamic Characteristics**<br>Ciss<br>Input Capacitance<br>560<br>pF<br>Coss<br>Output Capacitance<br>140<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>VDS= 15 V,<br>VGS= 0 V,<br>f = 1.0 MHz<br>55<br>pF<br>RG<br>Gate Resistance<br>VGS= 15 mV,  f = 1.0 MHz<br>2.5<br>Ω<br>**Switching Characteristics(Note 2)**<br>td(on)<br>Turn–On DelayTime<br>7<br>14<br>ns<br>tr<br>Turn–On Rise Time<br>5<br>10<br>ns<br>td(off)<br>Turn–Off DelayTime<br>22<br>35<br>ns<br>tf<br>Turn–Off Fall Time<br>VDD= 15 V,<br>ID= 1 A,<br>VGS= 10 V,<br>RGEN= 6Ω<br>3<br>6<br>ns<br>Qg<br>Total Gate Charge<br>5.4<br>7.6<br>nC<br>Qgs<br>Gate–Source Charge<br>1.7<br>nC<br>Qgd<br>Gate–Drain Charge<br>VDS= 15 V,<br>ID= 8.4 A,<br>VGS= 5 V<br>1.9<br>nC<br>**Drain–Source Diode Characteristics and Maximum Ratings**<br>~~eee~~<br>~~—~~<br>~~=~~<br>~~SS~~<br>~~EEE~~|
|---|
|IS<br>Maximum Continuous Drain–Source Diode Forward Current<br>2.1<br>A<br>VSD<br>Drain–Source Diode Forward<br>Voltage<br>VGS= 0 V,<br>IS= 2.1 A(Note 2)<br>0.77<br>1.2<br>V<br>trr<br>Diode Reverse Recovery Time<br>19<br>nS<br>Qrr<br>Diode Reverse Recovery Charge<br>IF= 8.4 A, diF/dt= 100 A/µs<br>9<br>nC<br>~~a~~|
|**Notes:**|
|**1.**RθJAis the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of|
|the drain pins.  RθJCis guaranteed by design while RθCAis determined by the user's board design.|



a) 50°C/W when mounted on a 1in[2] pad of 2 oz copper 

b) 125°C/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 

**2** Test: Pulse Width < 300µs, Duty Cycle < 2.0% 

- **3** Starting TJ = 25°C, L = 1mH, IAS = 7A, VDD = 27V, VGS = 10V 

FDS6612A Rev D1 (W) 

**==> picture [467 x 641] intentionally omitted <==**

**----- Start of picture text -----**<br>
Typical Characteristics<br>40 2<br>VGS = 10V 4.5V VGS = 3.5V<br>4.0V 1.8<br>30 6.0V<br>1.6<br> 4.0V<br>20 1.4<br>3.5V 4.5V<br> 5.0V<br>1.2<br> 6.0V<br>10<br> 10V<br>3.0V 1<br>0 0.8<br>0 0.5 1 1.5 2 2.5 3 0 10 20 30 40<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1. On-Region Characteristics.  Figure 2. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.6 0.1<br>VIDGS = 8.4A = 10V ID = 4.2A<br>1.4 0.08<br>1.2 0.06<br>TA = 125 [o] C<br>1 0.04<br>TA = 25 [o] C<br>0.8 0.02<br>0.6 0<br>-50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with  Figure 4. On-Resistance Variation with<br>Temperature.  Gate-to-Source Voltage.<br>40 100<br>VDS = 5V VGS = 0V<br>10<br>30<br>1<br>TA = 125 [o] C<br>20 0.1<br>25 [o] C<br>TA = 125 [o] C<br>-55 [o] C 0.01<br>-55 [o] C<br>10<br>0.001<br>25 [o] C<br>0 0.0001<br>1.5 2 2.5 3 3.5 4 4.5 0 0.2 0.4 0.6 0.8 1 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD,  BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics.  Figure 6. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>FDS6612A Single N-Channel, Logic-Level, PowerTrench<br>, NORMALIZED <br>RDS(ON) , ON-RESISTANCE (OHM)DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br> MOSFET<br>, DRAIN CURRENT (A)ID<br>, REVERSE DRAIN CURRENT (A)IS<br>**----- End of picture text -----**<br>


FDS6612A Rev D1 (W) 

**==> picture [449 x 642] intentionally omitted <==**

**----- Start of picture text -----**<br>
Typical Characteristics<br>10 800<br>f = 1 MHz<br>ID = 8.4A VGS = 0 V<br>8<br>VDS = 10V 600<br>20V<br>6 Ciss<br>15V 400<br>4<br>Coss<br>200<br>2<br>Crss<br>0 0<br>0 2 4 6 8 10 12 0 5 10 15 20 25 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics.  Figure 8. Capacitance Characteristics.<br>100<br>100<br>100µs<br>R DS(ON)  LIMIT 1ms<br>10 10ms<br>100ms<br>1s<br>10s<br>1 10<br>DC<br>25<br>0.1 SINGLE PULSE VGS = 10V 125<br>RθJA = 125 [o] C/W<br>TA = 25 [o] C 1<br>0.01<br>0.001 0.01 0.1 1 10 100<br>0.01 0.1 1 10 100<br>VDS, DRAIN-SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (mS)<br>Figure 9. Maximum Safe Operating Area.   Figure 10. Unclamped Inductive Switching<br>Capability<br>50<br>40 SINGLE PULSE<br>RθJA = 125 [o] C/W<br>TA = 25 [o] C<br>30<br>20<br>10<br>0<br>0.001 0.01 0.1 1 10 100<br>t1, TIME (sec)<br>          Figure 11. Single Pulse Maximum Power Dissipation.<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)ID , AVALANCHE CURRENT (A)<br>IAS<br>P(pk),PEAK TRANSIENT POWER (W)<br>**----- End of picture text -----**<br>


FDS6612A Rev D1 (W) 

**==> picture [449 x 642] intentionally omitted <==**

**----- Start of picture text -----**<br>
Typical Characteristics<br>1<br>D = 0.5<br>0.2 R θJA (t) = r(t) * R θJA<br>0.1 0.1 RθJA = 125 [o] C/W<br>0.05<br>P(pk)<br>0.02<br>0.01 t 1<br>0.01 t2<br>T J - T A = P * Rθ JA (t)<br>SINGLE PULSE Duty Cycle, D = t 1  / t 2<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>Figure 12. Transient Thermal Response Curve.<br>                                                          Thermal characterization performed using the conditions described in Note 1c.<br>                                                          Transient thermal response will change depending on the circuit board design.<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


FDS6612A Rev D1 (W) 

PSPICE Electrical Model N-Channel .SUBCKT FDS6612A  2 1 3 *NOM TEMP=25 DEG C *REV A - JULY 2003 

CA 12 8 1E-9 CB 15 14 4.0E-10 CIN 6 8 5.1E-10 

**==> picture [432 x 253] intentionally omitted <==**

**----- Start of picture text -----**<br>
LDRAIN<br>DBODY 7 5 DBODYMOD  DPLCAP 5 DRAIN2<br>DBREAK 5 11 DBREAKMOD  10<br>DPLCAP 10 5 DPLCAPMOD  RSLC1 RLDRAIN<br>51 DBREAK<br>EBREAK 11 7 17 18 34.2  RSLC2<br>EGS 13 8 6 8 1 EDS 14 8 5 8 1  (=) 515 ESLC 11<br>EVTEMP 20 6 18 22 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1  ESG CS +- 68 EVTHRES 50RDRAIN16 EBREAK (-) +1718- DBODY<br>IT 8 17 1  LGATE EVTEMP + 198 - 21 MWEAK<br>LGATE 1 9 3.84E-9 LDRAIN 2 5 1.00E-9  GATE1 Foyt) 9RGATE20+ 1822 - 6 ot tie MMED<br>LSOURCE 3 7 4E-9  RLGATE San MSTRO<br>LSOURCE<br>RLGATE 1 9 38.4  CIN 8 7 SOURCE3<br>RLDRAIN 2 5 10  T RSOURCE Was<br>RLSOURCE 3 7 40  RLSOURCE<br>S1A S2A<br>MMED 16 6 8 8 MMEDMOD  12 13 14 15 17 RBREAK 18<br>MSTRO 16 6 8 8 MSTROMOD   8 13<br>MWEAK 16 21 8 8 MWEAKMOD      S1B S2B RVTEMP<br>RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 8E-3 RGATE 9 20 4.2  CA EGS13 +68 EDSCB+ 58 14 IT +-19VBAT<br>RSLC1 5 51 RSLCMOD 1E-6  oO - © - 8 ryT 22<br>RSLC2 5 50 1E3  RVTHRES<br>+<br>-<br>**----- End of picture text -----**<br>


RSLC1 5 51 RSLCMOD 1E-6 RSLC2 5 50 1E3 RSOURCE 8 7 RSOURCEMOD 7.5E-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 

S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD 

VBAT 22 19 DC 1 

ESLC 51 50  VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))} 

.MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6 + CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0) .MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6) .MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34) 

.MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1) .MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2) .MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U) .MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7) .MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6) .MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6) .MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6) .MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6) .MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6) 

.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3) 

.ENDS 

Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 

FDS6612A Rev D1 (W) 

## **SPICE Thermal Model** 

|.SUBCKT FDS6612A_THERM TH TL<br>*THERMAL MODEL SUBCIRCUIT<br>*REV A - JULY 2003<br>*MIN PAD RJA<br>CTHERM1<br>TH<br>8<br>CTHERM2<br>8<br>7<br>CTHERM3<br>7<br>6<br>CTHERM4<br>6<br>5<br>CTHERM5<br>5<br>4<br>CTHERM6<br>4<br>3<br>CTHERM7<br>3<br>2<br>CTHERM8<br>2<br>TL<br>RTHERM1<br>TH<br>8<br>RTHERM2<br>8<br>7<br>RTHERM3<br>7<br>6<br>RTHERM4<br>6<br>5<br>RTHERM5<br>5<br>4<br>RTHERM6<br>4<br>3<br>RTHERM7<br>3<br>2<br>RTHERM8<br>2<br>TL<br>.ENDS|0.005<br>0.05<br>0.10<br>0.35<br>0.45<br>0.50<br>0.55<br>3.00<br>5.000<br>6.250<br>7.500<br>8.750<br>10.625<br>11.875<br>31.250<br>43.750|**RTHERM6**<br>**RTHERM8**<br>**RTHERM7**<br>**RTHERM5**<br>**RTHERM4**<br>**RTHERM3**<br>**RTHERM2**<br>**RTHERM1**|**CTHERM4**<br>**CTHERM6**<br>**CTHERM5**<br>**CTHERM3**<br>**CTHERM2**<br>**CTHERM1**<br>**tl**<br>**2**<br>**3**<br>**4**<br>**5**<br>**6**<br>**7**<br>**JUNCTION**<br>**AMBIENT**<br>**8**<br>**th**<br>**CTHERM7**<br>**CTHERM8**<br>=|
|---|---|---|---|



FDS6612A Rev D1 (W) 

tm 

## **TRADEMARKS** 

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx[®] _i-Lo_ ™ Power-SPM™ 

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## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|<br>**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product  Status**|**Definition**|
|Advance Information|Formative or In Design|This datasheet contains the design specifications for product<br>development. Specifications may change in any manner<br>without notice.|
|Preliminary|First Production|This datasheet contains preliminary data; supplementary data will<br>be published at a later date. Fairchild Semiconductor reserves the<br>right to make changes at any time without notice to improve<br>design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at any time<br>without notice to improve design.|
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Rev. I26 

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## Links

- [View this product on Novapart](https://novapart.co/products/FDS6612A/power-mosfet-n-channel-30-v-84-a-0022-ohm-soic)
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- [Supplier page](https://es.farnell.com/onsemi/fds6612a/mosfet-n-smd-8-soic/dp/1467983)
---

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