# Dual MOSFET, Complementary N and P Channel, 40 V, 40 V, 6.2 A, 6.2 A, 0.021 ohm ![Product image](https://novapart.co/image/farnell:2453864/) **URL**: https://novapart.co/products/FDS4897C/dual-mosfet-complementary-n-and-p-channel-40-v-62 **SKU**: FDS4897C **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Dual MOSFETs **Price**: €1.0700 **Stock**: 25+ **Lead Time**: 265 days (indicative) ## Description Transistor Polarity:N and P Channel; Continuous Drain Current Id:6.2A; Drain Source Voltage Vds:40V; On Resistance Rds(on):; Available until stocks are exhausted Alternative available ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (23-Jan-2024) | | No. Of Pins | 8Pins | | Channel Type | Complementary N and P Channel | | Product Range | - | | Qualification | - | | Transistor Case Style | SOIC | | Operating Temperature Max | 150°C | | Power Dissipation N Channel | 2W | | Power Dissipation P Channel | 2W | | Drain Source Voltage Vds N Channel | 40V | | Drain Source Voltage Vds P Channel | 40V | | Continuous Drain Current Id N Channel | 6.2A | | Continuous Drain Current Id P Channel | 6.2A | | Drain Source On State Resistance N Channel | 0.021ohm | | Drain Source On State Resistance P Channel | 0.021ohm | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2453864/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [75 x 9] intentionally omitted <==** **----- Start of picture text -----**
November 2005
**----- End of picture text -----**
## **FDS4897C** ## **Dual N & P-Channel PowerTrench**[®] **MOSFET** ## **General Description Features** **==> picture [429 x 511] intentionally omitted <==** **----- Start of picture text -----**
These dual N- and P-Channel enhancement mode • Q1 : N-Channel
power field effect transistors are produced using
Fairchild Semiconductor’s advanced PowerTrench 6.2A, 40V RDS(on) = 29mΩ @ VGS = 10V
process that has been especially tailored to minimize on-state resistance and yet maintain superior switching RDS(on) = 36mΩ @ VGS = 4.5V
performance. • Q2 : P-Channel
Application –4.4A, –40V RDS(on) = 46mΩ @ VGS = –10V
• Inverter RDS(on) = 63mΩ @ VGS = –4.5V
• Power Supplies • High power handling capability in a widely used
surface mount package
• RoHS compliant
DD2 Q2
DD2 5 4
DD1
DD1 6 3
Q1
7 2
SO-8 S2G2G
& G1 S cf 8 @rt 1
S1 S
Pin 1 SO-8 Pas S dee
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter Q1 Q2 Units
VDSS Drain-Source Voltage 40 40 V
VGSS Gate-Source Voltage ±20 ±20 V
ID Drain Current - Continuous (Note 1a) 6.2 –4.4 A
- Pulsed 20 –20
PD Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
p
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS4897C FDS4897C 13” 12mm 2500 units
—
©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
FDS4897C Rev C(W)
**----- End of picture text -----**
www.fairchildsemi.com **==> picture [456 x 632] intentionally omitted <==** **----- Start of picture text -----**
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Avalanche Ratings (Note 3)
EAS Drain-Source Avalanche VDD = 40 V, ID = 7.3 A, L = 1 mH Q1 27 mJ
Energy (Single Pulse)
VDD = –40 V, ID =–8.7 A, L = 1 mH Q2 38 mJ
IAS Drain-Source Avalanche Q1 7.3 A
Current Q2 –8.7
Off Characteristics
BVDSS Drain-Source Breakdown VGS = 0 V, ID = 250 μA Q1 40 V
Voltage VGS = 0 V, ID = –250 μA Q2 –40
ΔBVDSS Breakdown Voltage ID = 250 μA, Referenced to 25°C Q1 34 mV/°C
ΔTJ Temperature Coefficient ID = –250 µA, Referenced to 25°C Q2 –40
IDSS Zero Gate Voltage Drain VDS = 32 V, VGS = 0 V Q1 1 μA
Current VDS = –32 V, VGS = 0 V Q2 –1
IGSS Gate-Body Leakage VGS = ±20 V, VDS = 0 V All ±100 nA
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 μA Q1 1 1.9 3 V
VDS = VGS, ID = –250 µA Q2 –1 –1.7 –3
ΔVGS(th) Gate Threshold Voltage ID = 250 μA, Referenced to 25°C Q1 –5 mV/°C
ΔTJ Temperature Coefficient ID = –250 µA, Referenced to 25°C Q2 4
RDS(on) Static Drain-Source VGS = 10 V, ID = 6.2 A Q1 21 29 mΩ
On-Resistance VGS = 4.5 V, ID = 4.8 A 26 36
VGS = 10 V, ID = 6.2 A, TJ = 125°C 29 43
VGS = –10 V, ID = –4.4 A Q2 37 46
VGS = –4.5 V, ID = –3.8 A 50 63
VGS = –10 V, ID = –4.4 A, TJ = 125°C 55 73
gFS Forward Transconductance VDS = 10 V, ID = 6.2 A Q1 21 S
VDS = –10 V, ID =–4.4 A Q2 12
Dynamic Characteristics
Ciss Input Capacitance Q1 Q1 760 pF
VDS = 20 V, VGS = 0 V, f = 1.0 MHz Q2 1050
Coss Output Capacitance Q1 100 pF
Q2 Q2 140
Crss Reverse Transfer VDS = –20 V, VGS = 0 V, f = 1.0 MHz Q1 60 pF
Capacitance Q2 70
RG Gate Resistance f = 1.0 MHz Q1 1.2 Ω
Q2 9
**----- End of picture text -----**
FDS4897C Rev C(W) www.fairchildsemi.com |**Electrical Characteristics(continued)**
TA= 25°C unless other|**Electrical Characteristics(continued)**
TA= 25°C unless other|**Electrical Characteristics(continued)**
TA= 25°C unless other|wise note|d|||| |---|---|---|---|---|---|---|---| |**Symbol**|
**Parameter**|**Test Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**| |**Switching Characteristics ** (Note 2)|||||||| |td(on)|Turn-On Delay Time|Q1
VDD= 20 V, ID= 1 A,
VGS= 10V, RGEN= 6Ω
Q2
VDD= –20 V, ID= –1 A,
VGS= –10V, RGEN= 6Ω|Q1
Q2||9
12|18
22|ns| |tr|Turn-On Rise Time||Q1
Q2||5
15|10
27|ns| |td(off)|Turn-Off Delay Time||Q1
Q2||23
45|37
72|ns| |tf|Turn-Off Fall Time||Q1
Q2||3
18|6
32|ns| |Qg|Total Gate Charge|Q1
VDS= 20 V, ID= 6.2 A, VGS= 10 V
Q2
VDS= –20 V, ID= –4.4 A,VGS=–10 V|Q1
Q2||14
20|20
28|nC| |Qgs|Gate-Source Charge||Q1
Q2||2.4
3||nC| |Qgd|Gate-Drain Charge||Q1
Q2||2.8
4||nC| |**Drain–Source Diode Characteristics **|||||||| |VSD|Drain-Source Diode Forward
Voltage|VGS= 0 V, IS= 1.3 A
(Note 2)
VGS= 0 V, IS= –1.3 A
(Note 2)|Q1
Q2||0.7
–0.7|1.2
–1.2|V| |trr|Diode Reverse Recovery
Time|Q1
IF= 6.2 A, diF/dt= 100 A/µs
Q2
IF= –4.4 A,diF/dt= 100 A/µs|Q1
Q2||17
24||ns| |Qrr|Diode Reverse Recovery
Charge||Q1
Q2||7
12||nC| **Notes:** **1.** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. **==> picture [62 x 76] intentionally omitted <==** a) 78°C/W when b) 125°C/W when c) 135°C/W when mounted on a mounted on a mounted on a .02 in[2] minimum pad. 0.5 in[2] pad of 2 oz pad of 2 oz copper copper Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0% 3. BV(avalanche) Single-Pulse rating is guaranteed by design if device is operated within the UIS SOA boundary of the device. FDS4897C Rev C(W) www.fairchildsemi.com ## **Typical Characteristics: Q1 (N-Channel)** **==> picture [429 x 540] intentionally omitted <==** **----- Start of picture text -----**
20 3
VGS = 10V 4.0V 3.5V VGS = 3.0V
2.6
16
2.2
6.0V 4.5V
12
1.8
8 3.5V
3.0V 1.4 4.0V
4.5V
4 6.0V
1 10V
0 0.6
0 0.5 1 1.5 2 2.5 0 4 8 12 16 20
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6 0.07
VIDGS = 7.0A = 10V ID = 3.5A
1.4 0.06
0.05
1.2
0.04
1 TA = 125 [o] C
0.03
0.8 TA = 25 [o] C
0.02
0.6 0.01
-50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with
Temperature. Gate-to-Source Voltage.
20 100
VDS = 10V VGS = 0V
10
15
TA = 125 [o] C
1
25 [o] C
10 0.1
TA = 125 [o] C -55 [o] C 0.01 -55 [o] C
5
0.001
25 [o] C
0 0.0001
1 1.5 2 2.5 3 3.5 0 0.2 0.4 0.6 0.8 1 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
, NORMALIZED
, DRAIN CURRENT (A)ID RDS(ON)
DRAIN-SOURCE ON-RESISTANCE
, NORMALIZED
RDS(ON) , ON-RESISTANCE (OHM)DS(ON)
R
DRAIN-SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)ID
, REVERSE DRAIN CURRENT (A)IS
**----- End of picture text -----**
FDS4897C Rev C(W) www.fairchildsemi.com **==> picture [460 x 610] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics: Q1 (N-Channel)
10 1000
f = 1 MHz
ID = 7A VDS = 10V VGS = 0 V
8 800
30V
Ciss
20V
6 600
4 400
Coss
2 200
Crss
0 0
0 4 8 12 16 0 5 10 15 20 25 30 35 40
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.
100 50
SINGLE PULSE
10 R DS(ON) LIMIT 100μs 40 RθJAT = 135°C/WA = 25°C
1ms
10ms
30
100ms
1 1s
10s
DC 20
0.1 VGS = 10.0V
SINGLE PULSE 10
R θJA = 135 [o] C/W
T A = 25 [o] C
0.01 0
0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000
VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
50 100
SINGLE PULSE
40 RθJAT = 135°C/WA = 25°C
30 TJ = 25oC
10
20
10
0 1
0.001 0.01 0.1 1 10 100 1000 0.01 0.1 1 10
t1, TIME (sec) tAV, TIME IN AVANCHE(ms)
Figure 11. Single Pulse Maximum Peak Figure 12. Unclamped Inductive Switching
Current. Capability.
CAPACITANCE (pF)
, GATE-SOURCE VOLTAGE (V)
GS
V
FDS4897C Dual N & P-Channel PowerTrench
®
, DRAIN CURRENT (A)ID
P(pk), PEAK TRANSIENT POWER (W)
MOSFET
, AVALANCHE CURRENT (A)
I(pk), PEAK TRANSIENT CURRENT (A) I(AS)
**----- End of picture text -----**
## **Typical Characteristics: Q1 (N-Channel)** FDS4897C Rev C(W) www.fairchildsemi.com ## **Typical Characteristics: Q2 (P-Channel)** **==> picture [425 x 503] intentionally omitted <==** **----- Start of picture text -----**
30 2.6
VGS = -10V -6.0V -4.5V
2.4
25
-4.0V
2.2
20 2 VGS = - 3.5V
1.8
15 -3.5V -4.0V
1.6
-4.5V
10 1.4
-3.0V -6.0V
1.2
5 -10V
1
0 0.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 5 10 15 20 25 30
-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)
Figure 13. On-Region Characteristics. Figure 14. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6 0.14
1.5 ID = -4.4A ID = -2.2A
VGS = - 10V 0.12
1.4
1.3 0.1
1.2 TA = 125 [o] C
1.1 0.08
1
0.06
0.9
TA = 25 [o] C
0.8
0.04
0.7
0.6 0.02
-50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)
Figure 15. On-Resistance Variation with Figure 16. On-Resistance Variation with
Temperature. Gate-to-Source Voltage.
25 100
20 VDS = -10V TA = -55 [o] C 25 [o] C 10 V GS = 0V
125 [o] C 1 T A = 125 [o] C
15
25 [o] C
0.1
10
-55 [o] C
0.01
5
0.001
0 0.0001
1.5 2 2.5 3 3.5 4 4.5 0 0.2 0.4 0.6 0.8 1 1.2
-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)
, NORMALIZED
, DRAIN CURRENT (A)-ID RDS(ON)
DRAIN-SOURCE ON-RESISTANCE
, NORMALIZED
DS(ON) , ON-RESISTANCE (OHM)
R DS(ON)
R
DRAIN-SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)-ID
, REVERSE DRAIN CURRENT (A)-IS
**----- End of picture text -----**
**Figure 17. Transfer Characteristics.** **Figure 18. Body Diode Forward Voltage Variation with Source Current and Temperature.** FDS4897C Rev C(W) www.fairchildsemi.com ## **Typical Characteristics: Q2 (P-Channel)** **==> picture [419 x 135] intentionally omitted <==** **----- Start of picture text -----**
10 1400
8 ID = -4.4A VDS = -10V -20V 1200 CISS f = 1 MHz VGS = 0 V
1000
-30V
6
800
4 600
400
2 COSS
200
CRSS
0 0
0 5 10 15 20 25 0 5 10 15 20 25 30 35 40
Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
, GATE-SOURCE VOLTAGE (V)
GS
-V
**----- End of picture text -----**
**Figure 19. Gate Charge Characteristics.** **Figure 20. Capacitance Characteristics.** **==> picture [424 x 132] intentionally omitted <==** **----- Start of picture text -----**
100 50
SINGLE PULSE
10 R DS(ON) LIMIT 100μ 40 RθJAT = 135°C/WA = 25°C
1ms
10ms
30
100ms
1 1s
10s
DC 20
VGS = -10V
0.1 SINGLE PULSE
RθJA = 135 [o] C/W 10
T A = 25 [o] C
0.01 0
0.1 1 10 100 0.001 0.01 0.1 1 10 100 1000
-VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)
, DRAIN CURRENT (A)-ID
P(pk), PEAK TRANSIENT POWER (W)
**----- End of picture text -----**
**Figure 21. Maximum Safe Operating Area.** **Figure 22. Single Pulse Maximum Power Dissipation.** **==> picture [417 x 168] intentionally omitted <==** **----- Start of picture text -----**
40 100
SINGLE PULSE
RθJA = 135°C/W
30 TA = 25°C
TJ = 25oC
20 10
10
0 1
0.001 0.01 0.1 1 10 100 1000 0.01 0.1 1 10
t1, TIME (sec) tAV, TIME IN AVANCHE(ms)
Figure 23. Single Pulse Maximum Peak Figure 24. Unclamped Inductive Switching
Current Capability
, AVALANCHE CURRENT (A)
I(AS)
P(pk), PEAK TRANSIENT CURRENT (A)
**----- End of picture text -----**
FDS4897C Rev C(W) www.fairchildsemi.com ## **Typical Characteristics : N and P-Channel** **==> picture [424 x 128] intentionally omitted <==** **----- Start of picture text -----**
1
D = 0.5
0.2 R θJA (t) = r(t) * R θJA
0.1 0.1 RθJA = 135 [o] C/W
0.05
P(pk)
0.02
0.01 t 1
0.01 t2
TJ - TA = P * RθJA(t)
SINGLE PULSE Duty Cycle, D = t 1 / t 2
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
**----- End of picture text -----**
## **Figure 25. Transient Thermal Response Curve.** **Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design.** FDS4897C Rev C(W) www.fairchildsemi.com ## **TRADEMARKS** The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. |
FAST®
FASTr™
FPS™
FRFET™
ACEx™
ActiveArray™
Bottomless™
Build it Now™|ISOPLANAR™
LittleFET™
MICROCOUPLER™
MicroFET™|PowerSaver™
PowerTrench®
QFET®
QS™|SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic®| |---|---|---|---| |GlobalOptoisolator™
CoolFET™|MicroPak™|QT Optoelectronics™|TINYOPTO™| |GTO™
_CROSSVOLT_™|MICROWIRE™|Quiet Series™|TruTranslation™| |HiSeC™
I2C™
DOME™
EcoSPARK™|MSX™
MSXPro™|RapidConfigure™
RapidConnect™|UHC™
UltraFET®| |_i-Lo_™
E2CMOS™|OCX™|μSerDes™|UniFET™| |ImpliedDisconnect™
IntelliMAX™
EnSigna™
FACT™|OCXPro™
OPTOLOGIC®|ScalarPump™
SILENT SWITCHER®|VCX™
Wire™| |FACT Quiet Series™|OPTOPLANAR™|SMART START™|| |Across the board. Around the world.™
The Power Franchise®
Programmable Active Droop™|PACMAN™
POP™
Power247™
PowerEdge™|SPM™
Stealth™
SuperFET™
SuperSOT™-3|| ## **DISCLAIMER** FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. ## **LIFE SUPPORT POLICY** FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. ## **PRODUCT STATUS DEFINITIONS** ## **Definition of Terms** |**Definition of Terms**||| |---|---|---| |**Datasheet Identification**|**Product Status**|**Definition**| |Advance Information|Formative or
In Design|This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.| |Preliminary|First Production|This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.| |No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.| |Obsolete|Not In Production|This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
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