# Power MOSFET, N Channel, 80 V, 8.9 A, 0.016 ohm, SOIC, Surface Mount ![Product image](https://novapart.co/image/farnell:2453413/) **URL**: https://novapart.co/products/FDS3572/power-mosfet-n-channel-80-v-89-a-0016-ohm-soic **SKU**: FDS3572 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.6380 **Stock**: 500+ **Lead Time**: 141 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:8.9A; Drain Source Voltage Vds:80V; On Resistance Rds(on):0.014ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Powe ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 2.5W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | SOIC | | Drain Source Voltage Vds | 80V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 8.9A | | Drain Source On State Resistance | 0.016ohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2453413/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **November 2003 FDS3572** ## **N-Channel PowerTrench**[®] **MOSFET** ## **80V, 8.9A, 16m** Ω ## **Features Applications** - rDS(ON) = 14mΩ (Typ.), VGS = 10V, ID = 8.9A • Primary switch for Isolated DC/DC converters - Qg(tot) = 31nC (Typ.), VGS = 10V • Distributed Power and Intermediate Bus Architectures - Low Miller Charge - High Voltage Synchronous Rectifier for DC Bus - • Low QRR Body Diode Converters - Optimized efficiency at high frequencies - UIS Capability (Single Pulse and Repetitive Pulse) |Formerly developmental type 82663|Formerly developmental type 82663|Formerly developmental type 82663|||| |---|---|---|---|---|---| |**Branding Dash**||||**5**|**4**| ||||**5**|**6**|**3**| |**1**||||**7**|**2**| |**2**|**3**||||| ||**4**|||**8**|**1**| ||**SO-8**||||| |**MOSFET Maximum Ratings **TA= 25°C unless otherwise noted|||||| |**Symbol**
**Parameter**||**Ratings**|**Ratings**|**Units**| |---|---|---|---|---| |VDSS
Drain to Source Voltage||80||V| |VGS
Gate to Source Voltage||±20||V| |Drain Current||||| |ID
Continuous(TA= 25oC, VGS= 10V, RθJA= 50oC/W)
Continuous(TA= 100oC, VGS= 10V, RθJA= 50oC/W)||8.9
5.6||A
A| |Pulsed||Figure 4||A| |EAS
Single Pulse Avalanche Energy (Note 1)||515||mJ| |PD
Power dissipation
Derate above 25oC||2.5
20||W
mW/oC| |TJ, TSTG
Operatingand Storage Temperature||-55 to 150||oC| |**Thermal Characteristics**||||| |**Package Marking and Ordering Information**
RθJC
Thermal Resistance, Junction to Case (Note 2)
25
oC/W
RθJA
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)
50
oC/W
RθJA
Thermal Resistance, Junction to Ambient at 1000 seconds(Note 3)
85
oC/W
~~—_——~~
~~a~~
~~a~~||||| |**Device Marking**
**Device**
**Package**
FDS3572
FDS3572
SO-8
~~——~~|**Reel Size**
330mm|**Tape Width**
12mm|**Quantity**
2500 units|| ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A |**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted||||| |---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**||**Min**|**Typ**|**Max**|**Units**| |**Off Characteristics**|||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250µA, VGS|= 0V|80|-|-|V| |IDSS|Zero Gate Voltage Drain Current|VDS= 60V
VGS= 0V||-|-|1|µA| ||||TA= 150oC|-|-|250|| |IGSS|Gate to Source Leakage Current|VGS=±20V||-|-|±100|nA| |**On Characteristics**|||||||| |VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250µA||2|-|4|V| |rDS(ON)|Drain to Source On Resistance|ID= 8.9A, VGS = 10V||-|0.014|0.016|Ω| |||ID= 5.6A, VGS= 6V||-|0.019|0.029|| |||ID= 8.9A, VGS= 10V,
TA= 150oC||-|0.027|0.032|| |**Dynamic Characteristics**|||||||| |CISS|Input Capacitance|VDS= 25V, VGS= 0V,
f = 1MHz||-|1990|-|pF| |COSS|Output Capacitance|||-|320|-|pF| |CRSS|Reverse Transfer Capacitance|||-|85|-|pF| |Qg(tot)|Total Gate Charge at 10V|VGS= 0V to 10V||-|31|41|nC| |Qg(TH)|Threshold Gate Charge|VGS= 0V to 2V||-|4|5.2|nC| |Qgs|Gate to Source Gate Charge|||-|9|-|nC| |Qgs2|Gate Charge Threshold to Plateau|||-|5|-|nC| |Qgd|Gate to Drain “Miller” Charge|||-|7.5|-|nC| |**Switching Characteristics**(VGS= 10V)|||||||| |tON|Turn-On Time|VDD= 40V, ID= 8.9A
VGS= 10V, RGS= 10Ω||-|-|40|ns| |td(ON)|Turn-On Delay Time|||-|13|-|ns| |tr|Rise Time|||-|14|-|ns| |td(OFF)|Turn-Off Delay Time|||-|31|-|ns| |tf|Fall Time|||-|13|-|ns| |tOFF|Turn-Off Time|||-|-|67|ns| |**Drain-Source Diode Characteristics**|||||||| |VSD|Source to Drain Diode Voltage|ISD= 8.9A||-|-|1.25|V| |||ISD= 4.3A||-|-|1.0|V| |trr|Reverse RecoveryTime|ISD= 8.9A, dISD/dt= 100A/µs||-|-|50|ns| |QRR|Reverse Recovered Charge|ISD= 8.9A, dISD/dt= 100A/µs||-|-|70|nC| **Notes:** - **1:** Starting TJ = 25°C, L = 21mH, IAS = 7A. - **2:** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design. - **3:** RθJA is measured with 1.0 in[2] copper on FR-4 board ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A **==> picture [430 x 600] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TA = 25°C unless otherwise noted
1.2 10
VGS = 10V
1.0
8
0.8
6
0.6
4
0.4
2
0.2
R θ JA =50 [o] C/W
0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE ( [o] C) TA, AMBIENT TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature Ambient Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2 R θ JA=50 [o] C/W
0.1
0.05
0.02
0.01
0.1
PDM
0.01 t1
SINGLE PULSE t 2
NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK TJ = PDM x Z θ JA x R θ JA + TA
0.001
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TRANSCONDUCTANCE TA = 25 [o] C
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION
ABOVE 25 [o] C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V I = I25 150 - T A
125
100
10
5
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJA θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
**----- End of picture text -----**
**Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs Ambient Temperature Ambient Temperature** ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A **Typical Characteristics** TA = 25°C unless otherwise noted **==> picture [429 x 596] intentionally omitted <==** **----- Start of picture text -----**
50 20
If R = 0 PULSE DURATION = 80 µ s
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) DUTY CYCLE = 0.5% MAX
If R tAV = ≠ 0 (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] VDD = 15V
15
TJ = 150 [o] C
10
10
STARTING TJ = 25 [o] C
TJ = 25 [o] C TJ = -55 [o] C
5
STARTING TJ = 150 [o] C
1 0
0.1 1 10 100 3.0 3.5 4.0 4.5 5.0 5.5
tAV, TIME IN AVALANCHE (ms) VGS, GATE TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Transfer Characteristics
Figure 5. Unclamped Inductive Switching
Capability
20 20
VGS = 10V VGS = 6V VGS = 6V
VGS = 5V
15 18
VGS = 4.5V
10 16
VGS = 10V
5 14
TA = 25 [o] C
PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
0 12
0 0.25 0.5 0.75 1.0 0 2 4 6 8 10
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Drain
Current
2.0 1.2
PULSE DURATION = 80 µ s VGS = VDS, ID = 250 µ A
DUTY CYCLE = 0.5% MAX
1.1
1.5 1.0
0.9
1.0 0.8
0.7
VGS = 10V, ID = 8.9A
0.5 0.6
-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Normalized Drain to Source On Figure 10. Normalized Gate Threshold Voltage vs
Resistance vs Junction Temperature Junction Temperature
, DRAIN CURRENT (A)
, AVALANCHE CURRENT (A) ID
IAS
) Ω
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON RESISTANCE (m
ON RESISTANCE
NORMALIZED GATE THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
**----- End of picture text -----**
**==> picture [201 x 27] intentionally omitted <==** **----- Start of picture text -----**
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 5. Unclamped Inductive Switching
Capability
**----- End of picture text -----**
©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A **==> picture [429 x 390] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TA = 25°C unless otherwise noted
1.2 5000
ID = 250 µ A CISS = CGS + CGD
1000
C OSS ≅ C DS + C GD
1.1
CRSS = CGD
100
1.0
VGS = 0V, f = 1MHz
0.9 10
-80 -40 0 40 80 120 160 0.1 1 10 80
TJ, JUNCTION TEMPERATURE ( [o] C) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain to Source Figure 12. Capacitance vs Drain to Source
Breakdown Voltage vs Junction Temperature Voltage
10
VDD = 40V
8
6
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 8.9A
ID = 1A
0
0 10 20 30 40
Qg, GATE CHARGE (nC)
BREAKDOWN VOLTAGE C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**Figure 13. Gate Charge Waveforms for Constant Gate Currents** ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A **==> picture [427 x 176] intentionally omitted <==** **----- Start of picture text -----**
Test Circuits and Waveforms
VDS BVDSS
tP
L VDS
IAS
VARY tP TO OBTAIN + VDD
REQUIRED PEAK IAS RG VDD
VGS -
DUT
tP
0V IAS 0
0.01 Ω
tAV
**----- End of picture text -----**
**==> picture [403 x 10] intentionally omitted <==** **----- Start of picture text -----**
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
**----- End of picture text -----**
**==> picture [421 x 358] intentionally omitted <==** **----- Start of picture text -----**
VDS
VDD Qg(TOT)
L VDS
VGS VGS = 10V
VGS +
VDD Qgs2
-
DUT
Ig(REF) VGS = 2V
0
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 0 10%
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
**----- End of picture text -----**
©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A ## _**Thermal Resistance vs. Mounting Pad Area**_ The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance RθJA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. **==> picture [189 x 22] intentionally omitted <==** In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. **==> picture [190 x 18] intentionally omitted <==** The transient thermal impedance (ZθJA) is also effected by varied top copper board area. Figure 22 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized **==> picture [191 x 150] intentionally omitted <==** **----- Start of picture text -----**
200
R θ JA = 64 + 26/(0.23+Area)
150
100
50
0.001 0.01 0.1 1 10
AREA, TOP COPPER AREA (in [2] )
Figure 21. Thermal Resistance vs Mounting
Pad Area
oC/W)( RJA θ
**----- End of picture text -----**
**==> picture [408 x 143] intentionally omitted <==** **----- Start of picture text -----**
150
COPPER BOARD AREA - DESCENDING ORDER
0.04 in [2]
120 0.28 in [2]
0.52 in [2]
0.76 in [2]
90 1.00 in [2]
60
30
0
10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]
t, RECTANGULAR PULSE DURATION (s)
Figure 22. Thermal Impedance vs Mounting Pad Area
oC/W)
, THERMAL
ZJA θ
MPEDANCE (I
**----- End of picture text -----**
©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A ## _**PSPICE Electrical Model**_ .SUBCKT FDS3572 2 1 3 ; rev November 2003 Ca 12 8 7e-10 Cb 15 14 7e-10 Cin 6 8 1.9e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD **==> picture [319 x 257] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
515 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE RGATE + 18 - 6
1 9 20 22 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Ebreak 11 7 17 18 86.6 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 1e-9 Ldrain 2 5 1e-9 Lsource 3 7 0.1e-9 RLgate 1 9 10 RLdrain 2 5 10 RLsource 3 7 1 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 5.5e-3 Rgate 9 20 1.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 5.5e-3 Rvthres 22 8 Rvthresmod 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))} .MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5 XTI=3 CJO=1.4e-9 TT=3e-08 M=0.55) .MODEL DbreakMOD D (RS=2.5 TRS1=1e-4 TRS2=1e-6) .MODEL DplcapMOD D (CJO=4.6e-10 IS=1e-30 N=10 M=0.5) .MODEL MmedMOD NMOS (VTO=3.35 KP=3 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.3 T_ABS=25) .MODEL MstroMOD NMOS (VTO=3.9 KP=60 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=2.88 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=1e-3 TC2=-7.5e-7) .MODEL RdrainMOD RES (TC1=4.8e-3 TC2=3e-5) .MODEL RSLCMOD RES (TC1=2.4e-2 TC2=1e-7) .MODEL RsourceMOD RES (TC1=1e-2 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-4.4e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A ## _**SABER Electrical Model**_ REV November 2003 template FDS3572 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,xti=3,cjo=1.4e-9,tt=3e-08,m=0.55) dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6) dp..model dplcapmod = (cjo=4.6e-10,isl=10e-30,nl=10,m=0.5) m..model mmedmod = (type=_n,vto=3.35,kp=3,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.9,kp=60,is=1e-30, tox=1) **==> picture [432 x 263] intentionally omitted <==** **----- Start of picture text -----**
m..model mweakmod = (type=_n,vto=2.88,kp=0.04,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0) DPLCAP 5 LDRAIN DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0) 2
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0) 10 RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5) RSLC1
c.ca n12 n8 = 7e-10 51
c.cb n15 n14 = 7e-10 RSLC2
c.cin n6 n8 = 1.9e-9 ISCL
dp.dbody n7 n5 = model=dbodymod - 50 DBREAK
6 RDRAIN
dp.dbreak n5 n11 = model=dbreakmoddp.dplcap n10 n5 = model=dplcapmod ESG + 8 EVTHRES 16 11 DBODY
spe.ebreak n11 n7 n17 n18 = 86.6spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 GATE1 RLGATELGATE 9RGATE20EVTEMP+ 1822 - 6 + 198 CIN- MSTRO21 8 MMED MWEAKEBREAK+-1718 7 LSOURCE SOURCE3
RSOURCE
i.it n8 n17 = 1 RLSOURCE
S1A S2A
l.lgate n1 n9 = 1e-9 12 138 1413 15 17 RBREAK 18
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 0.1e-9 S1B S2B RVTEMP
res.rlgate n1 n9 = 10 CA 13+ CB+ 14 IT -19
res.rldrain n2 n5 = 10res.rlsource n3 n7 = 1 EGS -68 EDS - 58 8 + VBAT
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp RVTHRES
**----- End of picture text -----**
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7.5e-7 res.rdrain n50 n16 = 5.5e-3, tc1=4.8e-3,tc2=3e-5 res.rgate n9 n20 = 1.3 res.rslc1 n5 n51 = 1e-6, tc1=2.4e-2,tc2=1e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.5e-3, tc1=1e-2,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-4.4e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5)) } } ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A ## _**SPICE Thermal Model**_ |
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
**_SABER Thermal Model_**
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
**RTHERM6**
**RTHERM8**
**RTHERM7**
**RTHERM5**
**RTHERM4**
**RTHERM3**
**RTHERM2**
**RTHERM1**
**TABLE 1. THERMAL MODELS**|
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
**_SABER Thermal Model_**
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
**RTHERM6**
**RTHERM8**
**RTHERM7**
**RTHERM5**
**RTHERM4**
**RTHERM3**
**RTHERM2**
**RTHERM1**
**TABLE 1. THERMAL MODELS**|
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
**_SABER Thermal Model_**
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
**RTHERM6**
**RTHERM8**
**RTHERM7**
**RTHERM5**
**RTHERM4**
**RTHERM3**
**RTHERM2**
**RTHERM1**
**TABLE 1. THERMAL MODELS**|
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
**_SABER Thermal Model_**
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
**RTHERM6**
**RTHERM8**
**RTHERM7**
**RTHERM5**
**RTHERM4**
**RTHERM3**
**RTHERM2**
**RTHERM1**
**TABLE 1. THERMAL MODELS**|
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
**_SABER Thermal Model_**
Copper Area = 1.0 in2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
**RTHERM6**
**RTHERM8**
**RTHERM7**
**RTHERM5**
**RTHERM4**
**RTHERM3**
**RTHERM2**
**RTHERM1**
**TABLE 1. THERMAL MODELS**|**th**|**th**| |---|---|---|---|---|---|---| |||||||| ||||||**8**|| |||||||| ||||||**7**|| |||||||| ||||||**6**|| |||||||| ||||||**5**|| |||||||| ||||||**4**|| |||||||| ||||||**3**|| |||||||| ||||||**2**|| |||||||| |**COMPONANT**|**0.04 in2**|**0.28 in2**|**0.52 in2**||**0.76 in2**|**1.0 in2**| |CTHERM6|1.2e-1|1.5e-1|2.0e-1||2.0e-1|2.0e-1| |CTHERM7|0.5|1.0|1.0||1.0|1.0| |CTHERM8|1.3|2.8|3.0||3.0|3.0| |RTHERM6|26|20|15||13|12| |RTHERM7|39|24|21||19|18| |RTHERM8|55|38.7|31.3||29.7|25| ©2003 Fairchild Semiconductor Corporation FDS3572 Rev. A ## **TRADEMARKS** The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. |ACEx™|FACT Quiet Series™|ISOPLANAR™|POP™|SuperFET™| |---|---|---|---|---| |ActiveArray™|
FAST|LittleFET™
|Power247™
|SuperSOT™-3| |Bottomless™|FASTr™|MICROCOUPLER™|PowerTrench|SuperSOT™-6| |
CoolFET™|FPS™|MicroFET™|QFET|SuperSOT™-8| |_CROSSVOLT_™|FRFET™|MicroPak™|QS™|SyncFET™| |DOME™|GlobalOptoisolator™|MICROWIRE™|QT Optoelectronics™|TinyLogic| |EcoSPARK™|GTO™|MSX™|Quiet Series™|TINYOPTO™| |E2CMOSTM|HiSeC™|MSXPro™|RapidConfigure™|TruTranslation™| |EnSignaTM|I2C™|OCX™|RapidConnect™|UHC™| |FACT™|ImpliedDisconnect™|OCXPro™|SILENT SWITCHER|UltraFET| |Across the board. Around the world.™||OPTOLOGIC|SMART START™|VCX™| |The Power Franchise™||OPTOPLANAR™|SPM™|| |Programmable Active Droop™||PACMAN™|Stealth™|| ## **DISCLAIMER** FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. ## **LIFE SUPPORT POLICY** FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. ## **PRODUCT STATUS DEFINITIONS** ## **Definition of Terms** |**Datasheet Identification**|**Product Status**|**Definition**| |---|---|---| |Advance Information|Formative or
In Design|This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.| |Preliminary|First Production|This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
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Semiconductor reserves the right to make changes at
any time without notice in order to improve design.| |Obsolete|Not In Production|This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
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