# Power MOSFET, N Channel, 150 V, 4.9 A, 0.047 ohm, SOIC, Surface Mount ![Product image](https://novapart.co/image/farnell:9845186RL/) **URL**: https://novapart.co/products/FDS2572/power-mosfet-n-channel-150-v-49-a-0047-ohm-soic **SKU**: FDS2572 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.6530 **Stock**: 10+ **Lead Time**: 98 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:4.9A; Drain Source Voltage Vds:150V; On Resistance Rds(on):0.04ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Power Dissipation Pd ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 2.5W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | SOIC | | Drain Source Voltage Vds | 150V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 4.9A | | Drain Source On State Resistance | 0.047ohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:9845186RL/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [41 x 10] intentionally omitted <==** **----- Start of picture text -----**
July 2013
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## **FDS2572** ## **150V, 0.047 Ohms, 4.9A, N-Channel UltraFET[®] Trench MOSFET** ## **General Description** ## **Features** |**General Description**|**Features**|**Features**|**Features**|**Features**|||||| |---|---|---|---|---|---|---|---|---|---| |UltraFET®devices combine characteristics that enable|•|RDS(ON)= 0.040Ω(Typ.), V|||(Typ.), VGS=10V||||| |benchmark efficiency in power conversion applications.
Optimized for Rds(on), low ESR, low total and Miller gate|•|Qg(TOT)= 29nC (Typ.), VGS=10V|||||||| |charge, these devices are ideal for high frequency DC to|•|Low QRRBody Diode|||||||| |DC converters.|||||||||| ||•|Maximized efficiency at high frequencies|||||||| |**Applications**|•|UIS Rated|||||||| |• DC/DC converters|||||||||| |• Telecom and Data-Com Distributed Power Architectures|||||||||| |• 48-volt I/P Half-Bridge/Full-Bridge|||||||||| |• 24-volt Forward and Push-Pull topologies|||||||||| |**S**
**D**
**S**
**S**
**SO-8**
**D**
**D**
**D**
**G**
**D**
**D**
**D D**
**S S S**
**G**
Pin 1
**SO-8**
~~*~~|||**5**
**6**
**7**
**8**||||**4**
**3**
**2**
**1**||| |**MOSFET Maximum Ratings **TA=25°C unless otherwise noted|||||||||| |**Symbol**
**Parameter**|||||**Ratings**||||**Units**| |VDSS
Drain to Source Voltage|||||150||||V| |VGS
Gate to Source Voltage|||||±20||||V| |Drain Current|||||||||| |ID
Continuous (TC= 25oC, VGS= 10V, RθJA= 50oC/W)
Continuous (TC= 100oC, VGS= 10V, RθJA= 50o
C/W)|||||4.9
3.1||||A
A| |Pulsed|||||Figure 4|Figure 4|||A| |PD
Power dissipation
Derate above 25oC|||||2.5
20|||W
mW/oC|| |TJ, TSTG
Operating and Storage Temperature|||||-55 to 150||||oC| |**Thermal Characteristics**|||||||||| |**Package Marking and Ordering Information**
RθJC
Thermal Resistance Junction to Case(NOTE1)
25
oC/W
RθJA
Thermal Resistance Junction to Case at 10 seconds(NOTE2)
50
oC/W
RθJA
Thermal Resistance Junction to Case at steady state(NOTE2)
85
oC/W
rs
ee|||||||||| |**Device Marking**
**Device**
**Reel Size**
**Tape Width**
**Quantity**
FDS2572
FDS2572
330mm
12mm
2500units
ti]
+——|||||||||| ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 |**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|||||| |---|---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**||**Min**|**Typ**||**Max**|**Units**| |**Off Characteristics**||||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250µA, VGS= 0V||150|-||-|V| |IDSS|Zero Gate Voltage Drain Current|VDS= 120V
VGS= 0V||-|-||1|µA| ||||TC= 150o
C|-|-||250|| |IGSS|Gate to Source Leakage Current|VGS=±20V||-|-||±100|nA| |**On Characteristics**||||||||| |VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID=|250µA|2||-|4|V| |rDS(ON)|Drain to Source On Resistance|ID= 4.9A, VGS|= 10V|-||0.040|0.047|Ω| |rDS(ON)|Drain to Source On Resistance|ID= 4.9A, VGS|= 6V|-||0.044|0.053|Ω| |**Dynamic Characteristics**||||||||| |CISS|Input Capacitance|VDS= 25V, VGS= 0V,
f = 1MHz||-||2050|2870|pF| |COSS|Output Capacitance|||-||220|310|pF| |CRSS|Reverse Transfer Capacitance|||-||48|80|pF| |Rg|Gate Resistance|||0.1||1.3|3.0|Ω| |Qg(TOT)|Total Gate Charge at 10V|VGS= 0V to 10V||-||29|38|nC| |Qg(TH)|Threshold Gate Charge|VGS= 0V to 2V||-||4|6|nC| |Qgs|Gate to Source Gate Charge|||-||8|-|nC| |Qgd|Gate to Drain “Miller” Charge|||-||6|-|nC| |Qgs2|Gate Charge Threshold to Plateau|||-||4|-|nC| |**Switching Characteristics**||||||||| |tON|Turn-On Time|VDD= 75V, ID= 4.9A
VGS= 10V, RG= 10Ω||-||-|27|ns| |td(ON)|Turn-On Delay Time|||-||14|-|ns| |tr|Rise Time|||-||4|-|ns| |td(OFF)|Turn-Off Delay Time|||-||44|-|ns| |tf|Fall Time|||-||22|-|ns| |tOFF|Turn-Off Time|||-||-|100|ns| |**Drain-Source Diode Characteristics**||||||||| |VSD|Source to Drain Diode Voltage|ISD= 4.9A||-||-|1.25|V| |||ISD= 3.1A||-||-|1.0|V| |trr|Reverse Recovery Time|ISD= 4.9A, dISD/dt =100A/µs||-||-|72|ns| |QRR|Reverse Recovered Charge|ISD= 4.9, dISD/dt =100A/µs||-||-|158|nC| **Notes:** 1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal referance is defined as the solder mounting surface of the drain pins. R θ JC is guaranteed by design while R θ CA is determined by the user’s board design. 2. R θ JA is measured with 1.0in[2] copper on FR-4 board FDS2572 Rev. C, July 2013 ©2001 Fairchild Semiconductor Corporation **==> picture [432 x 600] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristic
1.2 6
1.0
VGS = 10V
0.8 4
0.6
0.4 2
0.2
0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continous Drain Current vs
Ambient Temperature Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
0.1
PDM
0.01 t1
t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x Z θ JA x R θ JA + TA
0.001
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
600
TRANSCONDUCTANCE TC = 25 [o] C
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION
ABOVE 25 [o] C DERATE PEAK
100 CURRENT AS FOLLOWS:
VGS = 10V
I = I25 150 - TC
125
10
1
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJA θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
**----- End of picture text -----**
©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 **==> picture [430 x 620] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristic (Continued)
10 30
PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
STARTING TJ = 25 [o] C VDD = 15V
20
1 STARTING TJ = 150 [o] C TJ = 25 [o] C
10
TJ = 150 [o] C
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) TJ = -55 [o] C
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1 0
0.001 0.1 1 10 100 3 4 5 6
tAV, TIME IN AVALANCHE (ms) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Unclamped Inductive Switching Figure 6. Transfer Characteristics
Capability
30 2.5
VGS = 10V PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
VGS = 6V VGS = 5V 2.0
20
1.5
1.0
10 VGS = 4.5V
PULSE DURATION = 80 µ s 0.5
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 4.9A
TC = 25 [o] C
0 0
0 0.5 1.0 1.5 2.0 -80 -40 0 40 80 120 160
VDS, DRAIN TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 7. Saturation Characteristics Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.4 1.2
VGS = VDS, ID = 250 µ A ID = 250 µ A
1.2
1.1
1.0
0.8
1.0
0.6
0.4 0.9
-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Normalized Gate Threshold Voltage vs Figure 10. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
, DRAIN CURRENT (A)
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A) ON RESISTANCE
ID
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
**----- End of picture text -----**
©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 **==> picture [434 x 213] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristic (Continued)
5000 10
CISS = CGS + CGD VDD = 75V
8
1000
COSS ≅ CDS + CGD
6
CRSS = CGD
100 4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 4.9A
VGS = 0V, f = 1MHz ID = 1A
10
0
0.1 1 10 150
0 5 10 15 20 25 30 35
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
Figure 11. Capacitance vs Drain to Source Figure 12. Gate Charge Waveforms for Constant
Gate Currents
C, CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**==> picture [186 x 20] intentionally omitted <==** **----- Start of picture text -----**
Figure 11. Capacitance vs Drain to Source
Voltage
**----- End of picture text -----**
## **Test Circuits and Waveforms** **==> picture [429 x 160] intentionally omitted <==** **----- Start of picture text -----**
VDS BVDSS
tP
L VDS
IAS
VARY tP TO OBTAIN + VDD
REQUIRED PEAK IAS RG VDD
VGS -
DUT
tP
0V IAS 0
0.01 Ω
tAV
Figure 13. Unclamped Energy Test Circuit Figure 14. Unclamped Energy Waveforms
**----- End of picture text -----**
**==> picture [422 x 158] intentionally omitted <==** **----- Start of picture text -----**
VDS D1
VDD Qg(TOT)
VDS
L
VGS = 10V
VGS +
- VDD VGS
DUT VGS = 2V
Ig(REF) 0 Qgs2
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 15. Gate Charge Test Circuit Figure 16. Gate Charge Waveforms
**----- End of picture text -----**
©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## **Test Circuits and Waveforms** (Continued) **==> picture [429 x 140] intentionally omitted <==** **----- Start of picture text -----**
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 0 10%
**----- End of picture text -----**
**Figure 17. Switching Time Test Circuit** **Figure 18. Switching Time Waveforms** ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## _**Thermal Resistance vs. Mounting Pad Area**_ The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance R θ JA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. _PDM_ = (----------------------------- _TJMR_ – _TA_ ) (EQ. 1) θ _JA_ In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 19 or by calculation using Equation 2. The area, in square inches is the top copper area including the gate and source pads. _R_ θ _JA_ = 64 + -----------------------------0.23 26+ _Area_ (EQ. 2) The transient thermal impedance (Z θ JA) is also effected by varied top copper board area. Figure 20 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas. Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1. 4. The use of thermal vias. **==> picture [413 x 299] intentionally omitted <==** **----- Start of picture text -----**
5. Air flow and board orientation. 200
R θ JA = 64 + 26/(0.23+Area)
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the
part, the board and the environment they are in. 150
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 19
θ JA for the device as a function of the top for the device as a function of the top 100
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000
seconds of steady state power with no air flow. This 50
graph provides the necessary information for calculation
of the steady state junction temperature or power 0.001 AREA, TOP COPPER AREA (in0.01 0.1 [2] 1) 10
dissipation. Pulse applications can be evaluated using Figure 19. Thermal Resistance vs Mounting
the Fairchild device Spice thermal model or manually Pad Area
150
COPPER BOARD AREA - DESCENDING ORDER
0.04 in [2]
120 0.28 in [2]
0.52 in [2]
0.76 in [2]
90 1.00 in [2]
60
30
0
10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]
t, RECTANGULAR PULSE DURATION (s)
Figure 20. Thermal Impedance vs Mounting Pad Area
oC/W)( RJA θ
oC/W)
, THERMAL
ZJA θ
IMPEDANCE (
**----- End of picture text -----**
5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 19 defines the R θ JA for the device as a function of the top for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## _**PSPICE Electrical Model**_ .SUBCKT FDS2572 2 1 3 ; rev August 2001 CA 12 8 8e-10 Cb 15 14 8e-10 Cin 6 8 2e-9 **==> picture [336 x 270] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
5
51 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE RGATE + 18 - 6
1 9 20 22 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 157.4 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.98e-9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 19.8 Mstro 16 6 8 8 MstroMOD Mmed 16 6 8 8 MmedMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.1e-2 Rgate 9 20 1.47 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 1.5e-2 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*65),3))} .MODEL DbodyMOD D (IS=4e-11 N=1.131 RS=4.4e-3 TRS1=2e-3 TRS2=1e-6 + CJO=1.44e-9 M=0.67 TT=7.4e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.38 TRS1=2e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=5e-10 IS=1e-30 N=10 M=0.7) .MODEL MstroMOD NMOS (VTO=4.05 KP=85 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.35 KP=5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.47) .MODEL MweakMOD NMOS (VTO=2.76 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=14.7 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-3e-7) .MODEL RdrainMOD RES (TC1=1e-2 TC2=3e-5) .MODEL RSLCMOD RES (TC1=3e-3 TC2=1e-6) .MODEL RsourceMOD RES (TC1=4.5e-3 TC2=1e-6) .MODEL RvtempMOD RES (TC1=-5e-3 TC2=2e-6) .MODEL RvthresMOD RES (TC1=-3e-3 TC2=-1.4e-5) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-10 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-10) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.8) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## _**SABER Electrical Model**_ REV August 2001 template FDS2572 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=4e-11,nl=1.131,rs=4.4e-3,trs1=2e-3,trs2=1e-6,cjo=1.44e-9,m=0.67,tt=7.4e-8,xti=4.2) dp..model dbreakmod = (rs=0.38,trs1=2e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=5e-10,isl=10e-30,nl=10,m=0.7) m..model mstrongmod = (type=_n,vto=4.05,kp=85,is=1e-30, tox=1) **==> picture [431 x 287] intentionally omitted <==** **----- Start of picture text -----**
m..model mmedmod = (type=_n,vto=3.35,kp=5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.76,kp=0.05,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-10,voff=-2)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-10)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.3) LDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.8) DPLCAP 5 DRAIN
c.ca n12 n8 = 8e-10 2
10
c.cb n15 n14 = 8e-10 RLDRAIN
c.cin n6 n8 = 2e-9 RSLC1
51
RSLC2
dp.dbody n7 n5 = model=dbodymod ISCL
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod - 50 DBREAK
spe.ebreak n11 n7 n17 n18 = 157.4spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1 LGATE EVTEMPESG + 68 EVTHRES+ 198 - 21RDRAIN16 MWEAK11 DBODY
spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1 GATE1 9RGATE20+ 1822 - 6 MMED EBREAK+
spe.evtemp n20 n6 n18 n22 = 1 RLGATE MSTRO 17
i.it n8 n17 = 1 CIN 8 -18 7 LSOURCE SOURCE3
RSOURCE
l.lgate n1 n9 = 5.61e-9 RLSOURCE
l.ldrain n2 n5 = 1.0e-9l.lsource n3 n7 = 1.98e-9 12S1A13 14S2A 15 17 RBREAK 18
8 13
res.rlgate n1 n9 = 56.1 S1B S2B RVTEMP
res.rldrain n2 n5 = 10res.rlsource n3 n7 = 19.8 CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u - -
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u 8 22
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RVTHRES
**----- End of picture text -----**
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-3e-7 res.rdrain n50 n16 = 2.1e-2, tc1=1e-2,tc2=3e-5 res.rgate n9 n20 = 1.47 res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.5e-2, tc1=4.5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-3e-3,tc2=-1.4e-5 res.rvtemp n18 n19 = 1, tc1=-5e-3,tc2=2e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/65))** 3)) } ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## _**SPICE Thermal Model**_ REV August 2001 FDS2572 Copper Area = 1 in[2] CTHERM1 TH 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 2.0e-1 CTHERM7 3 2 1 CTHERM8 2 TL 3 RTHERM1 TH 8 1.0e-1 RTHERM2 8 7 5.0e-1 RTHERM3 7 6 1 RTHERM4 6 5 5 RTHERM5 5 4 8 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERM8 2 TL 25 ## _**SABER Thermal Model**_ Copper Area = 1 in[2] template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th c2 =2.0e-3 ctherm.ctherm2 c2 c3 =5.0e-3 ctherm.ctherm3 c3 c4 =1.0e-2 ctherm.ctherm4 c4 c5 =4.0e-2 ctherm.ctherm5 c5 c6 =9.0e-2 ctherm.ctherm6 c6 c7 =2.0e-1 ctherm.ctherm7 c7 c8 =1 ctherm.ctherm8 c8 tl =3 rtherm.rtherm1 th c2 =1.0e-1 rtherm.rtherm2 c2 c3 =5.0e-1 rtherm.rtherm3 c3 c4 =1 rtherm.rtherm4 c4 c5 =5 rtherm.rtherm5 c5 c6 =8 rtherm.rtherm6 c6 c7 =12 rtherm.rtherm7 c7 c8 =18 rtherm.rtherm8 c8 tl =25 } |**RTHERM6**
**RTHERM8**
**RTHERM7**
**RTHERM5**
**RTHERM4**
**RTHERM3**
**RTHERM2**
**RTHERM1**|**CTHERM4**
**CTHERM6**
**CTHERM5**
**CTHERM3**
**CTHERM2**
**CTHERM1**
**tl**
**2**
**3**
**4**
**5**
**6**
**7**
**JUNCTION**
**CASE**
**8**
**th**
**CTHERM7**
**CTHERM8**| |---|---| **TABLE 1. THERMAL MODELS** |**COMPONANT**|**0.04 in2**|**0.28 in2**|**0.52 in2**|**0.76 in2**|**1.0 in2**| |---|---|---|---|---|---| |CTHERM6|1.2e-1|1.5e-1|2.0e-1|2.0e-1|2.0e-1| |CTHERM7|0.5|1.0|1.0|1.0|1.0| |CTHERM8|1.3|2.8|3.0|3.0|3.0| |RTHERM6|26|20|15|13|12| |RTHERM7|39|24|21|19|18| |RTHERM8|55|38.7|31.3|29.7|25| ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## _**MS-012AA**_ ## **8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE** |**_MS-012AA_**
**12mm TAPE AND REEL**
**E**
**E1**
**D**
**L**
**h x 45o**
**2**
**5**
**6**
**0.155**
**4.0**
**0.275**
**7.0**
**0.060**
**1.52**
**MINIMUM RECOMMENDED FOOT**
**SURFACE-MOUNTED APPLIC**
**1**|||||**A**
**e**
**b**
**c**||**A1**
**4 IN**
**mm**
**1.5m**
**DIA. HO**|**m**
**LE**|||**SYMBOL**
**INCHES**
**MILLIMETERS**
**NOTES**
**MIN**
**MAX**
**MIN**
**MAX**
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of
Rev. C of JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protru-
sions or gate burrs. Mold flash, protrusions or gate
burrs shall not exceed 0.006 inches (0.15mm) per
side.
3. Dimension “E1” does not include inter-lead flash or
protrusions. Inter-lead flash and protrusions shall
not exceed 0.010 inches (0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not
present, a visual index feature must be located with-
in the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
**USER DIRECTION OF FEED**
**L**
**C**
**2.0mm**
**4.0mm**
**1.75mm**
**8.0mm**
**S ONLY.**
**ICATIONS.**
**330mm**
**50mm**
**13mm**
**18.4mm**
**12.4mm**
**ACCESS HOLE**
**40mm MIN.**|**SYMBOL**
**INCHES**
**MILLIMETERS**
**NOTES**
**MIN**
**MAX**
**MIN**
**MAX**
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
1. All dimensions are within allowable dimensions of
Rev. C of JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protru-
sions or gate burrs. Mold flash, protrusions or gate
burrs shall not exceed 0.006 inches (0.15mm) per
side.
3. Dimension “E1” does not include inter-lead flash or
protrusions. Inter-lead flash and protrusions shall
not exceed 0.010 inches (0.25mm) per side.
4. “L” is the length of terminal for soldering.
5. The chamfer on the body is optional. If it is not
present, a visual index feature must be located with-
in the crosshatched area.
6. Controlling dimension: Millimeter.
7. Revision 8 dated 5-99.
**USER DIRECTION OF FEED**
**L**
**C**
**2.0mm**
**4.0mm**
**1.75mm**
**8.0mm**
**S ONLY.**
**ICATIONS.**
**330mm**
**50mm**
**13mm**
**18.4mm**
**12.4mm**
**ACCESS HOLE**
**40mm MIN.**|**INCHES**|**INCHES**|**INCHES**|**MILLIMETERS**|**MILLIMETERS**|**NOTES**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |||**E**
**E1**||||||||||||||||| ||||||||||||||**MIN**|**MAX**||**MIN**|**MAX**|| ||**D**|**2**
**5**
**6**
**1**|||||||||||.0532|0.0688||1.35|1.75|-| ||||||||||||||0.004|0.0098||0.10|0.25|-| |||||||||||||||||||| ||||||||||||||0.013|0.020||0.33|0.51|-| |||||||||||||||||||| ||||||||||||||.0075|0.0098||0.19|0.25|-| ||||||||||||||0.189|0.1968||4.80|5.00|2| |||**h x 45o**||||||||||||||||| ||||||||||||||.2284|0.244||5.80|6.20|-| ||||||||||||||.1497|0.1574||3.80|4.00|3| |||**0.155**
**4.0**
**0.275**|||||||||||0.050 BSC|||1.27 BSC||-| ||||||**0o-8o**
**0.050**
**1.27**
**0.024**
**0.6**
**FOR**
**S**
**COVER TAPE**
**ENERAL INFOR**
**. 2500 PIECES PE**
**. ORDER IN MUL**
**. MEETS EIA-481**|**0.00**|**4 IN**|||||||||||| |||||||**0.10**|**mm**||||||.0099|0.0196||0.25|0.50|-| |||||||**MATI**
**R R**
**TIPL**
**REV**||||||||||||| ||||||||||||||0.016|0.050||0.40|1.27|4| |||||||||||||||||||| |||||||||||||||||||| |||||||||||||||||||| |||||||||||||||||||| |||||||||||||||||||| |||||||||||||||||||| |||||||||||||||||||| |||||||||||||||||||| |||||**PRINT**
**ATION**
**G**
**1**
**2**
**3**||||||||||||||| ||||||||**12mm**|||||||||||| |||||||||||||||||||| |||||||||||||||||||| ||||||||**ON**
**EEL.**
**ES OF FU**
**ISION “A**|**LL**
**” S**|**REEL**
**PECIF**||**8.0mm**
**S ONLY.**
**ICATIONS.**|||||||| ©2001 Fairchild Semiconductor Corporation FDS2572 Rev. C, July 2013 ## **TRADEMARKS** The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. |2Cool™
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~~-~~|FPS™
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