# Power MOSFET, N Channel, 250 V, 51 A, 0.048 ohm, TO-220F, Through Hole ![Product image](https://novapart.co/image/farnell:3616168/) **URL**: https://novapart.co/products/FDPF51N25RDTU/power-mosfet-n-channel-250-v-51-a-0048-ohm-to-220f **SKU**: FDPF51N25RDTU **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.1600 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | UniFET | | Qualification | - | | Power Dissipation | 38W | | Transistor Mounting | Through Hole | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-220F | | Drain Source Voltage Vds | 250V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 51A | | Drain Source On State Resistance | 0.048ohm | | Gate Source Threshold Voltage Max | 5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3616168/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [56 x 8] intentionally omitted <==** **----- Start of picture text -----**
March 2016
**----- End of picture text -----**
## **FDP51N25 / FDPF51N25 N-Channel UniFET[TM] MOSFET 250 V, 51 A, 60 m** Ω ## **Features** - RDS(on) = 48 m Ω (Typ.) @ VGS = 10 V, ID = 25.5 A - Low Gate Charge (Typ. 55 nC) - Low Crss (Typ. 63 pF) ## **Applications** - PDP TV - Lighting ## **Description** UniFET[TM] MOSFET is Fairchild Semiconductor’s high voltage MOSFET family based on planar stripe and DMOS technology. This MOSFET is tailored to reduce on-state resistance, and to provide better switching performance and higher avalanche energy strength. This device family is suitable for switching power converter applications such as power factor correction (PFC), flat panel display (FPD) TV power, ATX and electronic lamp ballasts. - Uninterruptible Power Supply - AC-DC Power Supply **D D D G GDS G G GDS S TO-220F S TO-220F TO-220 TO-220F Y-formed LG-formed S Absolute Maximum Ratings** TC = 25°C unless otherwise noted. **FDPF51N25 FDP51N25 FDPF51N25YDTU Symbol Parameter FDPF51N25RDTU Unit** ~~a~~ VDSS Drain-Source Voltage 250 V ID Drain Current - Continuous (TC = 25 ° C) 51 51* A - Continuous (TC = 100 ° C) 30 30* A IDM Drain Current - Pulsed (Note 1) 204 204* A ~~ee~~ VGSS Gate-Source voltage ~~ee ee~~ ± 30 V EAS Single Pulsed Avalanche Energy (Note 2) 1111 mJ IAR Avalanche Current (Note 1) 51 A EAR Repetitive Avalanche Energy (Note 1) 32 mJ VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=0.3sec; TC = 25 ° C) N/A 2500 V dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns PD Power Dissipation (TC = 25 ° C) 320 38 W - Derate Above 25 ° C 3.7 0.3 W/ ° C ~~es~~ TJ, TSTG Operating and Storage Temperature Range -55 to +150 ° C TL Maximum Lead Temperature for Soldering, 300 ° C 1/8” from Case for 5 Seconds ~~i | aa =4~~ *Drain current limited by maximum junction temperature. **Thermal Characteristics** **FDPF51N25 FDP51N25 FDPF51N25YDTU Symbol Parameter FDPF51N25RDTU Unit** R θ JC Thermal Resistance, Junction-to-Case, Max. 0.39 3.3 ° C/W ~~ft~~ R θ JA Thermal Resistance, Junction-to-Ambient, Max. 62.5 62.5 ° C/W www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation **1** FDP51N25 / FDPF51N25 Rev. 1.8 ## **Package Marking and Ordering Information** |**Electrical Characteristics**|**Electrical Characteristics**TC= 25°C unless otherwise noted.|= 25°C unless otherwise noted.||||| |---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |**Off Characteristics**||||||| |BVDSS|Drain-Source Breakdown Voltage|VGS= 0 V, ID= 250μA, TJ= 25°C|250|--|--|V| |ΔBVDSS
/ΔTJ|Breakdown Voltage Temperature
Coefficient|ID= 250μA, Referenced to 25°C|--|0.25|--|V/°C| |IDSS|Zero Gate Voltage Drain Current|VDS= 250 V, VGS= 0 V
VDS= 200 V, TC= 125°C|--
--|--
--|1
10|μA
μA| |IGSSF|Gate-Body Leakage Current, Forward|VGS= 30 V, VDS= 0 V|--|--|100|nA| |IGSSR|Gate-Body Leakage Current, Reverse|VGS= -30 V, VDS= 0V|--|--|-100|nA| |**On Characteristics**||||||| |VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= 250μA|3.0|--|5.0|V| |RDS(on)|Static Drain-Source
On-Resistance|VGS= 10 V, ID= 25.5 A|--|0.048|0.060|Ω| |gFS|Forward Transconductance|VDS= 40 V, ID= 25.5 A|--|43|--|S| |**Dynamic Characteristics**||||||| |Ciss|Input Capacitance|VDS= 25 V, VGS= 0 V,
f = 1 MHz|--|2620|3410|pF| |Coss|Output Capacitance||--|530|690|pF| |Crss|Reverse Transfer Capacitance||--|63|90|pF| |**Switching Characteristics**||||||| |td(on)|Turn-On Delay Time|VDD= 125 V, ID= 51 A,
VGS= 10 V, RG= 25Ω
(Note 4)|--|62|135|ns| |tr|Turn-On Rise Time||--|465|940|ns| |td(off)|Turn-Off Delay Time||--|98|205|ns| |tf|Turn-Off Fall Time||--|130|270|ns| |Qg|Total Gate Charge|VDS= 200 V, ID= 51 A,
VGS= 10 V
(Note 4)|--|55|70|nC| |Qgs|Gate-Source Charge||--|16|--|nC| |Qgd|Gate-Drain Charge||--|27|--|nC| |**Drain-Source Diode Characteristics and Maximum Ratings**||||||| |IS|Maximum Continuous Drain-Source Diode Forward Current||--|--|51|A| |ISM|Maximum Pulsed Drain-Source Diode Forward Current||--|--|204|A| |VSD|Drain-Source Diode Forward Voltage|VGS= 0 V, IS= 51 A|--|--|1.4|V| |trr|Reverse Recovery Time|VGS= 0 V, IS= 51 A,
dIF/dt =100 A/μs|--|178|--|ns| |Qrr|Reverse Recovery Charge||--|4.0|--|μC| ## **Electrical Characteristics** TC = 25°C unless otherwise noted. ## **Notes:** 1. Repetitive rating: pulse-width limited by maximum junction temperature. 2. L = 0.68 mH, IAS = 51 A, VDD = 50 V, RG = 25 Ω , starting TJ = 25 ° C. 3. ISD ≤ 51 A, di/dt ≤ 200 A/ μ s, VDD ≤ BVDSS, starting TJ = 25 ° C. 4. Essentially independent of operating temperature typical characteristics. www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation FDP51N25 / FDPF51N25 Rev. 1.8 **2** ## **Typical Performance Characteristics** **Figure 1. On-Region Characteristics** **Figure 2. Transfer Characteristics** **==> picture [436 x 559] intentionally omitted <==** **----- Start of picture text -----**
VGS
102 Top : 15.0 V 10.0 V 8.0 V 102
7.0 V
6.5 V
6.0 V
Bottom : 5.5 V
150oC
101 101 25 o C
-55oC
* Notes : 1. 250 2. TC = 25 μ s Pulse Test [o] C * Notes : 2. 2501. V DS = 40V μ s Pulse Test
10010-1 100 101 100 2 4 6 8 10 12
VDS, Drain-Source Voltage [V] VGS, Gate-Source Voltage [V]
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage Variation vs. Source Current
and Temperatue
0.14 102
0.12
0.10
VGS = 10V
0.08 101
0.06 VGS = 20V 150 o C
25 o C * Notes :
1. V GS = 0V
0.04 * Note : T J = 25 [o] C 2. 250 μ s Pulse Test
100
0 25 50 75 100 125 150 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
ID, Drain Current [A] VSD, Source-Drain voltage [V]
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
12
6000
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd 10 V DS = 50V
C rss = C gd VDS = 125V
4000 Coss 8 V DS = 200V
Ciss
6
4
2000
* Note ;
Crss 2. f 1. V=GS 1 MHz = 0 V 2
* Note : ID = 51A
0
0 0 10 20 30 40 50 60
10-1 100 101 QG, Total Gate Charge [nC]
VDS, Drain-Source Voltage [V]
, Drain Current [A]ID , Drain Current [A]ID
], Drain-Source On-Resistance
Ω , Reverse Drain Current [A]
[DS(ON) IDR
R
Capacitances [pF] , Gate-Source Voltage [V]
GS
V
**----- End of picture text -----**
**Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage** **Figure 5. Capacitance Characteristics** www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation FDP51N25 / FDPF51N25 Rev. 1.8 **3** **==> picture [454 x 229] intentionally omitted <==** **----- Start of picture text -----**
Typical Performance Characteristics (Continued)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
1.2 3.0
2.5
1.1
2.0
1.0 1.5
1.0
0.9 * Notes :
1. V2. IDGS = 250 = 0 V μ A 0.5 * Notes :1. VGS = 10 V
2. ID = 25.5 A
0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
TJ, Junction Temperature [oC] TJ, Junction Temperature [oC]
, (Normalized) , (Normalized)
DSS DS(ON)
BV R
Drain-Source On-Resistance
Drain-Source Breakdown Voltage
**----- End of picture text -----**
## **Figure 9-1. Maximum Safe Operating Area for FDP51N25** **Figure 9-2. Maximum Safe Operating Area for FDPF51N25 / FDPF51N25YDTU** **==> picture [414 x 339] intentionally omitted <==** **----- Start of picture text -----**
101021 -7 7 = esau estSeTS—TSTSSs.ae=~ ~ 100 ms Teye, 10 ms te 1 ms tS= 100 : _ μ s 10 se~.! μ s 4:!f ' 101021 ---j2<2- - ~eA<7~Sie-<0ban+.==—ws==_—7A.Aare 10 ms1 ms as~S.bars 100 10 μ _— s μ s
Operation in This Area eT DC SStk!tS <. 100 ms _ >. ~S
100 is Limited by R DS(on) Se~! 100 Operation in This Area is Limited by R DS(on) DC ~. ~L >.
* Notes :
10-1 1. T3. Single Pulse2. TC J = 150 = 25 o CoC 10-1 * Notes : 12. T. TCJ = 150 = 25 oCoC
3. Single Pulse
10-2100 101 102 10-2100 101 102
VDS, Drain-Source Voltage [V] VDS, Drain-Source Voltage [V]
Figure 10. Maximum Drain Current
vs. Case Temperature
60
50
40
30
20
10
0
25 50 75 100 125 150
TC, Case Temperature [oC]
, Drain Current [A]ID , Drain Current [A]ID
, Drain Current [A]ID
**----- End of picture text -----**
## **Figure 10. Maximum Drain Current vs. Case Temperature** www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation FDP51N25 / FDPF51N25 Rev. 1.8 **4** ## **Typical Performance Characteristics (Continued)** **Figure 11-1. Transient Thermal Response Curve for FDP51N25** **==> picture [247 x 133] intentionally omitted <==** **----- Start of picture text -----**
D=0.5
10 -1 0.2
0.1
0.05 PDM
t 1
0.02 t2
10 -2 0.01 * Notes : 1. Z θ JC(t) = 0.39 0C/W Max.
2. Duty Factor, D=t1/t2
single pulse 3. T JM - T C = P DM * Z θ JC (t)
10 -5 10-4 10 -3 10 -2 10 -1 10 0 10 1
t1, Square W ave Pulse Duration [sec]
oC/W](t), Thermal Response
(t), Thermal Response [ZZJC θ JC θ
**----- End of picture text -----**
**Figure 11-2. Transient Thermal Response Curve for FDPF51N25 / FDPF51N25YDTU** **==> picture [242 x 144] intentionally omitted <==** **----- Start of picture text -----**
D=0.5
100
0.2
0.1
0.05 P DM
t1
10-1 0.02 t 2
* Notes :
0.01 1. Z θ JC (t) = 3.3 0 C/W Max.
2. Duty Factor, D=t1/t2
single pulse 3. TJM - TC = PDM * Z θ JC(t)
10-2
10-5 10-4 10-3 10-2 10-1 100 101
t1, Square Wave Pulse Duration [sec]
oC/W](t), Thermal Response [(t), Thermal Response
ZZJC θ JC θ
**----- End of picture text -----**
www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation FDP51N25 / FDPF51N25 Rev. 1.8 **5** **==> picture [432 x 521] intentionally omitted <==** **----- Start of picture text -----**
VGS
Same Type
50KΩ as DUT Qg
12V 200nF 300nF 10V
VGS VDS Qgs Qgd
DUT
IG = const. 3mA
Charge
Figure 12. Gate Charge Test Circuit & Waveform
VDS RL VDS 90%
VGS VDD
RG
10%
V 10V GS DUT VGS
td(on) tr td(off) tf
t on t off
Figure 13. Resistive Switching Test Circuit & Waveforms
VDS L EAS = ----12 L IAS2 --------------------BVBVDSSDSS- VDD
I D BVDSSIAS
RG VDD ID (t)
VV 10V GSGS DUT VDD VDS (t)
t p t p Time
**----- End of picture text -----**
**Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms** www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation FDP51N25 / FDPF51N25 Rev. 1.8 **6** **==> picture [335 x 547] intentionally omitted <==** **----- Start of picture text -----**
DUT +
VDS
_
I SD
L
Driver
RG
Same Type
as DUT VDD
VGS • dv/dt controlled by RG
• ISD controlled by pulse period
Gate Pulse Width
VGS D = --------------------------
Gate Pulse Period 10V
( Driver )
ff}
IFM , Body Diode Forward Current
I SD
( DUT ) di/dt
IRM
4 Ne
Body Diode Reverse Current
VDS
( DUT ) Body Diode Recovery dv/dt
VSD VDD
eerie
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
**----- End of picture text -----**
www.fairchildsemi.com ©2008 Fairchild Semiconductor Corporation FDP51N25 / FDPF51N25 Rev. 1.8 **7** **==> picture [484 x 490] intentionally omitted <==** **----- Start of picture text -----**
10.36 2.66
A B B
9.96 2.42
3.28
3.40 7.00 0.70
3.08
3.20
6.88
6.48
1 X 45° 16.07
B
15.67
R1.00
2.96
1 3 2.56
1.47 8.50
B
1.24 7.50
R1.00
0.90
2.14
0.70 0.60
4.50 B
0.50 [M] A B 0.45
3.50
4.80
2.54 2.54
B
4.20
4.90
B
4.50
**----- End of picture text -----**
NOTES: - A. EXCEPT WHERE NOTED CONFORMS TO EIAJ SC91A. - B DOES NOT COMPLY EIAJ STD. VALUE. - C. ALL DIMENSIONS ARE IN MILLIMETERS. - D. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS. - E. DIMENSION AND TOLERANCE AS PER ASME Y14.5-1994. - F. DRAWING FILE NAME: TO220N03REV2 **==> picture [539 x 526] intentionally omitted <==** **----- Start of picture text -----**
10.36 2.66
A B B
9.96 2.42
3.28
3.40 7.00
3.08 0.70
3.20
6.88
6.48
1 X 45° 16.07
B
15.67
16.00
15.60
R0.30 2.96
1 3
R0.30 2.56
1.47
1.24
10.45
B 10.00
2.14 9.45 B
9.00
0.90
0.70
0.50 [M] A
0.60
B
0.45
B 4.00 MIN
2.54 2.54
6.00
B
4.00
4.90
B
4.50
**----- End of picture text -----**
NOTES: - A. EXCEPT WHERE NOTED CONFORMS TO EIAJ SC91A. - B DOES NOT COMPLY EIAJ STD. VALUE. - C. ALL DIMENSIONS ARE IN MILLIMETERS. - D. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR PROTRUSIONS. - E. DIMENSION AND TOLERANCE AS PER ASME Y14.5-1994. - F. DRAWING FILE NAME: TO220Q03REV2 **==> picture [592 x 749] intentionally omitted <==** **----- Start of picture text -----**
SUPPLIER "B" PACKAGE
SHAPE �����
3.50
10.67
SUPPLIER "A" PACKAGE 9.65 E
SHAPE
3.40
2.50
16.30
IF PRESENT, SEE NOTE "D" 13.90
E
16.51 9.40
15.42
8.13 E
1 2 3
[2.46] C 2.704.10
14.04
2.13 12.70
2.06
FRONT VIEWS
4.70 1.62 1.62
4.00 1.42 [ H] 2.67 1.10
2.40
"A1" 8.65 1.00
SEE NOTE "F" 7.59 0.55
�� ��
OPTIONAL 6.69 �� ��
6.06
CHAMFER
E
14.30
11.50
NOTE "I" BOTTOM VIEW
NOTES:
A) REFERENCE JEDEC, TO-220, VARIATION AB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS COMMON TO ALL PACKAGE
SUPPLIERS EXCEPT WHERE NOTED [ ].
3 2 1 D) LOCATION OF MOLDED FEATURE MAY VARY
(LOWER LEFT CORNER, LOWER CENTER
AND CENTER OF THE PACKAGE)
E DOES NOT COMPLY JEDEC STANDARD VALUE.
F) "A1" DIMENSIONS AS BELOW:
SINGLE GAUGE = 0.51 - 0.61
DUAL GAUGE = 1.10 - 1.45
G) DRAWING FILE NAME: TO220B03REV9
H PRESENCE IS SUPPLIER DEPENDENT
I) SUPPLIER DEPENDENT MOLD LOCKING HOLES
IN HEATSINK.
0.60
0.36 2.85 BACK VIEW
2.10
SIDE VIEW
**----- End of picture text -----**
**==> picture [566 x 759] intentionally omitted <==** **----- Start of picture text -----**
10.36 2.66
A B B
9.96 2.42
3.28
3.40 7.00 3.08
0.70
3.20
SEE NOTE "F" SEE NOTE "F"
6.88
6.48
1 X 45°
16.07
B
15.67
16.00
15.60
(3.23) B
3
1
1.47
2.96
2.14 1.24
2.56
0.90
10.05 0.70
9.45 0.50 [M] A
30°
0.45
0.60
0.25 B
0.45
2.54 2.54
4.90
B
4.50
NOTES:
A. EXCEPT WHERE NOTED CONFORMS TO
EIAJ SC91A.
B DOES NOT COMPLY EIAJ STD. VALUE.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
D. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS.
E. DIMENSION AND TOLERANCE AS PER ASME
Y14.5-1994.
F. OPTION 1 - WITH SUPPORT PIN HOLE.
OPTION 2 - NO SUPPORT PIN HOLE.
G. DRAWING FILE NAME: TO220M03REV5
**----- End of picture text -----**
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