# Dual MOSFET, N Channel, 25 V, 88 A, 0.007 ohm

![Product image](https://novapart.co/image/farnell:3616900/)

**URL**: https://novapart.co/products/FDPC8012S/dual-mosfet-n-channel-25-v-88-a-0007-ohm
**SKU**: FDPC8012S
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Dual MOSFETs
**Price**: €0.3600
**Stock**: 10+
**Lead Time**: 148 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | Lead (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Transistor Case Style | PQFN |
| Operating Temperature Max | 150°C |
| Power Dissipation N Channel | 2W |
| Power Dissipation P Channel | - |
| Drain Source Voltage Vds N Channel | 25V |
| Drain Source Voltage Vds P Channel | - |
| Continuous Drain Current Id N Channel | 88A |
| Continuous Drain Current Id P Channel | - |
| Drain Source On State Resistance N Channel | 0.007ohm |
| Drain Source On State Resistance P Channel | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3616900/)

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## MOSFET – Dual, N-Channel, Asymmetric, POWERTRENCH , Power Clip, 25 V FDPC8012S 

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LSGV+ Pin 1<br>GND V+<br>GND<br>GND (HSD)<br>(LSS)<br>HSG<br>SW<br>SW<br>Os SW<br>Top Bottom<br>PQFN8 3.3X3.3, 0.65P<br>CASE 483AZ<br>**----- End of picture text -----**<br>


## **General Description** 

This device includes two specialized N−Channel MOSFETs in a dual package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET (Q2) have been designed to provide optimal power efficiency. 

## **Features** 

Q1: N−Channel 

- Max RDS(on) = 7.0 m at VGS = 4.5 V, ID = 12 A 

Q2: N−Channel 

## **MARKING DIAGRAM** 

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&Z&3&K<br>01OD<br>03OD<br>&Z = Assembly Plant Code<br>&3 = 3−Digit Date Code<br>&K = 2−Digits Lot Run Traceability Code<br>01OD03OD = Device Code<br>**----- End of picture text -----**<br>


- Max RDS(on) = 2.2 m at VGS = 4.5 V, ID = 23 A 

- Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses 

- MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing 

- RoHS Compliant 

## **Applications** 

- Computing 

## **PIN ASSIGNMENT** 

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PAD9 Q1<br>HSG 1 V+(HSD) 8 V+ HSG 1 8 V+<br>SW 2 7 LSG SW 2 7 LSG<br>SW<br>SW 3 6 GND SW 3 6 GND<br>PAD10<br>SW 4 GND(LSS) 5 GND SW 4 5 GND<br>Q2<br>**----- End of picture text -----**<br>


- Communications 

- General Purpose Point of Load 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 13 of this data sheet. 

Publication Order Number: **FDPC8012S/D** 

**1** 

© Semiconductor Components Industries, LLC, 2012 **July, 2024 − Rev. 3** 

**FDPC8012S** 

**MOSFET MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) 

|**MOSFET MAXIMUM RATINGS**|**MOSFET MAXIMUM RATINGS**(TA = 25A = 25= 25°C unless otherwise noted)|**MOSFET MAXIMUM RATINGS**(TA = 25A = 25= 25°C unless otherwise noted)||||
|---|---|---|---|---|---|
|**Symbol**|**Parameter**||**Q1**|**Q2**|**Unit**|
|VDS|Drain to Source Voltage||25|25|V|
|VGS|Gate to Source Voltage||12|12|V|
|ID|Drain Current|−Continuous TC= 25°C|35|88|A|
|||−Continuous TA= 25°C|13 (Note 1a)|26 (Note 1b)||
|||−Pulsed (Note 4)|40|120||
|EAS|Single Pulse Avalanche Energy (Note 3)||50|181|mJ|
|PD|Power Dissipation for Single<br>Operation|TA= 25°C|1.6 (Note 1a)|2.0 (Note 1b)|W|
|||TA= 25°C|0.8 (Note 1c)|0.9 (Note 1d)||
|TJ,TSTG|Operating and Storage Junction Temperature Range||−55 to +150||°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

**THERMAL CHARACTERISTICS** 

|**Symbol**<br>~~a~~|**Characteristic**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|
|R JA<br>~~a~~|Thermal Resistance, Junction to Ambient|77 (Note 1a)|63 (Note 1b)|°C/W|
|R JA|Thermal Resistance, Junction to Ambient|151 (Note 1c)|135 (Note 1d)||
|R JC<br>~~a~~|Thermal Resistance, Junction to Case|5.0|3.5||



**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**Symbol**<br>**Parameter**<br>**Test Condition**<br>**Type**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**OFF CHARACTERISTICS**<br>~~aDG~~<br>~~GO~~|
|---|
|BVDSS<br>Drain to Source Breakdown Voltage<br>ID= 250 A, VGS= 0 V<br>ID= 1 mA, VGS= 0 V<br>Q1<br>Q2<br>25<br>25<br>−<br>−<br>−<br>−<br>V<br>BVDSS<br>TJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250 A, referenced to 25°C<br>ID= 10 mA, referenced to 25°C<br>Q1<br>Q2<br>−<br>−<br>18<br>22<br>−<br>−<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 20 V, VGS= 0 V<br>VDS= 20 V, VGS= 0 V<br>Q1<br>Q2<br>−<br>−<br>−<br>−<br>1<br>500<br>A<br>IGSS<br>Gate to Source Leakage Current,<br>Forward<br>VGS= 12 V/−8 V, VDS= 0 V<br>VGS= 12 V/−8 V, VDS= 0 V<br>Q1<br>Q2<br>−<br>−<br>−<br>−<br>±100<br>±100<br>nA<br>**ON CHARACTERISTICS**<br>~~ee ee ee ee eee~~<br>~~aee~~<br>~~ee ee eee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~ee~~<br>~~ee ee~~|
|VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS, ID= 250 A<br>VGS= VDS, ID= 1 mA<br>Q1<br>Q2<br>0.8<br>1.1<br>1.3<br>1.6<br>2.2<br>2.2<br>V<br>VGS(th)<br>TJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= 250 A, referenced to 25°C<br>ID= 10 mA, referenced to 25°C<br>Q1<br>Q2<br>−<br>−<br>−4<br>−4<br>−<br>−<br>mV/°C<br>RDS(on)<br>Drain to Source On Resistance<br>VGS= 4.5 V, ID= 12 A<br>VGS= 4.5 V, ID= 12 A, TJ= 125°C<br>Q1<br>−<br>−<br>5.2<br>7.5<br>7.0<br>10.5<br>m<br>VGS= 4.5 V, ID= 23 A<br>VGS= 4.5 V, ID= 23 A ,TJ= 125°C<br>Q2<br>−<br>−<br>1.6<br>2.3<br>2.2<br>3.2<br>gFS<br>Forward Transconductance<br>VDS= 5 V, ID= 13 A<br>VDS= 5 V, ID= 26 A<br>Q1<br>Q2<br>−<br>−<br>79<br>200<br>−<br>−<br>S<br>**DYNAMIC CHARACTERISTICS**<br>~~ee~~<br>~~ee~~<br>~~ee ee eee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~pf eo~~<br>~~ee ee eee ee~~<br>~~ee~~|
|Ciss<br>Input Capacitance<br>Q1:<br>VDS= 13 V, VGS= 0 V, f = 1 MHz<br>Q2:<br>VDS= 13 V, VGS= 0 V, f = 1 MHz<br>Q1<br>Q2<br>−<br>−<br>1075<br>3456<br>−<br>−<br>pF<br>Coss<br>Output Capacitance<br>Q1<br>Q2<br>−<br>−<br>250<br>885<br>−<br>−<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>Q1<br>Q2<br>−<br>−<br>50<br>130<br>−<br>−<br>pF<br>Rg<br>Gate Resistance<br>Q1<br>Q2<br>0.1<br>0.1<br>0.4<br>0.5<br>2.0<br>2.0<br>~~pe~~<br>~~P|~~<br>~~| tt~~<br>~~ee~~<br>~~P|~~<br>~~**|** tt~~<br>~~Po~~<br>~~P|~~<br>~~ft~~<br>~~ee~~<br>~~ee ee~~|
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**FDPC8012S** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) (continued) 

|**ELECTRICAL CHARACTERISTICS**(TJ = 25J = 25= 25°C unless otherwise noted) (continued)|C unless otherwise noted) (continued)|C unless otherwise noted) (continued)|C unless otherwise noted) (continued)|||
|---|---|---|---|---|---|
|**Symbol**<br>**Test Condition**<br>**Parameter**|||**Max**<br>**Typ**<br>**Min**<br>**Type**||**Unit**|
|**SWITCHING CHARACTERISTICS**||||||
|td(on)<br>Turn−On Delay Time<br>Q1:<br>VDD= 13 V, ID= 13 A, RGEN= 6<br>Q2:<br>VDD= 13 V, ID= 26 A, RGEN= 6<br>tr<br>Rise Time<br>~~Pf~~<br>~~Pf~~|= 6<br>= 6|= 6<br>= 6<br>o<br>a|Q1<br>Q2<br>−<br>−<br>6<br>12<br>−<br>−<br>Q1<br>Q2<br>−<br>−<br>2<br>3<br>−<br>−<br>~~|~~<br>~~|~~<br>~~|~~<br>~~| ~~<br>a|ns<br>ns<br> ~~|~~||
|td(off)<br>Turn−Off Delay Time|||Q1<br>Q2<br>−<br>−<br>19<br>34<br>−<br>−||ns|
|tf<br>Fall Time|||Q1<br>−<br>2<br>−||ns|
||||Q2<br>−<br>3<br>−|||
|Qg<br>Total Gate Charge<br>VGS= 0 V to 4.5 V<br>Q1:<br>VDD= 13 V, I|= 13 V, I|= 13 V, ID|D= 13 A<br>Q1<br>Q2<br>−<br>−<br>8<br>25<br>−<br>−||nC|
|Qgs<br>Gate to Source Gate Charge<br>Q2:<br>VDD= 13 V, I|= 13 V, I|= 13 V, ID|D= 26 A<br>Q1<br>Q2<br>−<br>−<br>2.3<br>7.8<br>−<br>−||nC|
|Qgd<br>Gate to Drain “Miller” Charge|||Q1<br>Q2<br>−<br>−<br>2.0<br>6.4<br>−<br>−||nC|
|**DRAIN−SOURCE CHARACTERISTICS**||||||
|VSD<br>Source to Drain Diode Forward<br>VGS= 0 V, IS= 13 A (Note 2)|||Q1<br>−<br>0.8<br>1.2||V|
|Voltage<br>VGS= 0 V, IS= 26 A (Note 2)|||Q2<br>−<br>0.8<br>1.2|||
|trr<br>Reverse Recovery Time<br>Q1:<br>IF= 13 A, di/dt = 100 A/ s<br>Q2:<br>IF= 26 A, di/dt = 300 A/ s<br>Qrr<br>Reverse Recovery Charge<br>~~Sf~~<br>~~Pf~~|||Q1<br>Q2<br>−<br>−<br>20<br>27<br>35<br>43<br>ns<br>Q1<br>Q2<br>−<br>−<br>6<br>27<br>12<br>43<br>nC<br>~~{|~~<br>ft ft ~~|~~<br>~~Ff~~<br>~~ft~~<br>~~ft~~<br>~~|~~|||
|Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product||||||
|performance may not be indicated by the Electrical Characteristics if operated under different conditions.||||||
|NOTES:||||||
|1. R JAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R<br>~~00~~|pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R<br>~~00~~|pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R JCis guaranteed<br>~~00~~||||
|by design while R CAis determined by the user’s board design.<br>0||||||
|a. 77°C/W when mounted on|||b. 63°C/W when mounted on|||
|a 1 in2pad of 2 oz copper|||a 1 in2pad of 2 oz copper|||
|00000<br>00000||||||
|G<br>DF<br>DS<br>SF<br>SS<br>G<br>DF<br>DS|SF<br>SS|||||
|c. 151°C/W when mounted on a<br>minimum pad of 2 oz copper<br>S<br>Ay|||d. 135°C/W when mounted on a<br>minimum pad of 2 oz copper|||
|00000<br>00000||||||
|G<br>DF<br>DS<br>SF<br>SS<br>G<br>DF<br>DS||SF<br>SS||||



2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%. uw 

3. Q1: EAS of 50 mJ is based on starting TJ = 25 ° C; N−ch: L = 3 mH, IAS = 5.8 A, VDD = 25 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 14.5 A. Q2: EAS of 181 mJ is based on starting TJ = 25 ° C; N−ch: L = 3 mH, IAS = 11 A, VDD = 25 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 32.9 A. 

4. Pulsed Id limited by junction temperature, td ≤ 10 s. Please refer to SOA curve for more details. u 

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## **TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)** (TJ = 25 ° C unless otherwise noted) 

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40 5<br>VGS = 10 V VGS = 2.5 V<br>VGS = 4.5 V<br>32 HF VGS = 3.5 V | 4 LLY PULSE DURATION = 80 s<br>VGS = 3 V DUTY CYCLE = 0.5% MAX<br>a ee<br>24 3<br>VGS = 3 V<br>16 yeej| tea VGS = 2.5 V -| 2 | }|<br>8 1<br>PULSE DURATION = 80 s VGS = 3.5 V VGS = 4.5 V VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>Y)|<br>0 | tt 0 EL<br>0.0 0.2 0.4 0.6 0.8 1.0 0 8 16 24 32 40<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>ON−RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

**Figure 2. Normalized On−Resistance vs. Drain Current and Gate Voltage** 

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1.6 30<br>ID = 13 A PULSE DURATION = 80 s<br>VGS = 10 V ID = 13 A DUTY CYCLE = 0.5% MAX<br>TTA 25<br>1.4<br>20<br>1.2<br>rrr *  fe<br>15<br>1.0<br>Hiatt 10 a<br>TJ = 125 ° C<br>0.8<br>ee 5 Se eee<br>TJ = 25 ° C<br>0.6 PTE EEE L LE ) 0 =o<br>−75 −50 −25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( ° C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. Normalized On−Resistance vs.  Figure 4. On−Resistance vs. Gate to Source Voltage<br>Junction Temperature<br>40 100<br>VDS = 5 V VGS = 0 V<br>32 ie ee 10 ——__.__--—<br>PULSE DURATION = 80 s<br>DUTY CYCLE = 0.5% MAX<br>ee<br>24 1<br>TJ = 150 ° C TJ = 150 ° C T J  = 25 ° C<br>16 0.1<br>TJ = 25 ° C TJ = −55 ° C<br>8 0.01<br>TJ = −55 ° C<br>0 0.001<br>i) ee e e ==.=<br>0 1 2 3 4 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs.<br>)<br>, DRAIN TO SOURCE<br>ON−RESISTANCE ON−RESISTANCE (m<br>DS(on)<br>R<br>NORMALIZED DRAIN TO SOURCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 6. Source to Drain Diode Forward Voltage vs. Source Current** 

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**FDPC8012S** 

## **TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)** (TJ = 25 ° C unless otherwise noted) (continued) 

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10 5000<br>ID = 13 A Va /] AEH<br>VDD = 10 V<br>8 ae a a a Ciss<br>1000<br>VDD = 13 V<br>6 ae WA, 40 eea_-.a =:ee eS C oss [|<br>VDD = 15 V<br>4<br>A 100 TIES<br>Crss<br>2 a Eeee<br>f = 1 MHz<br>VGS = 0 V<br>0 Yi | | | ft } 10 RHEee ee eee<br>0 4 8 12 16 20 0.1 1 10 25<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Gate Charge Characteristics** 

**Figure 8. Capacitance vs. Drain to Source Voltage** 

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**----- Start of picture text -----**<br>
50 60<br>a TT R JC = 5.0 ° C/W<br>Po TTT TTT<br>48<br>LUISA ETT PT VGS = 10 V<br>10 CLM SOTAPSSST TT Il 36 ieeeeee<br>eee T J  = 100 EHH ° C HH eo<br>VGS = 4.5 V<br>YT PT TT T TTeHT eet,TT TTT TJ TTT  = 125 ensNBSPTORU ° NNT C TTTanTT T TJ TT]ET  = 25 TT) ° C TT 24 w Limited by Package eIw NX<br>0 NN 12 ee ee Ne<br>Beni HOUT /ONQUIVI@BOSS( (NBII .<br>1 ETI [LI] [EEN] [DS] OTM =  EL 0<br>0.001 0.01 0.1 1 10 100 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE ( ° C)<br>Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs.<br>Case Temperature<br>100 1000<br>100 s<br>Pe TT TT ET TT<br>10 E| We SPN PTET EY UH 100 ETAT UIT PATTITIENT<br>LZ TTT TSP ST SPST SET PE<br>1 THIS AREA IS 1 ms 10<br>a LIMITED BY RDS(on) ee ae 10 ms100 ms LUI TIT SUTIN<br>Prem HEE BS 4 FE EHCHCHSSC<br>SINGLE PULSE 1 s<br>0.1 TJ = MAX RATED 10 s 1 SINGLE PULSE<br>R JA = 151 ° C/W DERIVED FROM DC R JA = 151 ° C/W<br>0.01 TE T A  = 25 ° C ee TEST DATA ta [| ttTT 0.1 ETI TA = 25 ° VU C TATeeeeEIN aUSTa<br>0.01 0.1 1 10 100 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1] 100 1000<br>VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>, DRAIN CURRENT (A)<br>, AVALANCHE CURRENT (A) ID<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>, PEAK TRANSIENT POWER (W)<br>PK)<br>P(<br>**----- End of picture text -----**<br>


**Figure 11. Forward Bias Safe Operating Area** 

**Figure 12. Single Pulse Maximum Power Dissipation** 

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**TYPICAL CHARACTERISTICS (Q1 N−CHANNEL)** (TJ = 25 ° C unless otherwise noted) (continued) 

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2<br>DUTY CYCLE−DESCENDING ORDER<br>1<br>eS——_--...SN NS————__--.._-.SS SS SS SS i es===...SS ON SS—_ __-...——Se = = ce RS _OO OS neeSG OO<br>D = 0.5 aA 0 8HS OO 0 SR NN8ONO 0 i oo 0 a<br>0.1 0.2 0.1 0.05 Mo1eeSS || eee TT  ce eeeeeieSo| PDM || ||H<br>ry CS eee eee ree eee a<br>0.02 a a a ss ee es a<br>0.01 aa 09 a a t 1 | i|<br>t2<br>0.01 Pole_—Saasee oe oe oo oo TNT SINGLE PULSE SEee NOTES: —_ <— | | 4<br>aeS A Oea R JA = 151 ° C/W aeeA OO OO || DUTY FACTOR: D = t1 / t2 a]a<br>}—_| 1 Pritt (Note 1c) PET PEAK T J  = P DM  x Z JA  x R JA  + T A [|<br>0.001 Lx Toi Coes<br>fan) 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1] 100 1000<br>t, RECTANGULAR PULSE DURATION (s)<br>, NORMALIZED THERMAL IMPEDANCE<br>JA<br>Z<br>**----- End of picture text -----**<br>


**Figure 13. Junction−to−Ambient Transient Thermal Response Curve** 

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## **TYPICAL CHARACTERISTICS (Q2 N−CHANNEL)** (TJ = 25 ° C unless otherwise noted) 

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120 5<br>VGS = 10 V PULSE DURATION = 80 s<br>DUTY CYCLE = 0.5% MAX<br>VGS = 4.5 V 4<br>90<br>VGS = 4 V VGS = 3 V<br>VGS = 3.5 V 3<br>VGS = 3 V<br>60<br>fe 2 =<br>VGS = 3.5 V<br>30<br>1<br>=== PULSE DURATION = 80 s VGS = 4 V VGS = 4.5 V VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>es<br>0 0<br>0.0 0.2 0.4 0.6 0.8 0 30 60 90 120<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 14. On−Region Characteristics Figure 15. Normalized On−Resistance vs.<br>Drain Current and Gate Voltage<br>1.6 8<br>ID = 26 A PULSE DURATION = 80 s<br>VGS = 10 V ID = 26 A DUTY CYCLE = 0.5% MAX<br>1.4<br>6<br>1.2 4 |<br>4<br>1.0<br>PCopeRET AU TJ = 125 ° C<br>2<br>0.8<br>coerpe FAN TJ = 25 ° C<br>0.6 0<br>−75 SPEC) −50 −25 0 25 50 75 100 125 150 = 2 COPE 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( ° C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 16. Normalized On−Resistance vs.  Figure 17. On−Resistance vs. Gate to Source Voltage<br>Junction Temperature<br>120 200<br>PULSE DURATION = 80 s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>es<br>100<br>VDS = 5 V 10<br>80 a ————— T J  = 125 ° C<br>TJ = 125 ° C 1<br>60<br>TJ = 25 ° C 0.1 T J  = 25 ° C<br>40<br>TJ = −55 ° C 0.01 T J  = −55 ° C<br>20<br>0 0.001<br>1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.2 0.4 0.6 0.8 1.0<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage<br>ON−RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>NORMALIZED DRAIN TO SOURCE<br>)<br>, DRAIN TO SOURCE<br>ON−RESISTANCE ON−RESISTANCE (m<br>DS(on)<br>R<br>NORMALIZED DRAIN TO SOURCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 19. Source to Drain Diode Forward Voltage<br>vs. Source Current<br>**----- End of picture text -----**<br>


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**FDPC8012S** 

## **TYPICAL CHARACTERISTICS (Q2 N−CHANNEL)** (TJ = 25 ° C unless otherwise noted) (continued) 

**==> picture [484 x 383] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 10000<br>ID = 26 A<br>VDD = 10 V Ciss<br>8<br>VDD = 13 V W,y [x] 1000 ss—— eeeeee Coss<br>6<br>4 } VDD = 15 V Crss<br>100<br>2 | Afff Ato A<br>f = 1 MHz<br>VGS = 0 V<br>Ze SY PLE eeEETOO<br>0 10<br>0 12 24 36 48 60 0.1 1 10 25<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain to Source Voltage<br>300 120<br>100 MMT 96 Eee<br>pf TENNIS Se<br>CO eS 72 pf | [[™aY]]<br>TJ = 100 ° C VGS = 10 VGS = 10 V = 10 V<br>Limited by Package<br>10 TCSLu 48 =kOROR<br>rT Tt rT T TTT J = 125 ° C TT TTT WN NUTT TJ = 25 ° TT C TTT] R JC = 3.5 = 3.5 ° C/W VGS = 4.5 VGS = 4.5 V = 4.5 V<br>24<br>1 ESSLETPTET PTETUTI LEIAUTSNINA TTT 0 ee ee\\<br>0.001 0.01 0.1 1 10 100 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (C, CASE TEMPERATURE (, CASE TEMPERATURE ( ° C)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)<br>, AVALANCHE CURRENT (A) IDD<br>IAS<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
120<br>96 Eee<br>72 pf | [[™aY]]<br>VGS = 10 VGS = 10 V = 10 V<br>Limited by Package<br>48 =kOROR<br>R JC = 3.5 = 3.5 ° C/W VGS = 4.5 VGS = 4.5 V = 4.5 V<br>24<br>0 ee ee\\<br>25 50 75 100 125 150<br>TC, CASE TEMPERATURE (C, CASE TEMPERATURE (, CASE TEMPERATURE ( ° C)<br>Figure 23. Maximum Continuous Drain Current vs.<br>Case Temperature<br>10000<br>1000 ee<br>PTINET<br>100<br>10 OEE TEE SRI CI STE<br>1 SINGLE PULSE<br>R JA = 135 ° C/W<br>TA = 25 ° C<br>0.1 Ca Cc oe<br>10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1] 100 1000<br>t, PULSE WIDTH (s)<br>, DRAIN CURRENT (A)<br>IDD<br>, PEAK TRANSIENT POWER (W)<br>PK)<br>P(<br>**----- End of picture text -----**<br>


**Figure 22. Unclamped Inductive Switching Capability** 

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200<br>100<br>Pa ATS HH 100 s<br>10 ee SSS SSS SS: = = ===:<br>1 ms<br>1 THIS AREA IS 10 ms<br>. LIMITED BY RDS(on) 100 ms<br>SINGLE PULSE 1 s<br>0.1 TJ = MAX RATED 10 s<br>TRA = 25JA = 135 ° C ° C/W DERIVED FROMTEST DATA DC<br>0.01 Fee eH<br>0.01 0.1 1 10 100<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 24. Forward Bias Safe Operating Area** 

**Figure 25. Single Pulse Maximum Power Dissipation** 

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**FDPC8012S** 

## **TYPICAL CHARACTERISTICS (Q2 N−CHANNEL)** (TJ = 25 ° C unless otherwise noted) (continued) 

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2<br>1 SNe DUTY CYCLE−DESCENDING ORDER<br>0 |<br>D = 0.5 Aert<br>0.2 a rm<br>0.1 0.1 hnne<br>0.05 Sea a a ae eee en es Os —— oTee ee PDM #|imu<br>0.02 Fem A A ]<br>0.01 0.01 eee dd 4<br>t1<br>a ee eee SINGLE PULSE Perri eeEee t2 j—<e— [1<br>1E−3 lapf||S==| teeJTSSSeetreTri (Note 1d) R ee JA = 135 ° C/W eeLLUAS555AeeeSS—tf==A NOTES: DUTY FACTOR: D = tPEAK TJ = PDM x Z 9 JA1 x R / t2 0 JA + TA lljanFaCyA<br>rT ET TTT TTT TT (I<br>1E−4 PT [TTT] [ET][EET] ]<br>i>) 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1] 100 1000<br>t, RECTANGULAR PULSE DURATION (s)<br>, NORMALIZED THERMAL IMPEDANCE<br>JA<br>Z<br>**----- End of picture text -----**<br>


**Figure 26. Junction−to−Ambient Transient Thermal Response Curve** 

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**FDPC8012S** 

## **TYPICAL CHARACTERISTICS** (continued) 

## **SyncFET Schottky Body Diode Characteristics** 

**onsemi** ’s SyncFET process embeds a Schottky diode in parallel with POWERTRENCH MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDPC8012S. 

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. 

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30 10−2<br>di/dt = 300 A/ s<br>25 T J  = 125 ° C<br>I  — EEE<br>10 [−3]<br>20<br>TJ = 100 ° C<br>15 ee<br>10 [−4]<br>10 es a ee ee ————a eeee<br>5<br>10 [−5]<br>0 ao == T J  = 25 ° C<br>we ==<br>−5 TMT 10 [−6] SSS<br>0 80 160 240 320 400 0 5 10 15 20 = 25<br>TIME (ns) VDS, REVERSE VOLTAGE (V)<br>Figure 27. FDPC8012S SyncFET Body Diode Figure 28. SyncFET Body Diode Reverse Leakage<br>Reverse Recovery Characteristic versus Drain−Source Voltage<br>CURRENT (A)<br>, REVERSE LEAKAGE CURRENT (A)<br>IDSS<br>**----- End of picture text -----**<br>


**Figure 27. FDPC8012S SyncFET Body Diode Reverse Recovery Characteristic** 

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**FDPC8012S** 

## **APPLICATION INFORMATION** 

## **Typical Application Diagram (Synchronous Rectifier Buck Converter)** 

Table 1 Pin Information shows the name and description of each pin. 

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V+(HSD)<br>VIN<br>Q1<br>Input<br>Capacitor<br>HSG I<br>SW Inductor<br>VO<br>Q2<br>Out<br>Capacitor<br>LSG I<br>GND(LSS)<br>**----- End of picture text -----**<br>


**Figure 29. Power Clip in Buck Converter Topology** 

**Table 1. PIN INFORMATION** 

|**Table 1. PIN INFORMATION**|**Table 1. PIN INFORMATION**||
|---|---|---|
|**PIN**||**Description**|
|**Number**|**Name**||
|1|HSG|Gate signal input of Q1 Gate|
|2, 3, 4|SW|Switch or Phase node,<br>Source of Q1 and Drain of Q2|
|5, 6,<br>PAD 10|GND, GND(LSS) PAD|Ground, Source of Q2|
|7|LSG|Gate signal input of Q2 Gate|
|8, PAD 9|V+, V+(HSD) PAD|Input voltage of SR Buck<br>converter, Drain of Q1|



As shown in Figure 29 in the Power Clip package Q1 is the High Side MOSFET (Control MOSFET) and Q2 is the Low Side MOSFET (Synchronous MOSFET). Figure 30 below shows the package pin out. The blue overlay on the drawing indicates a typical PCB land pattern for the part. 

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Top View<br>V+(HSD)<br>HSG 1 PAD 9 8 V+<br>SW 2 7 LSG<br>SW 3 PAD 10 6 GND<br>GND<br>SW 4 (LSS) 5 GND<br>**----- End of picture text -----**<br>


**Figure 30. Top View of Power Clip** 

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## **RECOMMENDED PCB LAYOUT GUIDELINES** 

As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Clip is a high power density solution and all high current flow paths, such as V+(HSD), SW and GND(LSS) should be short and wide for minimal 

resistance and inductance. V+(HSD) and GND(LSS) are the primary heat flow paths for the Power Clip. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. 

**Figure 31. Top/Component (Green) View and Bottom (Red) PCB View** 

_Following is a guideline, not a requirement which the PCB designer should consider._ 

Figure 31 shows an example of a well designed layout. The discussion that follows summarizes the key features of this layout. 

- ”The input ceramic bypass capacitor between VIN and GND should be placed as close as possible to the pins V+ / V+(HSD) PAD and GND / GND(LSS) PAD to help reduce parasitic inductance and high frequency ringing. Several capacitors may be placed in parallel, and capacitors may be placed on both the top and bottom side of the board. The capacitor located immediately adjacent to the Power Clip will be the most effective at reducing HF parasitic. Caps located farther away, or on the opposite side of the board will also assist, but will be less effective due to increased trace inductance. 

- ”The Power Clip package design, with very short distance between pins V+ and GND, allows for a short connect distance to the input cap. This is a factor that enables the Power Clip switch loop to have very low parasitic inductance. 

- ”Use large copper areas on the component side to connect the V+ pin and V+ (HSD) pad, and the GND and GND(LSS) PAD. 

- ”The SW to inductor copper trace is a high current path. It will also be a high noise region due to switching voltage 

   - transients. The trace should be short and wide to enable a low resistance path and to minimize the size of the noise region. Care should be taken to minimize coupling of this trace to adjacent traces. The layout in Figure 31 shows a good example of this short, wide path. 

- ”The POWERTRENCH Technology MOSFETs used in the Power Clip are effective at minimizing SW node ringing. They incorporate a proprietary design1 that minimizes the peak overshoot ring voltage on the switch node (SW). They allow the part to operate well within the breakdown voltage limits. For most layouts, this eliminates the need to add an external snubber circuit. If the designer chooses to use an RC snubber, it should be placed close to the part between the SW pins and GND / GND(LSS) PAD to dampen the high frequency ringing. 

- ”The Driver IC should be placed relatively closed to HSG pin and LSG pin to minimize G drive trace inductance. Excessive G trace length may slow the switching speed of the HS drive. And it may lead to excessive ringing on the LS G. If the designer must place the driver a significant distance away from the Power Clip, it would be a good practice to include a 0 Ohm resistor in the LS G path as a place holder. In the final design, if the LS G exhibits excessive LF ringing, efficiency can often be improved by changing this resistor to a few Ohms to dampen the LS G LF ringing. 

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## **FDPC8012S** 

- ”The Power Clip has very good Junction−PCB heat transfer from all power pins. It has much better heat transfer Junction−GND (LSS) than traditional dual FET packages. In most cases, board ground will be the most effective heat transfer path on the PCB. Use a large copper area between GND / GND(LSS) PAD pins and board ground. To ensure the best thermal and electrical connection to ground, we recommend using multiple vias to interconnect ground plane layers as shown in Figure 31. 

- ”Use multiple vias in parallel on each copper region to interconnect top, inner and bottom layers. This will reduce resistance and inductance of the vias and will improve thermal conductivity. Vias should be relatively large, around 8 mils to 10 mils. 

- ”Avoid using narrow thermal relief traces on the V+ / V+(HSD) PAD and GND / GND(LSS) PAD pins. These will increase HF switch loop inductance. And these will increase ringing of the HF power loop and the SW node. 

## **PACKAGE MARKING AND ORDERING INFORMATION** 

|**Device**|**Device Marking**|**Package**|**Reel Size**|**Tape Width**|**Shipping**†|
|---|---|---|---|---|---|
|FDPC8012S|01OD/03OD|PQFN8 3.3X3.3, 0.65P<br>Power Clip 33|13”|10 mm|3000 / Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

SyncFET is trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [93 x 29] intentionally omitted <==**

**----- Start of picture text -----**<br>
PQFN8 3.3X3.3, 0.65P<br>CASE 483AZ<br>ISSUE B<br>**----- End of picture text -----**<br>


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DATE 14 FEB 2022<br>**----- End of picture text -----**<br>


## **DOCUMENT NUMBER:** 

**98AON13675G** 

**DESCRIPTION: PQFN8 3.3X3.3, 0.65P** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

**PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2016 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **ADDITIONAL INFORMATION** 

**TECHNICAL PUBLICATIONS** : **ONLINE SUPPORT** : www.onsemi.com/support **Technical Library:** www.onsemi.com/design/resources/technical−documentation **For additional information, please contact your local Sales Representative at onsemi Website:** www.onsemi.com www.onsemi.com/support/sales 

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---

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