# Power MOSFET, N Channel, 60 V, 80 A, 4300 µohm, TO-220AB, Through Hole ![Product image](https://novapart.co/image/farnell:2454156/) **URL**: https://novapart.co/products/FDP050AN06A0/power-mosfet-n-channel-60-v-80-a-4300-ohm-to-220ab **SKU**: FDP050AN06A0 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.1100 **Stock**: 200+ **Lead Time**: 141 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:80A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0043ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; P ## Specifications | Parameter | Value | |---|---| | Msl | - | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 245W | | Transistor Mounting | Through Hole | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-220AB | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 80A | | Drain Source On State Resistance | 4300µohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2454156/) ## **ON Semiconductor** ## **Is Now** **==> picture [390 x 69] intentionally omitted <==** **To learn more about onsemi™, please visit our website at www.onsemi.com** **onsemi** and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as-is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. ## **FDP050AN06A0 / FDB050AN06A0 N-Channel PowerTrench[®] MOSFET 60 V, 80 A, 5 m** Ω ## **Features** - RDS(on) = 4.3 m Ω ( Typ.) @ VGS = 10 V, ID = 80 A ## **Applications** - QG(tot) = 61 nC ( Typ.) @ VGS = 10 V > • Synchronous Rectification for ATX / Server / Telecom PSU • Low Miller Charge • Battery Protection Circuit • Low Qrr Body Diode • Motor drives and Uninterruptible Power Supplies • UIS Capability (Single Pulse and Repetitive Pulse) Formerly developmental type 82575 **D D G G GDS S D[2] -PAK TO-220** ~~-. @~~ **S** ## **MOSFET Maximum Ratings** TC = 25°C unless otherwise noted |**Symbol**|**Parameter**|**FDP050AN06A0**
**FDB050AN06A0**|**FDP050AN06A0**
**FDB050AN06A0**|**Unit**| |---|---|---|---|---| |VDSS|Drain to Source Voltage||60|V| |VGS|Gate to Source Voltage||±20|V| ||Drain Current|||| |ID|Continuous(TC< 135oC, VGS= 10V)
Continuous(TA= 25oC, VGS= 10V, RθJA= 43oC/W)||80
18|A
A| ||Pulsed||Figure 4|A| |EAS|Single Pulse Avalanche Energy (Note 1)||470|mJ| |PD|Power dissipation
Derate above 25oC||245
1.63|W
oC
W/| |TJ, TSTG|Operatingand Storage Temperature||-55 to 175|oC| |**Thermal Characteristics**|**Thermal Characteristics**|||| |Thermal Resistance Junction to AmbientD2-PAK, Max. 1in2copper pad area
Thermal Resistance Junction to Ambient, Max. TO-220,D2-PAK (Note 2)
Thermal Resistance Junction to Case, Max. TO-220,D2-PAK
0.61
RθJC
oC/W
RθJA
oC/W
RθJA
oC/W
62
43
~~——~~||||| Publication Order Number: FDP050AN06A0/D ©2003 Semiconductor Components Industries, LLC. November-2017,Rev.3 ## **Package Marking and Ordering Information** |**Device Marking**|**Device Marking**|**Device**|**Package**|**Package**|**Reel Size**|**Reel Size**|**Tape Width**|**Tape Width**|**Quantity**|**Quantity**|**Quantity**| |---|---|---|---|---|---|---|---|---|---|---|---| |FDB050AN06A0||FDB050AN06A0|D2-PAK||330 mm||24 mm||800 units||| |FDP050AN06A0||FDP050AN06A0|TO-220||Tube||N/A||50 units||| |**Electrical Characteristics**TC= 25°C unless otherwise noted|||||||||||| |**Symbol**|**Parameter**|||**Test Conditions**|||**Min**|**Typ**||**Max**|**Unit**| |**Off Characteristics**|||||||||||| |BVDSS|Drain to Source Breakdown Voltage|||ID= 250µA, VGS||= 0V|60|-||-|V| |IDSS|Zero Gate Voltage Drain Current|||VDS= 50V
VGS= 0V|||-|-||1|µA| |||||||TC= 150oC|-|-||250|| |IGSS|Gate to Source Leakage Current|||VGS=±20V|||-|-||±100|nA| |**On Characteristics**|||||||||||| |VGS(TH)|Gate to Source Threshold Voltage|||VGS= VDS, ID=||250µA|2|-||4|V| |rDS(ON)|Drain to Source On Resistance|||ID= 80A, VGS= 10V|||-|0.0043||0.005|Ω| |||||ID= 40A, VGS= 6V|||-|0.007||0.011|| |||||ID= 80A, VGS= 10V,
TJ= 175oC|||-|0.0085||0.010|| |**Dynamic Characteristics**|||||||||||| |CISS|Input Capacitance|||VDS= 25V, VGS= 0V,
f = 1MHz|||-|3900||-|pF| |COSS|Output Capacitance||||||-|750||-|pF| |CRSS|Reverse Transfer Capacitance||||||-|270||-|pF| |Qg(TOT)|Total Gate Charge at 10V|||VGS= 0V to 10V||||61||80|nC| |Qg(TH)|Threshold Gate Charge|||VGS= 0V to 2V|||-|8||11|nC| |Qgs|Gate to Source Gate Charge||||||-|24||-|nC| |Qgs2|Gate Charge Threshold to Plateau||||||-|16||-|nC| |Qgd|Gate to Drain “Miller” Charge||||||-|15||-|nC| |**Switching Characteristics**(VGS= 10V)|||||||||||| |tON|Turn-On Time|||VDD= 30V, ID= 80A
VGS= 10V, RGS= 4.3Ω|||-|-||264|ns| |td(ON)|Turn-On Delay Time||||||-|16||-|ns| |tr|Rise Time||||||-|160||-|ns| |td(OFF)|Turn-Off Delay Time||||||-|28||-|ns| |tf|Fall Time||||||-|29||-|ns| |tOFF|Turn-Off Time||||||-|-||86|ns| |**Drain-Source Diode Characteristics**|||||||||||| |VSD|Source to Drain Diode Voltage|||ISD= 80A|||-|-||1.25|V| |||||ISD= 40A|||-|-||1.0|V| |trr|Reverse RecoveryTime|||ISD= 75A, dISD/dt = 100A/µs|||-|-||34|ns| |QRR|Reverse Recovered Charge|||ISD= 75A, dISD/dt = 100A/µs|||-|-||25|nC| |**Notes:**|||||||||||| **1:** Starting TJ = 25°C, L = 229 µ H, IAS = 64A. - **2:** Pulse width = 100s. **www.onsemi.com** **2** **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [429 x 572] intentionally omitted <==** **----- Start of picture text -----**
1.2 160
CURRENT LIMITED
B Y PACKAGE
1.0
120
0.8
0.6 80
0.4
40
0.2
0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t 1
t 2
NOTES:
DUTY FACTOR: D = t 1 /t 2
SINGLE PULSE PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
TC = 25 [o] C
FOR TEMPERATURES
1000 ABOVE 25 [o] C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V I = I25 175 - T150 C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100
50
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJC θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
**----- End of picture text -----**
**www.onsemi.com** **3** ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [429 x 588] intentionally omitted <==** **----- Start of picture text -----**
1000 500
If R = 0
10 µ s t AV = (L)(I AS )/(1.3*RATED BV DSS - V DD )
If R ≠ 0
100 µ s tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100 100
1ms
OPERATION IN THIS STARTING T J = 25 [o] C
10 AREA MAY BE 10ms
LIMITED BY rDS(ON)
10
DC
1
T SINGLE PULSEJ = MAX RATED STARTING T J = 150 [o] C
T C = 25 [o] C
0.1 1
1 10 100 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to ON Semiconductor Application Notes AN7514 and
AN7515
Figure 6. Unclamped Inductive Switching
Capability
160 160
PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX VGS = 7V
VDD = 15V VGS = 10V VGS = 6V
120 120
80 80
TJ = 175 [o] C
TJ = 25 [o] C VGS = 5V
40 40
T C = 25 [o] C
T J = -55 [o] C PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
0 0
0 0.5 1.0 1.5
4.0 4.5 5.0 5.5 6.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
8 2.0
PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX VGS = 6V DUTY CYCLE = 0.5% MAX
7
1.5
6
1.0
5
VGS = 10V
VGS = 10V, ID =80A
4
0.5
0 20 40 60 80
-80 -40 0 40 80 120 160 200
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature
, DRAIN CURRENT (A)
ID , AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)ID , DRAIN CURRENT (A)ID
)
Ω
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
DRAIN TO SOURCE ON RESISTANCE(m
**----- End of picture text -----**
**www.onsemi.com** **4** **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [429 x 387] intentionally omitted <==** **----- Start of picture text -----**
1.4 1.15
VGS = VDS, ID = 250 µ A ID = 250 µ A
1.2 1.10
1.0 1.05
0.8 1.00
0.6 0.95
0.4
0.90
-80 -40 0 40 80 120 160 200
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
10000 10
VDD = 30V
C ISS = C GS + C GD
8
COSS ≅ CDS + CGD
6
1000
CRSS = CGD
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 80A
VGS = 0V, f = 1MHz ID = 18A
100 0
0.1 1 10 60 0 10 20 30 40 50 60 70
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Current
NORMALIZED GATE THRESHOLD VOLTAGE BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature** **www.onsemi.com** **5** ## **Test Circuits and Waveforms** **==> picture [421 x 148] intentionally omitted <==** **----- Start of picture text -----**
VDS
BVDSS
L tP
VDS
VARY tREQUIRED PEAK IP TO OBTAINAS RG + VDD IAS VDD
VGS -
DUT
tP
0V IAS
0.01 Ω 0
tAV
**----- End of picture text -----**
**Figure 15. Unclamped Energy Test Circuit** **Figure 16. Unclamped Energy Waveforms** **==> picture [421 x 358] intentionally omitted <==** **----- Start of picture text -----**
VDS
VDD Qg(TOT)
L VDS
VGS VGS = 10V
VGS +
VDD Qgs2
-
DUT
Ig(REF) VGS = 2V
0
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
- VDD 0 10% 10%
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
**----- End of picture text -----**
**www.onsemi.com** **6** ## **Thermal Resistance vs. Mounting Pad Area** The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance RθJA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. **==> picture [62 x 22] intentionally omitted <==** **==> picture [26 x 9] intentionally omitted <==** In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. **==> picture [208 x 163] intentionally omitted <==** **----- Start of picture text -----**
80
R θ JA = 26.51+ 19.84/(0.262+Area) EQ.2
R θ JA = 26.51+ 128/(1.69+Area) EQ.3
60
40
20
0.1 1 10
(0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
C/W)
o(RJA θ
**----- End of picture text -----**
**Figure 21. Thermal Resistance vs Mounting Pad Area** 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. ON Semiconductor provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the ON Semiconductor device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. **==> picture [197 x 70] intentionally omitted <==** **www.onsemi.com** **7** ## _**PSPICE Electrical Model**_ **==> picture [430 x 355] intentionally omitted <==** **----- Start of picture text -----**
.SUBCKT FDB050AN06A0 2 1 3 ; rev February 2003
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9 LDRAIN
Cin 6 8 3.75e-9 DPLCAP 5 DRAIN
2
10
Dbody 7 5 DbodyMOD RLDRAIN
Dbreak 5 11 DbreakMOD 51RSLC1 DBREAK
Dplcap 10 5 DplcapMOD RSLC2
Ebreak 11 7 17 18 64.8 515 ESLC 11
Eds 14 8 5 8 1Egs 13 8 6 8 1Esg 6 10 6 8 1Evthres 6 21 19 8 1Evtemp 20 6 18 22 1 LGATE EVTEMPESG +- 68 EVTHRES+ 198 - 21RDRAIN50 16 EBREAKMWEAK+-1718 DBODY
GATE RGATE + 18 - 6
It 8 17 1 1 9 20 22 MMED
RLGATE MSTRO
Lgate 1 9 4.7e-9Ldrain 2 5 1.0e-9 CIN 8 7 LSOURCE SOURCE3
Lsource 3 7 4.03e-9
RSOURCE
RLSOURCE
RLgate 1 9 47 S1A S2A
RLdrain 2 5 10 12 13 14 15 17 RBREAK 18
RLsource 3 7 40 8 13
S1B S2B RVTEMP
Mmed 16 6 8 8 MmedMODMstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD CA EGS13+68 EDSCB+ 58 14 IT +-19VBAT
Rbreak 17 18 RbreakMOD 1 - - 8
Rdrain 50 16 RdrainMOD 1.1e-3 22
Rgate 9 20 1.3 RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2.1e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
+
-
**----- End of picture text -----**
Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10))} .MODEL DbodyMOD D (IS=1.3E-11 N=1.04 RS=1.76e-3 TRS1=2.7e-3 TRS2=2e-7 + CJO=2.7e-9 M=5.4e-1 TT=1e-10 XTI=3.9) .MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=1.3e-9 IS=1e-30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=3.7 KP=9 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.3) .MODEL MstroMOD NMOS (VTO=4.29 KP=155 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.05 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13 RS=0.1) .MODEL RbreakMOD RES (TC1=9.3e-4 TC2=-5.5e-7) .MODEL RdrainMOD RES (TC1=1.3e-2 TC2=4e-5) .MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.8e-3 TC2=-1.4e-5) .MODEL RvtempMOD RES (TC1=-2.8e-3 TC2=1e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. **www.onsemi.com 8** ## _**SABER Electrical Model**_ rev February 2003 template FDB050AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.3e-11,nl=1.04,rs=1.76e-3,trs1=2.7e-3,trs2=2e-7,cjo=2.7e-9,m=5.4e-1,tt=1e-10,xti=3.9) dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6) dp..model dplcapmod = (cjo=1.3e-9,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.7,kp=9,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.29,kp=155,is=1e-30, tox=1) **==> picture [437 x 390] intentionally omitted <==** **----- Start of picture text -----**
m..model mweakmod = (type=_n,vto=3.05,kp=0.03,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2) DPLCAP 5 LDRAIN DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4) 2
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=0.5) 10 RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1.5) RSLC1
c.ca n12 n8 = 1.5e-9 51
c.cb n15 n14 = 1.5e-9 RSLC2
c.cin n6 n8 = 3.75e-9 ISCL
dp.dbody n7 n5 = model=dbodymod - 50 DBREAK
dp.dbreak n5 n11 = model=dbreakmoddp.dplcap n10 n5 = model=dplcapmod ESG + 68 EVTHRES RDRAIN16 11 DBODY
spe.ebreak n11 n7 n17 n18 = 64.8spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 GATE1 RLGATELGATE 9RGATE20EVTEMP+ 1822 - 6 + 198 CIN- MSTRO21 8 MMED MWEAKEBREAK+-1718 7 LSOURCE SOURCE3
RSOURCE
i.it n8 n17 = 1 RLSOURCE
S1A S2A
l.lgate n1 n9 = 4.7e-9 12 138 1413 15 17 RBREAK 18
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 4.03e-9 S1B S2B RVTEMP
res.rlgate n1 n9 = 47 CA 13+ CB+ 14 IT -19
res.rldrain n2 n5 = 10res.rlsource n3 n7 = 40 EGS -68 EDS - 58 8 + VBAT
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u RVTHRES
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9.3e-4,tc2=-5.5e-7
res.rdrain n50 n16 = 1.1e-3, tc1=1.3e-2,tc2=4e-5
res.rgate n9 n20 = 1.3
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2.1e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.8e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-2.8e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
**----- End of picture text -----**
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 10)) } } **www.onsemi.com** **9** **==> picture [399 x 455] intentionally omitted <==** **----- Start of picture text -----**
SPICE Thermal Model
th JUNCTION
REV 23 February 2003
FDB050AN06A0T
CTHERM1 TH 6 5e-3
CTHERM2 6 5 1.3e-2
CTHERM3 5 4 1.4e-2 RTHERM1 CTHERM1
CTHERM4 4 3 1.9e-2
CTHERM5 3 2 4.7e-2
CTHERM6 2 TL 9e-2
6
RTHERM1 TH 6 1e-2
RTHERM2 6 5 3.1e-2
RTHERM3 5 4 4.5e-2
RTHERM2 CTHERM2
RTHERM4 4 3 1.2e-1
RTHERM5 3 2 1.3e-1
RTHERM6 2 TL 1.52e-1
5
SABER Thermal Model
SABER thermal model FDB050AN06A0T
template thermal_model th tl RTHERM3 CTHERM3
thermal_c th, tl
{
ctherm.ctherm1 th 6 =5e-3
ctherm.ctherm2 6 5 =1.3e-2 4
ctherm.ctherm3 5 4 =1.4e-2
ctherm.ctherm4 4 3 =1.9e-2
ctherm.ctherm5 3 2 =4.7e-2 RTHERM4 CTHERM4
ctherm.ctherm6 2 tl =9e-2
rtherm.rtherm1 th 6 =1e-2
rtherm.rtherm2 6 5 =3.1e-2 3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =1.2e-1
rtherm.rtherm5 3 2 =1.3e-1
RTHERM5 CTHERM5
rtherm.rtherm6 2 tl =1.52e-1
}
2
RTHERM6 CTHERM6
tl CASE
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**www.onsemi.com** **10** ## **Mechanical Dimensions** **==> picture [308 x 244] intentionally omitted <==** **----- Start of picture text -----**
TO-220 3L
__ 4833.56 > 18]
6.86
} t
'.r es——}-}—--—it6.865.84 f—---—4ae,|| / £413.40
Ty | 12,19
\ j
|
|
| '
fe _ |\} 3\!|2||i|1 |
5° 5° I} yi} ft
33
**----- End of picture text -----**
## **Figure 22. TO-220, Molded, 3Lead, Jedec Variation AB** Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a ON Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor's worldwide terms and conditions, specif-ically the warranty therein, which covers ON Semiconductor products. Dimension in Millimeters **www.onsemi.com** **11** ## **Mechanical Dimensions** **==> picture [159 x 22] intentionally omitted <==** **----- Start of picture text -----**
TO-263 2L (D [2] PAK)
**----- End of picture text -----**
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