# Power MOSFET, Trench, N Channel, 40 V, 30 A, 0.0056 ohm, Power 56, Surface Mount

![Product image](https://novapart.co/image/farnell:2617744/)

**URL**: https://novapart.co/products/FDMS9411L-F085/power-mosfet-trench-n-channel-40-v-30-a-00056-ohm
**SKU**: FDMS9411L-F085
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2570
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Qualification | AEC-Q101 |
| Power Dissipation | 50W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 50W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.0056ohm |
| Transistor Case Style | Power 56 |
| Drain Source Voltage Vds | 40V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 30A |
| Drain Source On State Resistance | 0.0056ohm |
| Automotive Qualification Standard | AEC-Q101 |
| Gate Source Threshold Voltage Max | 2V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2617744/)

## **Is Now Part of** 

**To learn more about ON Semiconductor, please visit our website at www.onsemi.com** 

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

**==> picture [46 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
May 2016<br>**----- End of picture text -----**<br>


## **FDMS9411L_F085** 

## **N-Channel Logic Level PowerTrench[® ] MOSFET** 

## **40 V, 30 A, 7.0 m** Ω 

## **Features** 

Typical RDS(on) = 5.6 mΩ at VGS = 10V, ID 

Typical Qg(tot) = 18 nC at VGS = 10V, ID = 30 A UIS Capability 

RoHS Compliant 

Qualified to AEC Q101 

**Applications** Automotive Engine Control a| 

PowerTrain Management 

7 Solenoid and Motor Drivers s r Electronic Steering[<] y For current package drawing, please refer to the Fairchild web‐ a Integrated Starter/Alternator site at https://www.fairchildsemi.com/package‐drawings/PQ/ a Distributed Power Architectures and VRM PQFN08M.pdf 

Primary Switch for 12V Systems 

**MOSFET Maximum Ratings** TJ = 25°C unless otherwise noted. 

|**Symbol**|**Parameter**|**Ratings**|**Units**|
|---|---|---|---|
|VDSS|Drain-to-Source Voltage|40|V|
|VGS|Gate-to-Source Voltage|±20|V|
|ID|Drain Current - Continuous(VGS=10) (Note 1)TC = 25°C|30|A|
||Pulsed Drain Current                                                      TC = 25°C|See Figure 4||
|EAS|Single Pulse Avalanche Energy (Note 2)|15.7|mJ|
|PD|Power Dissipation|50|W|
||Derate Above 25oC|0.33|W/oC|
|TJ, TSTG|Operatingand Storage Temperature|-55 to + 175|oC|
|RθJC|Thermal Resistance, Junction to Case|3|oC/W|
|RθJA|Maximum Thermal Resistance, Junction to Ambient(Note 3)|50|oC/W|



## **Notes:** 

- 1:  Current is limited by bondwire configuration. 

- 2:  Starting TJ = 25°C, L = 40μH, IAS = 28A, VDD = 40V during inductor charging and VDD = 0V during time in avalanche. 

- 3:  RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain pins.  RθJC is guaranteed by design, while RθJA is determined by the board design.  The maximum rating presented here is based on mounting on a 1 in[2 ] pad of 2oz copper. 

## **Package Marking and Ordering Information** 

|**Device Marking**|**Device**|**Package**|**Reel Size**|**Tape Width**|**Quantity**|
|---|---|---|---|---|---|
|FDMS9411L|FDMS9411L_F085|Power56|13”|12mm|3000units|



©2016 Fairchild Semiconductor Corporation FDMS9411L_F085 Rev. 1.0 

www.fairchildsemi.com 

**1** 

**Electrical Characteristics** TJ = 25°C unless otherwise noted. 

|**Symbol**|**Parameter**|**Test Conditions**|**Test Conditions**|**Min.**|**Typ.**|**Max.**|**Units**|
|---|---|---|---|---|---|---|---|
|**Off Characteristics**||||||||
|BVDSS|Drain-to-Source Breakdown Voltage|ID= 250μA, VGS= 0V||<br>40|-|-|V|
|IDSS|Drain-to-Source Leakage Current|VDS= 40V,<br>VGS= 0V|TJ= 25oC|-|-|1|μA|
||||TJ= 175oC (Note 4)|-|-|1|mA|
|IGSS|Gate-to-Source Leakage Current|VGS= ±20V||-|-|±100|nA|
|**On Characteristics**||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250μA||1.0|2.0|3.0|V|
|RDS(on)|Drain to Source On Resistance|ID= 30A, VGS= 4.5V||-|9.0|12.5|mΩ|
|||ID= 30A,<br>VGS= 10V|TJ= 25oC|-|5.6|7.0|mΩ|
||||TJ= 175oC(Note 4)|-|10.0|12.5|mΩ|



## **Dynamic Characteristics** 

|Ciss|Input Capacitance|VDS= 20V, VGS= 0V,<br>f = 1MHz|-|1210|-|pF|
|---|---|---|---|---|---|---|
|Coss|Output Capacitance||-|413|-|pF|
|Crss|Reverse Transfer Capacitance||-|28|-|pF|
|Rg|Gate Resistance|f = 1MHz|-|2.6|-|Ω|
|Qg(ToT)|Total Gate Charge|VGS= 0 to 10V|-|18|28|nC|
|Qg(th)|Threshold Gate Charge|VGS= 0 to 2V|-|2|-|nC|
|Qgs|Gate-to-Source Gate Charge||-|4|-|nC|
|Qgd|Gate-to-Drain “Miller“ Charge||-|3|-|nC|
|**Switching Characteristics**|||||||
|ton|Turn-On Time|VDD= 20V, ID= 30A,<br>VGS= 10V, RGEN= 6Ω|-|-|15|ns|
|td(on)|Turn-On Delay||-|8|-|ns|
|tr|Rise Time||-|3|-|ns|
|td(off)|Turn-Off Delay||-|20|-|ns|
|tf|Fall Time||-|4|-|ns|
|toff|Turn-Off Time||-|-|36|ns|



## **Drain-Source Diode Characteristics** 

|VSD|Source-to-Drain Diode Voltage|ISD=30A, VGS= 0V|-|-|1.25|V|
|---|---|---|---|---|---|---|
|||ISD= 15A, VGS= 0V|-|-|1.2|V|
|trr|Reverse-RecoveryTime|IF= 30A, dISD/dt = 100A/μs<br>VDD= 32V|-|38|57|ns|
|Qrr|Reverse-RecoveryCharge||-|22|33|nC|



## **Note:** 

- 4:  The maximum value is specified by design at TJ = 175°C.  Product is not tested to this condition in production. 

©2016 Fairchild Semiconductor Corporation FDMS9411L_F085 Rev. 1.0 

www.fairchildsemi.com 

**2** 

## **Typical Characteristics** 

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**----- Start of picture text -----**<br>
1.2 80<br>VGS = 10V<br>1.0 CURRENT LIMITED<br>60 BY SILICON<br>0.8 CURRENT LIMITED<br>BY PACKAGE<br>0.6 40<br>0.4<br>20<br>0.2<br>0.0 0<br>0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 200<br>TC, CASE TEMPERATURE( [o] C) TC, CASE TEMPERATURE( [o] C)<br>Figure 1.  Normalized Power Dissipation vs. Case  Figure 2.  Maximum Continuous Drain Current vs.<br>Temperature              Case Temperature<br>2<br>DUTY CYCLE - DESCENDING ORDER<br>1<br>D = 0.50<br>      0.20<br>      0.10 P DM<br>      0.05<br>      0.02<br>0.1       0.01 t1<br>t2<br>NOTES:<br>SINGLE PULSE DUTY FACTOR: D = t1/t2<br>PEAK T J = P DM  x Z θ JC  x R θ JC  + T C<br>0.01<br>10-5 10-4 10-3 10-2 10-1 100 101<br>t, RECTANGULAR  PULSE DURATION(s)<br>Figure 3.  Normalized Maximum Transient Thermal Impedance<br>1000<br>VGS = 10V FOR TEMPERATURESTC = 25 [o] C<br>ABOVE 25 [o] C DERATE PEAK<br>CURRENT AS FOLLOWS:<br>I = I25  175 - TC<br>150<br>100<br>SINGLE PULSE<br>10<br>10-5 10-4 10-3 10-2 10-1 100 101<br>t, RECTANGULAR PULSE DURATION(s)<br>Figure 4.  Peak Current Capability<br>, DRAIN CURRENT (A)<br>ID<br>POWER DISSIPATION MULTIPLIER<br>IMPEDANCE, ZJC θ<br>NORMALIZED THERMAL<br>PEAK CURRENT (A)<br>,<br>IDM<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

©2016 Fairchild Semiconductor Corporation FDMS9411L_F085 Rev. 1.0 

**3** 

**==> picture [432 x 608] intentionally omitted <==**

**----- Start of picture text -----**<br>
Typical Characteristics<br>100<br>1000 If R = 0<br>tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)<br>If R  ≠  0<br>tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]<br>100<br>10 100us 10 STARTING TJ = 25 [o] C<br>OPERATION IN THIS<br>AREA MAY BE<br>LIMITED BY PACKAGE STARTING T J  = 150 [o] C<br>1<br>OPERATION IN THIS  SINGLE PULSE 1ms<br>AREA MAY BE LIMITED BY rDS(on) TJ = MAX RATED 10ms<br>T C  = 25 [o] C 100ms 1<br>0.1 0.001 0.01 0.1 1 10 100<br>0.1 1 10 100 200 tAV, TIME IN AVALANCHE (ms)<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>NOTE: Refer to Fairchild Application Notes AN7514 and AN7515<br>Figure 5.  Forward Bias Safe Operating Area Figure 6.  Unclamped Inductive Switching<br>Capability<br>100 100<br>PULSE DURATION = 250 μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>80 VDD = 5V<br>10<br>60<br>TJ = 175  [o] C TJ = 25 [ o] C<br>TJ = 25 [o] C<br>40 TJ = -55 [o] C<br>1<br>TJ = 175 [o] C<br>20<br>0 0.1<br>1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 7.  Transfer Characteristics Figure 8.  Forward Diode Characteristics<br>100 100<br>250 μ s PULSE WIDTH 10V  TopVGS VGS<br>80 Tj=25 [o] C 6V5V 80 10V  Top 6V<br>4.5V 5V<br>4V 4.5V<br>60 3.5V 3V     Bottom 60 4V3.5V<br>3V     Bottom<br>40 40<br>3V<br>20 20<br>250 μ s PULSE WIDTH<br>3V<br>Tj=175 [o] C<br>0 0<br>0 1 2 3 4 5 0 1 2 3 4 5<br>VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 9.  Saturation Characteristics  Figure 10.  Saturation Characteristics<br>, DRAIN CURRENT (A)<br>D<br> I<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID , REVERSE DRAIN CURRENT (A)IS<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>**----- End of picture text -----**<br>


©2016 Fairchild Semiconductor Corporation FDMS9411L_F085 Rev. 1.0 

www.fairchildsemi.com 

**4** 

**==> picture [433 x 623] intentionally omitted <==**

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Typical Characteristics<br>50 2.0<br>PULSE DURATION = 250 μ s PULSE DURATION = 250 μ s<br>DUTY CYCLE = 0.5% MAX 1.8 DUTY CYCLE = 0.5% MAX<br>40 ID = 30A<br>1.6<br>1.4<br>30<br>1.2<br>20<br>1.0<br>TJ = 175 [o] C 0.8<br>10  ID = 30A<br>0.6 VGS = 10V<br>TJ = 25 [o] C<br>0 0.4<br>3 4 5 6 7 8 9 10 -80 -40 0 40 80 120 160 200<br>VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE( [o] C)<br>Figure 11.  RDSON vs. Gate Voltage Figure 12.  Normalized RDSON vs. Junction<br>Temperature<br>1.2 1.10<br>VGS = VDS ID = 5mA<br>1.1 ID = 250 μ A<br>1.0 1.05<br>0.9<br>0.8 1.00<br>0.7<br>0.6 0.95<br>0.5<br>0.4 0.90<br>-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)<br>Figure 13.  Normalized Gate Threshold Voltage vs.  Figure 14.  Normalized Drain to Source<br>Temperature Breakdown Voltage vs. Junction Temperature<br>10000 10<br>ID = 30A<br>8<br>VDD = 20V<br>1000 Ciss VDD = 24V<br>6<br>C oss 4 VDD =16V<br>100<br>2<br>f = 1MHz<br>V GS  = 0V Crss<br>10 0<br>0.1 1 10 100 0 3 6 9 12 15 18<br>VDS, DRAIN TO SOURCE VOLTAGE (V) Qg ,  GATE CHARGE(nC)<br>Figure 15.  Capacitance vs. Drain to Source  Figure 16.  Gate Charge  vs. Gate to Source<br>Voltage Voltage<br>) Ω<br>m<br>, DRAIN TO SOURCE  NORMALIZED<br>ON-RESISTANCE (<br>rDS(on)<br> DRAIN TO SOURCE ON-RESISTANCE<br>NORMALIZED GATE<br>THRESHOLD VOLTAGE  BREAKDOWN VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE(V)<br>GS<br>V<br>**----- End of picture text -----**<br>


©2016 Fairchild Semiconductor Corporation FDMS9411L_F085 Rev. 1.0 

www.fairchildsemi.com 

**5** 

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## **PRODUCT STATUS DEFINITIONS** 

## **Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications<br>may change in any manner without notice.|
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|Obsolete|Not In Production|Datasheet contains specifications on a product that is discontinued by Fairchild<br>Semiconductor. The datasheet is for reference information only.|



Rev. I77 

**6** 

©2016 Fairchild Semiconductor Corporation FDMS9411L_F085 Rev. 1.0 

www.fairchildsemi.com 

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