# Power MOSFET, N Channel, 60 V, 129 A, 2700 µohm, Power 56, Surface Mount ![Product image](https://novapart.co/image/farnell:2829470/) **URL**: https://novapart.co/products/FDMS86540/power-mosfet-n-channel-60-v-129-a-2700-ohm-56 **SKU**: FDMS86540 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.6640 **Stock**: 1000+ **Lead Time**: 134 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:129A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0027ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3.2V; ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | PowerTrench | | Qualification | - | | Power Dissipation | 96W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | Power 56 | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 129A | | Drain Source On State Resistance | 2700µohm | | Gate Source Threshold Voltage Max | 3.2V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2829470/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [41 x 10] intentionally omitted <==** **----- Start of picture text -----**
May 2015
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## **FDMS86540** ## **N-Channel PowerTrench[®] MOSFET 60 V, 129 A, 3.4 m** Ω ## **Features** Max rDS(on) = 3.4 mΩ at VGS = 10 V, ID = 20 A Max rDS(on) = 4.1 mΩ at VGS = 8 V, ID = 18.5 A Advanced Package and Silicon combination for low rDS(on) and high efficiency Next generation enhanced body diode technology, engineered for soft recovery MSL1 robust package design ## **General Description** This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers.It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. ## **Applications** Primary Switch in isolated DC-DC > 100% UIL tested - - yiaa Synchronous Rectifier RoHS Compliant -a Load Switch ||**Top**|||**Bottom**|**S**
**Bottom**|**S**
<—|**S**
<—|Pin 1|Pin 1|**S**|i|i|||‘8|**D**|| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||||||||**S**|**G**||**S**|2}||||i|**D**|| |||||||||||**S**|3}||||i|**D**|| ||**Power 56**
**D **|**D D**||**D**||||||**G**|4}||||i|**D**|| |**MOSFET Maximum Ratings**|**MOSFET Maximum Ratings **TA= 25 °C unless otherwise noted.|= 25 °C unless otherwise noted.|||||||||||||||| |**Symbol**|||**Parameter**||||||||||**Ratings**||||**Units**| |VDS|Drain to Source Voltage||||||||||||60||||V| |VGS|Gate to Source Voltage||||||||||||±20||||V| ||Drain Current -Continuous||||T|TC|= 25 °C|= 25 °C||(Note 5)|||129||||| |ID|-Continuous
-Continuous||||T|TC
TA|= 100 °C
A= 25 °C|= 100 °C
= 25 °C||(Note 5)
(Note 1a)|||82
20||||A| ||-Pulsed|||||||||(Note 4)|||642||||| |EAS|Single Pulse Avalanche Energy|||||||||(Note 3)|||228||||mJ| |PD|Power Dissipation
Power Dissipation|||T|T|TC= 25 °C
TA= 25 °C|= 25 °C
= 25 °C|= 25 °C
= 25 °C||= 25 °C
(Note 1a)|||96
2.5||||W| |TJ, TSTG
Operatingand Storage Junction Tem||e Junction Temperature Range|||||||||||-55 to +150||||°C| |**Thermal Characteristics**|**Thermal Characteristics**||||||||||||||||| |RθJC|Thermal Resistance, Junction-to-Case||||||||||||1.3||||°C/W| |RθJA|Thermal Resistance, Junction-to-Ambient|||||||||(Note 1a)|||50||||| |**Package Marking and Ordering Information**|**Package Marking and Ordering Information**||||||||||||||||| |**Device Marking**
**Device**||||**Package**|||||**Reel Size**||||**Tape Width**|||**Quantity**|| ||FDMS86540
FDMS86540|||Power 56|Power 56|||||13 ’’|||12 mm|||3000 units|| **MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted. ## **Thermal Characteristics** ## **Package Marking and Ordering Information** www.fairchildsemi.com **1** ©2012 Fairchild Semiconductor Corporation FDMS86540 Rev. 1.4 ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. |**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
28
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
2
3.2
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-11
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 20 A
2.7
3.4
mΩ
VGS= 8 V, ID= 18.5 A
3.1
4.1
VGS= 10 V, ID= 20 A, TJ = 125 °C
3.8
4.8
gFS
Forward Transconductance
VDS= 10 V, ID= 20 A
73
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
4837
6435
pF
Coss
Output Capacitance
1413
1880
pF
Crss
Reverse Transfer Capacitance
50
90
pF
Rg
Gate Resistance
1.0
Ω
~~a~~
~~eee~~
~~—————~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
28
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
2
3.2
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-11
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 20 A
2.7
3.4
mΩ
VGS= 8 V, ID= 18.5 A
3.1
4.1
VGS= 10 V, ID= 20 A, TJ = 125 °C
3.8
4.8
gFS
Forward Transconductance
VDS= 10 V, ID= 20 A
73
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
4837
6435
pF
Coss
Output Capacitance
1413
1880
pF
Crss
Reverse Transfer Capacitance
50
90
pF
Rg
Gate Resistance
1.0
Ω
~~a~~
~~eee~~
~~—————~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
28
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
2
3.2
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-11
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 20 A
2.7
3.4
mΩ
VGS= 8 V, ID= 18.5 A
3.1
4.1
VGS= 10 V, ID= 20 A, TJ = 125 °C
3.8
4.8
gFS
Forward Transconductance
VDS= 10 V, ID= 20 A
73
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
4837
6435
pF
Coss
Output Capacitance
1413
1880
pF
Crss
Reverse Transfer Capacitance
50
90
pF
Rg
Gate Resistance
1.0
Ω
~~a~~
~~eee~~
~~—————~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
28
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
2
3.2
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-11
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 20 A
2.7
3.4
mΩ
VGS= 8 V, ID= 18.5 A
3.1
4.1
VGS= 10 V, ID= 20 A, TJ = 125 °C
3.8
4.8
gFS
Forward Transconductance
VDS= 10 V, ID= 20 A
73
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
4837
6435
pF
Coss
Output Capacitance
1413
1880
pF
Crss
Reverse Transfer Capacitance
50
90
pF
Rg
Gate Resistance
1.0
Ω
~~a~~
~~eee~~
~~—————~~| |---|---|---|---| |**Switching Characteristics**|||| |td(on)
Turn-On DelayTime|||28
45
ns| |tr
Rise Time|VDD= 30 V, ID= 20 A,||16
29
ns| |td(off)
Turn-Off DelayTime|VGS= 10 V, RGEN= 6Ω||32
52
ns| |tf
Fall Time|||7.2
15
ns| |Qg
Total Gate Charge
VGS= 0 V to 10 V
VDD= 30 V,
ID= 20 A
65
90
nC
Qg
Total Gate Charge
VGS= 0 V to 8 V
53
75
nC
Qgs
Gate to Source Charge
23
nC
Qgd
Gate to Drain “Miller” Charge
12
nC
~~——————~~|||| |**Drain-Source Diode Characteristics**|||| |VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 2.1 A(Note 2)
0.70
1.2
V
VGS = 0 V, IS = 20 A(Note 2)
0.79
1.3
trr
Reverse RecoveryTime
IF= 20 A, di/dt = 100 A/μs
55
88
ns
Qrr
Reverse RecoveryCharge
41
66
nC
trr
Reverse RecoveryTime
IF= 20 A, di/dt = 300 A/μs
44
70
ns
Qrr
Reverse RecoveryCharge
76
122
nC
Notes**:**
1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCAis determined by the user's board design.
~~=—————~~
~~nae~~|||| |50 °C/W when mounted on a
1 in2pad of 2 oz copper
a)|50 °C/W when mounted on a
pad of 2 oz copper
Q||125 °C/W when mounted on a
minimum pad of 2 oz copper.
b)| |**G**
**DF**
**DS**
**SF**
**SS**|**G**
**DF**
**DS**
**SF**
**SS**||| 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Starting TJ = 25 °C, L = 0.3 mH, IAS = 39 A, VDD = 54 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 57 A. 4. Pulse Id please refer to SOA curve for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2012 Fairchild Semiconductor Corporation FDMS86540 Rev. 1.4 **2** www.fairchildsemi.com **Typical Characteristics** TJ = 25 °C unless otherwise noted. **==> picture [462 x 351] intentionally omitted <==** **----- Start of picture text -----**
350 5
VGS = 10 V
VGS = 9 V VGS = 6 V
280 4
VGS = 8 V
VGS = 7 V VGS = 7 V
210 3
VGS = 8 V
140 2
VGS = 6 V
70 1
PULSE DURATION = 80 μ s PULSE DURATION = 80 μ s VGS = 9 V VGS = 10 V
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
0 0
0 1 2 3 4 5 0 70 140 210 280 350
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
1.7 15
1.6 I D = 20 A ID = 20 AD = 20 A= 20 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAXDUTY CYCLE = 0.5% MAX μ s
1.5 V GS = 10 V 12
1.4
1.3 9
1.2
1.1 6
TJ = 125 J = 125 = 125 [[o]] C
1.0
0.9 3
0.8 TJ = 25 J = 25 = 25 [[o]] C
0.7 0
-75 -50 -25 0 25 50 75 100 125 150 4 5 6 7 8 9 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGSGS, GATE TO SOURCE VOLTAGE (V) GATE TO SOURCE VOLTAGE (V)
NORMALIZED
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON-RESISTANCE
)
Ω
m
(
DRAIN TO
NORMALIZED rDS(on),DS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
**----- End of picture text -----**
**==> picture [208 x 149] intentionally omitted <==** **----- Start of picture text -----**
15
ID = 20 AD = 20 A= 20 A μ s
PULSE DURATION = 80 DUTY CYCLE = 0.5% MAXDUTY CYCLE = 0.5% MAX
12
9
6
TJ = 125 J = 125 = 125 [[o]] C
3
TJ = 25 J = 25 = 25 [[o]] C
0
4 5 6 7 8 9 10
VGSGS, GATE TO SOURCE VOLTAGE (V)
)
Ω
m
(
DRAIN TO
rDS(on),DS(on),
SOURCE ON-RESISTANCE
**----- End of picture text -----**
**vs. Junction Temperature** **Figure 4. Source Voltage** **==> picture [466 x 187] intentionally omitted <==** **----- Start of picture text -----**
350 400
PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s 100 V GS = 0 V
280
VDS = 5 V 10
210 TJ = 150 [o] C
1
TJ = 25 [ o] C
140
TJ = 150 [o] C 0.1
TJ = 25 [o] C TJ = -55 [o] C
70 0.01
TJ = -55 [o] C
0 0.001
2 3 4 5 6 7 8 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
©2012 Fairchild Semiconductor Corporation FDMS86540 Rev. 1.4 **3** www.fairchildsemi.com **Typical Characteristics** TJ = 25 °C unless otherwise noted. **==> picture [469 x 575] intentionally omitted <==** **----- Start of picture text -----**
10 10000
Ciss
ID = 20 A VDD = 30 V
8
VDD = 20 V VDD = 40 V 1000 Coss
6
4
100
2 f = 1 MHz Crss
VGS = 0 V
0 10
0 10 20 30 40 50 60 70 0.1 1 10 60
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain
to Source Voltage
100 140
R θ JC = 1.3 [o] C/W
120
VGS = 10 V
100
VGS = 8 V
TJ = 25 [ o] C 80
10
60
TJ = 100 [ o] C
40
TJ = 125 [o] C 20
1 0
0.01 0.1 1 10 100 300 25 50 75 100 125 150
tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)
Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain
Switching Capability Current vs. Case Temperature
1000 20000
10000 SINGLE PULSE
10 μ s R θ JC = 1.3 [o] C/W
100
TC = 25 [o] C
10 100 μ s 1000
THIS AREA IS 1 ms
1 LIMITED BY r DS(on)
10 ms
SINGLE PULSE 100
DC
0.1 TR J θ JC= MAX RATED= 1.3 [o] C/W CURVE BENT TO
TC = 25 [o] C MEASURED DATA
0.010.1 1 10 100 200 1010-5 10-4 10-3 10-2 10-1 1
VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum
Operating Area Power Dissipation
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
,
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)
ID
PEAK TRANSIENT POWER (W)
,
(PK)
P
**----- End of picture text -----**
©2012 Fairchild Semiconductor Corporation FDMS86540 Rev. 1.4 **4** www.fairchildsemi.com **==> picture [457 x 196] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TJ = 25 °C unless otherwise noted.
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1 0.1 PDM
0.05
0.02
0.01 t1
t 2
0.01 NOTES:
SINGLE PULSE Z θ JC(t) = r(t) x R θ JC
R θ JC = 1.3 [o] C/W
Peak TJ = PDM x Z θ JC(t) + TC
Duty Cycle, D = t1 / t2
0.001
10-5 10-4 10-3 10-2 10-1 1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE TRANSIENT
**----- End of picture text -----**
©2012 Fairchild Semiconductor Corporation FDMS86540 Rev. 1.4 **5** www.fairchildsemi.com **==> picture [490 x 598] intentionally omitted <==** **----- Start of picture text -----**
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10 A 5.10
3.91
PKG SEE
1.27
CL B DETAIL B
8 5 8 7 6 5
0.77
4.52
3.75
PKG CL 6.15 5.85 6.61
5.65
KEEP OUT
AREA
1.27
1 4
1 2 3 4
TOP VIEW
1.27 0.61
3.81
LAND PATTERN
OPTIONAL DRAFT RECOMMENDATION
ANGLE MAY APPEAR
SEE ON FOUR SIDES
5.00
4.80 DETAIL C OF THE PACKAGE
0.35
0.15
������
0.10 C
0.30
0.05
0.05
SIDE VIEW 0.00 ������
8X
0.08 C
0.35 C
5.20 0.15
4.80 1.10 SEATING
0.90 PLANE
DETAIL C DETAIL B
3.81
SCALE: 2:1 SCALE: 2:1
1.27 0.51
0.31 [ (8X)]
(0.34) NOTES: UNLESS OTHERWISE SPECIFIED
0.10 C A B A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
1 2 3 4 ISSUE A, VAR. AA,.
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
0.76 MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
0.51 (0.52) C. ALL DIMENSIONS ARE IN MILLIMETERS.
6.25 D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
5.90 E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
(0.50) 3.48 [+0.30]
-0.10
(0.30)
(2X)
8 7 6 5
���������
0.20 [+0.10] 3.96
-0.15 [(8X)]
3.61
**----- End of picture text -----**
**==> picture [63 x 8] intentionally omitted <==** **----- Start of picture text -----**
BOTTOM VIEW
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