# Power MOSFET, N Channel, 60 V, 80 A, 2500 µohm, Power 56, Surface Mount ![Product image](https://novapart.co/image/farnell:2083321RL/) **URL**: https://novapart.co/products/FDMS86500L/power-mosfet-n-channel-60-v-80-a-2500-ohm-56 **SKU**: FDMS86500L **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.1600 **Stock**: 1000+ **Lead Time**: 701 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:80A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0021ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.8V; Po ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 104W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | Power 56 | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 80A | | Drain Source On State Resistance | 2500µohm | | Gate Source Threshold Voltage Max | 1.8V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2083321RL/) ## **Is Now Part of** **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **www.onsemi.com** ## **FDMS86500L** **N-Channel PowerTrench[®] MOSFET 60 V, 158 A, 2.5 m** Ω ## **Features** i[|] Max rDS(on) = 2.5 mΩ at VGS = 10 V, ID = 25 A Max rDS(on) = 3.7 mΩ at VGS = 4.5 V, ID = 20 A Advanced Package and Silicon combination for low rDS(on) and high efficiency Next generation enhanced body diode technology, engineered for soft recovery MSL1 robust package design 100% UIL tested RoHS Compliant ## **General Description** This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. ## **Applications** Primary Switch in Isolated DC-DC Synchronous Rectifier Load Switch |**Top**
Pin 1||**Bottom**|**S**
**Bottom**|<—|Pin 1|Pin 1|**S**|1}||18||**D**||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |||||**S**||||||||||| |||||**S**|**G**||**S**|2}||‘7||**D**||| ||||||||**S**|3}||‘6||**D**||| |**D D D**||**D**|||||**G**|4}||is||**D**||| |**Power 56**||||||||||||||| |**MOSFET Maximum Ratings **TA= 25 °C unless otherwise noted.||||||||||||||| |**Symbol**|**Parameter**|||||||||**Ratings**||||**Units**| |VDS
Drain to Source Voltage||||||||||60||||V| |VGS
Gate to Source Voltage|e|e|e|e|e|e|e|||±20||||V| |Drain Current -Continuous T|Drain Current -Continuous T|Drain Current -Continuous T|Drain Current -Continuous T|Drain Current -Continuous TC = 25 °C|= 25 °C||= 25 °C(Note 5)|||158||||| |ID
-Continuous T
-Continuous T|-Continuous T
-Continuous T|-Continuous T
-Continuous T|-Continuous T
-Continuous T|-Continuous TC = 100 °C
-Continuous TA= 25 °C|= 100 °C
= 25 °C||= 100 °C(Note 5)
= 25 °C(Note 1a)|||100
25||||A| |-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed(Note 4)|||799||||| |EAS
Single Pulse Avalanche Energy|||||||(Note 3)|||240||||mJ| |PD
Power Dissipation T
Power Dissipation T|ation T
ation T|ation T
ation T|ation T
ation T|ation TC= 25 °C
ation TA= 25 °C|= 25 °C
= 25 °C||= 25 °C(Note 1a)|||104
2.5||||W| |TJ, TSTG
Operatingand Storage Junction Temperature Range||||||||||-55 to +150||||°C| |**Thermal Characteristics**||||||||||||||| |RθJC
Thermal Resistance, Junction-to-Case||||||||||1.2||||°C/W| |RθJA
Thermal Resistance, Junction-to-Ambient|||Thermal Resistance, Junction-to-Ambient|Thermal Resistance, Junction-to-Ambient|Thermal Resistance, Junction-to-Ambient|Thermal Resistance, Junction-to-Ambient|Thermal Resistance, Junction-to-Ambient(Note 1a)|||50||||| |**Package Marking and Ordering Information**||||||||||||||| |**Device Marking**
**Device**||**Package**||||**Reel Size**||||**Tape Width**||**Quantity**||| |FDMS86500L
FDMS86500L||Power 56|Power 56||||13 ’’|||12 mm||3000 units||3000 units| Semiconductor Components Industries, LLC, 2016 November, 2016, Rev. 1.5 Publication Order Number: FDMS86500L **1** ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. |**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
30
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
1
1.8
3
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-7
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 25 A
2.1
2.5
mΩ
VGS= 4.5 V, ID= 20 A
2.9
3.7
VGS= 10 V, ID= 25 A, TJ = 125 °C
3.1
3.7
gFS
Forward Transconductance
VDS= 5 V, ID= 20 A
95
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
9420
12530
pF
Coss
Output Capacitance
1470
1955
pF
Crss
Reverse Transfer Capacitance
50
80
pF
Rg
Gate Resistance
0.1
1.1
3.0
Ω
~~re~~
~~—————~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
30
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
1
1.8
3
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-7
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 25 A
2.1
2.5
mΩ
VGS= 4.5 V, ID= 20 A
2.9
3.7
VGS= 10 V, ID= 25 A, TJ = 125 °C
3.1
3.7
gFS
Forward Transconductance
VDS= 5 V, ID= 20 A
95
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
9420
12530
pF
Coss
Output Capacitance
1470
1955
pF
Crss
Reverse Transfer Capacitance
50
80
pF
Rg
Gate Resistance
0.1
1.1
3.0
Ω
~~re~~
~~—————~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
60
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
30
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 48 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
1
1.8
3
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-7
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 25 A
2.1
2.5
mΩ
VGS= 4.5 V, ID= 20 A
2.9
3.7
VGS= 10 V, ID= 25 A, TJ = 125 °C
3.1
3.7
gFS
Forward Transconductance
VDS= 5 V, ID= 20 A
95
S
Ciss
Input Capacitance
VDS= 30 V, VGS= 0 V,
f = 1 MHz
9420
12530
pF
Coss
Output Capacitance
1470
1955
pF
Crss
Reverse Transfer Capacitance
50
80
pF
Rg
Gate Resistance
0.1
1.1
3.0
Ω
~~re~~
~~—————~~| |---|---|---| |td(on)
Turn-On DelayTime|27
43
ns|| |VDD= 30 V, ID= 25 A,
tr
Rise Time|16
28
ns|| |VGS= 10 V, RGEN= 6Ω
td(off)
Turn-Off DelayTime|63
100
ns|| |tf
Fall Time|7.8
16
ns|| |Qg
Total Gate Charge
VGS= 0 V to 10 V
VDD= 30 V,
ID= 25 A
117
165
nC
Qg
Total Gate Charge
VGS= 0 V to 4.5 V
54
108
nC
Qgs
Gate to Source Charge
26.6
nC
Qgd
Gate to Drain “Miller” Charge
11.5
nC
~~—————~~||| |**Drain-Source Diode Characteristics**||| |Is
Continuous Drain to Source Diode
Forward Current
TC= 25 °C|80
A|| |Is, pluse
Pluse Drain to Source Diode
Forward Current
TC= 25 °C|799
A|| |VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 2.1 A(Note 2)
VGS = 0 V, IS = 25 A(Note 2)|0.68
1.2
V
0.79
1.3|| |trr
Reverse RecoveryTime
IF= 25 A, di/dt = 100 A/μs
54
87
ns
Qrr
Reverse RecoveryCharge
42
67
nC
trr
Reverse RecoveryTime
IF= 25 A, di/dt = 300 A/μs
46
73
ns
Qrr
Reverse RecoveryCharge
84
134
nC
~~——————~~||| |Notes**:**||| |1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCAis determined by the user's board design.||| |a) 50 °C/W when mounted on a
1 in2pad of 2 oz copper
b) 125 °C/W when mounted on a
i)|b) 125 °C/W when mounted on a
minimum pad of 2 oz copper.|| |**G**
**DF**
**DS**
**SF**
**SS**
**G**
**DF**
**DS**
**SF**
**SS**||| 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 240 mJ is based on starting TJ = 25 °C, L = 0.3 mH, IAS = 40 A, VDD = 54 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 66 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. www.onsemi.com **2** ## **Typical Characteristics** TJ = 25 °C unless otherwise noted. **==> picture [223 x 351] intentionally omitted <==** **----- Start of picture text -----**
350
VGS = 10 V
VGS = 5 V
280
VGS = 4.5 V VGS = 4 V
210
140
VGS = 3.5 V
70
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
0
0 1 2 3 4 5
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
1.8
ID = 25 A
1.6 VGS = 10 V
1.4
1.2
1.0
0.8
0.6
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE ( [o] C)
, DRAIN CURRENT (A)
ID
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
**----- End of picture text -----**
**Figure 3. Normalized On- Resistance vs. Junction Temperature** **==> picture [221 x 177] intentionally omitted <==** **----- Start of picture text -----**
350
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
280
VDS = 5 V
210
140
TJ = 150 [o] C
TJ = 25 [o] C
70
TJ = -55 [o] C
0
1 2 3 4 5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**==> picture [223 x 169] intentionally omitted <==** **----- Start of picture text -----**
5
VGS = 3.5 V
4
VGS = 4 V
3
VGS = 4.5 V
2
1
PULSE DURATION = 80 μ s VGS = 5 V VGS = 10 V
DUTY CYCLE = 0.5% MAX
0
0 70 140 210 280 350
ID, DRAIN CURRENT (A)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
**----- End of picture text -----**
**Figure 2. vs. Drain Current and Gate Voltage** **==> picture [208 x 149] intentionally omitted <==** **----- Start of picture text -----**
10
ID = 25 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s
8
6
TJ = 125 [o] C
4
2
TJ = 25 [o] C
0
2 4 6 8 10
VGS, GATE TO SOURCE VOLTAGE (V)
)
Ω
m
(
DRAIN TO
rDS(on),
SOURCE ON-RESISTANCE
**----- End of picture text -----**
**Figure 4. Source Voltage** **==> picture [227 x 187] intentionally omitted <==** **----- Start of picture text -----**
500
V GS = 0 V
100
10
TJ = 150 [o] C
1
TJ = 25 [ o] C
0.1
0.01 TJ = -55 [o] C
0.001
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
www.onsemi.com **3** **Typical Characteristics** TJ = 25 °C unless otherwise noted. **==> picture [463 x 575] intentionally omitted <==** **----- Start of picture text -----**
10 50000
ID = 25 A VDD = 20 V
8 10000
Ciss
VDD = 30 V
6 1000 Coss
VDD = 40 V
4
100 Crss
2
f = 1 MHz
V GS = 0 V
0 10
0 20 40 60 80 100 120 0.1 1 10 60
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain
to Source Voltage
100 160
120
TJ = 25 [ o] C
VGS = 10 V
TJ = 100 [ o] C
10 80
VGS = 4.5 V
TJ = 125 [o] C
40
R θ JC = 1.2 [o] C/W
1 0
0.01 0.1 1 10 100 1000 25 50 75 100 125 150
tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)
Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain
Switching Capability Current vs. Case Temperature
1000 20000
10000 SINGLE PULSE
R θ JC = 1.2 [o] C/W
100 10 μ s TC = 25 [o] C
1000
10 THIS AREA IS 100 μ s
LIMITED BY r
DS(on)
SINGLE PULSE 1 ms 100
1 TJ = MAX RATED
R θ JC = 1.2 [ o] C/W CURVE BENT TO 10 msDC
T C = 25 [o] C MEASURED DATA
0.10.1 1 10 100 300 1010-5 10-4 10-3 10-2 10-1 1
VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum
Operating Area Power Dissipation
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
,
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)
ID
PEAK TRANSIENT POWER (W)
,
(PK)
P
**----- End of picture text -----**
www.onsemi.com **4** **==> picture [460 x 196] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TJ = 25 °C unless otherwise noted.
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1 0.1 PDM
0.05
0.02
0.01 t1
t 2
0.01 NOTES:
SINGLE PULSE Z θJC (t) = r(t) x R θJC
R θJC = 1.2 °C/W
Peak TJ = PDM x Z θJC (t) + TC
Duty Cycle, D = t1 / t2
0.00110-5 10-4 10-3 10-2 10-1 1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE TRANSIENT
**----- End of picture text -----**
www.onsemi.com **5** ## **Dimensional Outline and Pad Layout** **==> picture [413 x 427] intentionally omitted <==** **----- Start of picture text -----**
5.204.80 A 5.103.91
8 PKGCL 5 B SEEDETAIL B 8 7 6 0.645 1.27
0.77
4.52
PKG CL 6.255.90 5.855.65 3.75 6.61
KEEP OUT
AREA
1.27
1 4
1 2 3 4
TOP VIEW
1.27 0.61
3.81
LAN D PATTERN
OPTIONAL DRAFT REC OM MEND ATION
ANGLE MAY APPEAR
5.004.80 SEEDETAIL C OF THE PACKAGEON FOUR SIDES
0.35
0.15
0.10 C
SIDE VIEW 0.050.00 0.300.06
8X
0.08 C
0.35 C
0.15
1.10 SEATING
0.90 PLANE
3.81 DETAIL C DETAIL B
SCALE: 2:1 SCALE: 2:1
1.27 0.51
(0.34) 0 .31 [ (8X)] N OTES: UNLESS OTHERWISE SPECIFIED
0.10 C A B A. PACKAGE STAND ARD REFERENCE: JEDEC M O-240,
1 2 3 4 ISSUE A, VAR. AA, DATED OCTOBER 2002.
B. DIMENSIONS DO N OT INCLUDE BURRS OR MOLD FLASH.
0.76 MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
0.44 (0.52) C . ALL DIMEN SIONS ARE IN MILLIMETERS.
D . DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN TH E KEEP OUT AREA.
(0.50)(0.30) 3.783.38 4.223.99 F. DRAWING FILE NAME: PQFN08AREV8
(3.40) (2X )
8 7 6 5
0.64
3 .96 0.34
3.61
BOTTOM VIEW
**----- End of picture text -----**
_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ www.onsemi.com **6** **==> picture [133 x 113] intentionally omitted <==** **==> picture [81 x 120] intentionally omitted <==** **==> picture [45 x 35] intentionally omitted <==** **==> picture [80 x 43] intentionally omitted <==** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **PUBLICATION ORDERING INFORMATION** **N. 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