# Power MOSFET, N Channel, 150 V, 12 A, 0.056 ohm, Power 56, Surface Mount ![Product image](https://novapart.co/image/farnell:2825178/) **URL**: https://novapart.co/products/FDMS86252L/power-mosfet-n-channel-150-v-12-a-0056-ohm-56 **SKU**: FDMS86252L **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.8700 **Stock**: 10+ **Lead Time**: 141 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:12A; Drain Source Voltage Vds:150V; On Resistance Rds(on):0.046ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.5V ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | PowerTrench | | Qualification | - | | Power Dissipation | 50W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | Power 56 | | Drain Source Voltage Vds | 150V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 12A | | Drain Source On State Resistance | 0.056ohm | | Gate Source Threshold Voltage Max | 1.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2825178/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [58 x 7] intentionally omitted <==** **----- Start of picture text -----**
October 2014
**----- End of picture text -----**
## **FDMS86252L** ## **N-Channel Shielded Gate PowerTrench[®] MOSFET 150 V, 12 A, 56 m** Ω **Features** ## **General Description** This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench **[®]** process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. Shielded Gate MOSFET Technology Max rDS(on) = 56 mΩ at VGS = 10 V, ID = 4.4 A Max rDS(on) = 71 mΩ at VGS = 6 V, ID = 3.8 A Max rDS(on) = 75 mΩ at VGS = 4.5 V, ID = 3.7 A Advanced package and silicon combination for low rDS(on) and **Applications** high efficiency OringFET / Load Switching Next generation enhanced body diode technology, engineered for soft recovery Synchronous Rectification DC-DC Conversion MSL1 robust package design 100% UIL tested RoHS Compliant **==> picture [419 x 108] intentionally omitted <==** **----- Start of picture text -----**
Top Bottom
Pin 1
Pin 1 S <~ S S i} (3 D
S
\ G S 3 7 D
S D
D
D
D G D
D
Power 56
**----- End of picture text -----**
## **MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted |**MOSFET Maximum Ratings**|**MOSFET Maximum Ratings **TA = 25 °C unless otherwise notedA = 25 °C unless otherwise noted= 25 °C unless otherwise noted||| |---|---|---|---| |**Symbol**|**Parameter**|**Ratings**|**Units**| |VDS|Drain to Source Voltage|150|V| |VGS|Gate to Source Voltage|±20|V| |ID|Drain Current -Continuous
TC = 25 °C|12|A| ||-Continuous
TA= 25 °C(Note 1a)|4.4|| ||-Pulsed
(Note 4)|30|| |EAS|Single Pulse Avalanche Energy
(Note 3)|73|mJ| |PD|Power Dissipation
TC= 25 °C|50|W| ||Power Dissipation
TA= 25 °C
(Note 1a)|2.5|| |TJ, TSTG|Operatingand Storage Junction Temperature Range|-55 to +150|°C| ## **Thermal Characteristics** ## **Package Marking and Ordering Information** |**Device Marking**|**Device**|**Package**|**Reel Size**|**Tape Width**|**Quantity**| |---|---|---|---|---|---| |FDMS86252L|FDMS86252L|Power 56|13 ’’|12 mm|3000 units| www.fairchildsemi.com ©2013 Fairchild Semiconductor Corporation FDMS86252L Rev.C2 **1** ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted |**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250 μA, VGS= 0 V
150
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250 μA, referenced to 25 °C
104
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 120 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250 μA
1
1.5
3
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250 μA, referenced to 25 °C
-6
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 4.4 A
46
56
mΩ
VGS= 6 V, ID= 3.8 A
48
71
VGS= 4.5 V, ID= 3.7 A
52
75
VGS= 10 V, ID= 4.4 A,
TJ = 125 °C
90
110
gFS
Forward Transconductance
VDS= 5 V, ID= 4.4 A
21
S
Ciss
Input Capacitance
VDS= 75 V, VGS= 0 V,
f = 1 MHz
952
1335
pF
Coss
Output Capacitance
74
105
pF
Crss
Reverse Transfer Capacitance
3
5
pF
Rg
Gate Resistance
0.1
0.6
1.8
Ω
td(on)
Turn-On DelayTime
VDD= 75 V, ID= 4.4 A,
VGS= 10 V, RGEN= 6 Ω
6.8
14
ns
tr
Rise Time
1.4
10
ns
td(off)
Turn-Off DelayTime
19
34
ns
~~=~~
~~=~~
~~EE~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250 μA, VGS= 0 V
150
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250 μA, referenced to 25 °C
104
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 120 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250 μA
1
1.5
3
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250 μA, referenced to 25 °C
-6
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 4.4 A
46
56
mΩ
VGS= 6 V, ID= 3.8 A
48
71
VGS= 4.5 V, ID= 3.7 A
52
75
VGS= 10 V, ID= 4.4 A,
TJ = 125 °C
90
110
gFS
Forward Transconductance
VDS= 5 V, ID= 4.4 A
21
S
Ciss
Input Capacitance
VDS= 75 V, VGS= 0 V,
f = 1 MHz
952
1335
pF
Coss
Output Capacitance
74
105
pF
Crss
Reverse Transfer Capacitance
3
5
pF
Rg
Gate Resistance
0.1
0.6
1.8
Ω
td(on)
Turn-On DelayTime
VDD= 75 V, ID= 4.4 A,
VGS= 10 V, RGEN= 6 Ω
6.8
14
ns
tr
Rise Time
1.4
10
ns
td(off)
Turn-Off DelayTime
19
34
ns
~~=~~
~~=~~
~~EE~~| |---|---| |tf
Fall Time
2.9
10
ns|| |Qg
Total Gate Charge
VGS= 0 V to 10 V
VDD= 75 V,
ID= 4.4 A
15
21
nC
Qg
Total Gate Charge
VGS= 0 V to 4.5 V
7.6
11
nC
Qgs
Gate to Source Charge
2.1
nC
Qgd
Gate to Drain “Miller” Charge
2.3
nC
~~ae~~|| |**Drain-Source Diode Characteristics**|| |VSD
Source-Drain Diode Forward Voltage
VGS = 0 V, IS = 1.9 A(Note 2)
0.7
1.2
V
VGS = 0 V, IS = 4.4 A(Note 2)
0.8
1.3
trr
Reverse RecoveryTime
IF= 4.4 A, di/dt = 100 A/μs
53
85
ns
Qrr
Reverse RecoveryCharge
51
82
nC
Notes**:**
1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined by
the user's board design.
50 °C/W when mounted on a
1 in2pad of 2 oz copper
a.
125 °C/W when mounted on a
minimum pad of 2 oz copper.
b.
~~aD~~|~~aD~~| |**G**
**DF**
**DS**
**SF**
**SS**
**G**
**DF**
**DS**
**SF**
**SS**|| |2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.|| |3. EASof 73 mJ is based on Starting TJ= 25°C, L = 3 mH, IAS= 7 A, VDD= 150 V, VGS= 10 V. 100% tested at L =0.1 mH, IAS= 24 A.|| 4. Pulsed Id limited by junction temperature, td<=100 μS, please refer to SOA curve for more details. ©2013 Fairchild Semiconductor Corporation FDMS86252L Rev.C2 www.fairchildsemi.com **2** **Typical Characteristics** TJ = 25 °C unless otherwise noted **==> picture [454 x 584] intentionally omitted <==** **----- Start of picture text -----**
30 3.0
VGS = 10 V PULSE DURATION = 80 μ s PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
24 V GS = 6 V 2.5
VGS = 2.5 V
18 2.0
VGS = 4.5 V VGS = 3 V
VGS = 3.5 V
12 VGS = 3.5 V 1.5
VGS = 3 V
6 1.0
VGS = 2.5 V VGS = 4.5 V VGS = 6 V VGS = 10 V
0 0.5
0 1 2 3 4 5 0 6 12 18 24 30
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
2.4 150
ID = 4.4 A PULSE DURATION = 80 μ s
VGS = 10 V DUTY CYCLE = 0.5% MAX
2.0 120 ID = 4.4 A
1.6 TJ = 125 [o] C
90
1.2
60
0.8 TJ = 25 [o] C
0.4 30
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
30 30
PULSE DURATION = 80 μ s 10 V GS = 0 V
DUTY CYCLE = 0.5% MAX
24
VDS = 5 V TJ = 150 [o] C
1
18
TJ = 150 [o] C 0.1
12
TJ = 25 [o] C
T J = 25 [ o] C
6 0.01
TJ = -55 [o] C T J = -55 [o] C
0 0.001
1 2 3 4 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
NORMALIZED
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON-RESISTANCE
) Ω
(m
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
**Figure 5. Transfer Characteristics** **Figure 6. Source to Drain Diode Forward Voltage vs Source Current** ©2013 Fairchild Semiconductor Corporation FDMS86252L Rev.C2 www.fairchildsemi.com **3** **Typical Characteristics** TJ = 25 °C unless otherwise noted **==> picture [468 x 587] intentionally omitted <==** **----- Start of picture text -----**
10 10000
ID = 4.4 A
8 C iss
VDD = 50 V 1000
6 VDD = 75 V Coss
100
4
VDD = 100 V C rss
10
2
f = 1 MHz
VGS = 0 V
0 1
0 4 8 12 16 0.1 1 10 100
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain
to Source Voltage
30 24
R θ JC = 2.5 [o] C/W
TJ = 25 [ o] C 18
10
T J = 100 [ o] C 12 VGS = 10 V
VGS = 4.5 V
TJ = 125 [o] C 6
Limited by Package
1 0
0.001 0.01 0.1 1 10 25 50 75 100 125 150
tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)
Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain
Switching Capability Current vs Case Temperature
100 10000
SINGLE PULSE
10 us R θ JC = 2.5 [o] C/W
10
TC = 25 [o] C
1000
THIS AREA IS
100 us
1 LIMITED BY rDS(on)
SINGLE PULSE
T J = MAX RATED 1 ms 100
0.1 R θ JC = 2.5 [ o] C/W CURVE BENT TO 1 DC 0 ms
TC = 25 [o] C MEASURED DATA
0.01 10
0.1 1 10 100 500 10-5 10-4 10-3 10-2 10-1 1
VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
,
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)
ID
PEAK TRANSIENT POWER (W)
P)(PK,
**----- End of picture text -----**
**Figure 11. Forward Bias Safe Operating Area** **Figure 12. Single Pulse Maximum Power Dissipation** ©2013 Fairchild Semiconductor Corporation FDMS86252L Rev.C2 www.fairchildsemi.com **4** **==> picture [470 x 208] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2 PDM
0.1
0.05
0.1 0.02 0.01 t1
t2
NOTES:
Z θ JC (t) = r(t) x R θ JC
R θ JC = 2.5 [o] C/W
SINGLE PULSE Peak TJ = PDM x Z θ JC(t) + TC
0.01 Duty Cycle, D = t1 / t2
0.005
10-5 10-4 10-3 10-2 10-1 1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE TRANSIENT
**----- End of picture text -----**
©2013 Fairchild Semiconductor Corporation FDMS86252L Rev.C2 www.fairchildsemi.com **5** **==> picture [490 x 598] intentionally omitted <==** **----- Start of picture text -----**
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10 A 5.10
3.91
PKG SEE
1.27
CL B DETAIL B
8 5 8 7 6 5
0.77
4.52
3.75
PKG CL 6.15 5.85 6.61
5.65
KEEP OUT
AREA
1.27
1 4
1 2 3 4
TOP VIEW
1.27 0.61
3.81
LAND PATTERN
OPTIONAL DRAFT RECOMMENDATION
ANGLE MAY APPEAR
SEE ON FOUR SIDES
5.00
4.80 DETAIL C OF THE PACKAGE
0.35
0.15
������
0.10 C
0.30
0.05
0.05
SIDE VIEW 0.00 ������
8X
0.08 C
0.35 C
5.20 0.15
4.80 1.10 SEATING
0.90 PLANE
DETAIL C DETAIL B
3.81
SCALE: 2:1 SCALE: 2:1
1.27 0.51
0.31 [ (8X)]
(0.34) NOTES: UNLESS OTHERWISE SPECIFIED
0.10 C A B A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
1 2 3 4 ISSUE A, VAR. AA,.
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
0.76 MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
0.51 (0.52) C. ALL DIMENSIONS ARE IN MILLIMETERS.
6.25 D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
5.90 E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
(0.50) 3.48 [+0.30]
-0.10
(0.30)
(2X)
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0.20 [+0.10] 3.96
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3.61
**----- End of picture text -----**
**==> picture [63 x 8] intentionally omitted <==** **----- Start of picture text -----**
BOTTOM VIEW
**----- End of picture text -----**
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