# Dual MOSFET, N Channel, 30 V, 30 V, 28 A, 28 A, 6000 µohm ![Product image](https://novapart.co/image/farnell:3616881/) **URL**: https://novapart.co/products/FDML7610S/dual-mosfet-n-channel-30-v-28-a-6000-ohm **SKU**: FDML7610S **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Dual MOSFETs **Price**: €0.4610 **Stock**: 10+ **Lead Time**: 169 days (indicative) ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Transistor Case Style | MLP | | Operating Temperature Max | 150°C | | Power Dissipation N Channel | 2.2W | | Power Dissipation P Channel | 2.2W | | Drain Source Voltage Vds N Channel | 30V | | Drain Source Voltage Vds P Channel | 30V | | Continuous Drain Current Id N Channel | 28A | | Continuous Drain Current Id P Channel | 28A | | Drain Source On State Resistance N Channel | 6000µohm | | Drain Source On State Resistance P Channel | 6000µohm | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3616881/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [49 x 10] intentionally omitted <==** **----- Start of picture text -----**
April 2013
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## **FDML7610S** ## **PowerTrench[®] Power Stage Asymmetric Dual N-Channel MOSFET** ## **Features** Q1: N-Channel Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A - Q2: N-Channel Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 17 A Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 14 A RoHS Compliant ## **General Description** This device includes two specialized N-Channel MOSFETs in a dual MLP package.The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET[TM] (Q2) have been designed to provide optimal power efficiency. ## **Applications** Computing Communications General Purpose Point of Load Notebook VCORE **==> picture [415 x 121] intentionally omitted <==** **----- Start of picture text -----**
Pin 1
G1 [D1 D1D1]
D1 S2 5 Q2 4 D1
PHASE
(S1/D2) S2 6 PHASE 3 D1
S2 7 2 D1
S2
S2
° G2S2 G2 Hep 8 Q1 TE 1 G1
Top MLP 3X4.5 Bottom
**----- End of picture text -----**
## **MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted |**MOSFET Maximum Ratings**|**MOSFET Maximum Ratings **TA = 25 °C unless otherwise notedA = 25 °C unless otherwise noted= 25 °C unless otherwise noted|||| |---|---|---|---|---| |**Symbol**|**Parameter**|**Q1**|**Q2**|**Units**| |VDS|Drain to Source Voltage|30|30|V| |VGS|Gate to Source Voltage(Note 3)|±20|±20|V| |ID|Drain Current -Continuous(Package limited)TC = 25 °C|30|28|A| ||-Continuous(Silicon limited)TC = 25 °C|40|60|| ||-Continuous TA= 25 °C|121a|171b|| ||-Pulsed|40|40|| |PD|Power Dissipation for Single Operation TA= 25 °C|2.11a|2.21b|W| ||TA= 25 °C|0.81c|0.91d|| |TJ, TSTG|Operatingand Storage Junction Temperature Range|-55 to +150||°C| **Thermal Characteristics** RθJA Thermal Resistance, Junction to Ambient 60[1a] 56[1b] RθJA Thermal Resistance, Junction to Ambient 150[1c] 140[1d] °C/W ~~ae~~ RθJC Thermal Resistance, Junction to Case 4 3.5 **Package Marking and Ordering Information Device Marking Device Package Reel Size Tape Width Quantity** FDML7610S FDML7610S MLP3X4.5 13 ” 12 mm 3000 units ~~en~~ ©2013 Fairchild Semiconductor Corporation **1** FDML7610S Rev.C1 www.fairchildsemi.com ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted |**Electrica**|**l Characteristics**TJ= 25 °C u|nless otherwise noted|||||||| |---|---|---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**||**Typ**|**Max**||**Units**| |**Off Characteristics**|||||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V
ID= 1 mA, VGS= 0 V|Q1
Q2|30
30|||||V| |ΔBVDSS
ΔTJ|Breakdown Voltage Temperature
Coefficient|ID= 250μA, referenced to 25 °C
ID= 10 mA, referenced to 25 °C|Q1
Q2|||15
14|||mV/°C| |IDSS|Zero Gate Voltage Drain Current|VDS= 24 V, VGS= 0 V|Q1
Q2||||1
500||μA
μA| |IGSS|Gate to Source Leakage Current|VGS= 20 V, VDS= 0 V|Q1
Q2||||100
100||nA
nA| |**On Characteristics**|||||||||| |VGS(th)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250μA
VGS= VDS, ID= 1 mA|Q1
Q2|1
1||1.8
1.8|3
3||V| |ΔVGS(th)
ΔTJ|Gate to Source Threshold Voltage
Temperature Coefficient|ID= 250μA, referenced to 25 °C
ID= 10 mA, referenced to 25 °C|Q1
Q2|||-6
-5|||mV/°C| |rDS(on)|Drain to Source On Resistance|VGS= 10 V, ID= 12 A
VGS= 4.5 V, ID= 10 A
VGS= 10 V, ID= 12 A , TJ= 125 °C|Q1|||6.0
8.5
8.3|7.5
12
12||mΩ| |||VGS= 10 V, ID= 17 A
VGS= 4.5 V, ID= 14 A
VGS= 10 V, ID= 17 A , TJ= 125 °C|Q2|||3.2
4.1
4.1|4.2
5.5
6||| |gFS|Forward Transconductance|VDS= 5 V, ID= 12 A
VDS= 5 V, ID= 17 A|Q1
Q2|||63
86|||S| |**Dynamic Characteristics**|||||||||| |Ciss|Input Capacitance|Q1:
VDS= 15 V, VGS= 0 V, f = 1 MHZ
Q2:
VDS= 15 V, VGS= 0 V, f = 1 MHZ|Q1
Q2|||1315
2960|1750
3940||pF| |Coss|Output Capacitance||Q1
Q2|||455
1135|600
1510||pF| |Crss|Reverse Transfer Capacitance||Q1
Q2|||45
100|70
150||pF| |Rg|Gate Resistance||Q1
Q2|||0.9
0.6|||Ω| |**Switching Characteristics**|||||||||| |td(on)|Turn-On Delay Time|Q1:
VDD= 15 V, ID= 12 A,
VGS= 10 V, RGEN= 6Ω
Q2:
VDD= 15 V, ID= 17 A,
VGS= 10 V, RGEN= 6Ω|Q1
Q2|||8.6
13||18
23|ns| |tr|Rise Time||Q1
Q2|||2.5
4||10
10|ns| |td(off)|Turn-Off Delay Time||Q1
Q2|||20
31||32
49|ns| |tf|Fall Time||Q1
Q2|||2.3
3.1||10
10|ns| |Qg|Total Gate Charge|VGS= 0 V to 10 V|Q1
Q2|||20
43||28
60|nC| |Qg|Total Gate Charge|VGS= 0 V to 4.5 V|Q1
Q2|||9.3
20||13
28|nC| |Qgs|Gate to Source Gate Charge||Q1
Q2|||4.3
8.9|||nC| |Qgd|Gate to Drain “Miller” Charge||Q1
Q2|||2.2
4.7|||nC| www.fairchildsemi.com ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 **2** |**Electrical Characteristics**TJ= 25 °C unless otherwise noted
**Drain-Source Diode Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
VSD
Source to Drain Diode Forward Voltage VGS= 0 V, IS= 12 A (Note 2)
VGS = 0 V, IS = 17 A(Note 2)
trr
Reverse Recovery Time
Q1
IF= 12 A, di/dt = 100 A/μs
Q2
IF= 17 A, di/dt = 300 A/μs
Qrr
Reverse Recovery Charge
**Notes:**
**1:** RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
by the user's board design.
~~a~~|**Type**
**Min**
**Typ**
**Max**
**Units**
Q1
Q2
0.8
0.8
1.2
1.2
V
Q1
Q2
27
35
43
56
ns
Q1
Q2
10
40
18
64
nC
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined| |---|---| **==> picture [297 x 131] intentionally omitted <==** **----- Start of picture text -----**
b. 56 °C/W when mounted on
a. 60 °C/W when mounted on a 1 in [2 ] pad of 2 oz copper a 1 in [2 ] pad of 2 oz copper
Be86e
c. 150 °C/W when mounted on a d. 140 °C/W when mounted on a
minimum pad of 2 oz copper minimum pad of 2 oz copper
**----- End of picture text -----**
- **2:** Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. - **3:** As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 www.fairchildsemi.com **3** ## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted **==> picture [469 x 576] intentionally omitted <==** **----- Start of picture text -----**
40 4
VGS = 10 V PULSE DURATION = 80 μ s
VGS = 6 V DUTY CYCLE = 0.5% MAX
30 3
VGS = 4.5 V VGS = 3.5 V
VGS = 4 V VGS = 4 V
20 2
VGS = 4.5 V
10 1
VGS = 3.5 V PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s VGS = 6 V VGS = 10 V
0 0
0.0 0.5 1.0 1.5 2.0 0 10 20 30 40
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6 40
ID = 12 A PULSE DURATION = 80 μ s
VGS = 10 V DUTY CYCLE = 0.5% MAX
1.4 30
ID = 12 A
1.2 20
TJ = 125 [ o] C
1.0 10
TJ = 25 [o] C
0.8 0
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance Figure 4. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
40 40
PULSE DURATION = 80 μ s VGS = 0 V
DUTY CYCLE = 0.5% MAX 10
30
VDS = 5 V 1
TJ = 150 [o] C
TJ = 150 [o] C
20
0.1 TJ = 25 [ o] C
TJ = 25 [o] C
10
0.01
TJ = -55 [o] C
TJ = -55 [o] C
0 0.001
1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
NORMALIZED
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON-RESISTANCE
)
Ω
m
(
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
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©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 www.fairchildsemi.com **4** ## **Typical Characteristics (Q1 N-Channel)** TJ = 25 °C unless otherwise noted **==> picture [471 x 584] intentionally omitted <==** **----- Start of picture text -----**
10 2000
ID = 12 A
1000 Ciss
8
VDD = 10 V
6 Coss
VDD = 15 V
100
4
VDD = 20 V
2
Crss
f = 1 MHz
VGS = 0 V
0 10
0 5 10 15 20 0.1 1 10 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain
to Source Voltage
60 100
VGS = 10 V R θ JC = 4 [o] C/W 100us
10
40
1 ms
VGS = 4.5 V
1 10 ms
THIS AREA IS
20 Limited by Package LIMITED BY rDS(on) 100 ms
SINGLE PULSE 1s
0.1 TJ = MAX RATED 10s
R θ JA = 150 [o] C/W DC
T A = 25 [o] C
0 0.01
25 50 75 100 125 150 0.01 0.1 1 10 100 200
TC, CASE TEMPERATURE (oC) VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Maximum Continuous Drain Current vs Figure 10. Forward Bias Safe Operating Area
Case Temperature
1000
SINGLE PULSE
R θ JA = 150 [o] C/W
100 TA = 25 [o] C
10
1
0.5
10-4 10-3 10-2 10-1 1 10 100 1000
t, PULSE WIDTH (s)
Figure 11. Single Pulse Maximum Power Dissipation
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
I, D , DRAIN CURRENT (A)ID
, PEAK TRANSIENT POWER (W)
(PK)
P
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www.fairchildsemi.com ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 **5** **==> picture [469 x 199] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1 0.05
0.02 PDM
0.01
t1
0.01 SINGLE PULSE t2
R θ JA = 150 [o] C/W NOTES:DUTY FACTOR: D = t1/t2
( Note 1c ) PEAK T J = P DM x Z θJA x R θJA + T A
0.001
10-4 10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
Z JA θ
IMPEDANCE,
NORMALIZED THERMAL
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**Figure 12. Junction-to-Ambient Transient Thermal Response Curve** ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 www.fairchildsemi.com **6** ## **Typical Characteristics (Q2 N-Channel)** TJ = 25[o] C unlenss otherwise noted **==> picture [468 x 588] intentionally omitted <==** **----- Start of picture text -----**
40 6
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
VGS = 10 V 5
30 VGS = 3 V
VGS = 4.5 V 4
VGS = 4 V
20 3
VGS = 3.5 V VGS = 3.5 V
2
10
PULSE DURATION = 80 μ s 1
VGS = 3 V DUTY CYCLE = 0.5% MAX VGS = 4 V VGS = 4.5 V VGS = 10 V
0 0
0.0 0.2 0.4 0.6 0.8 0 10 20 30 40
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 13. On-Region Characteristics Figure 14. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6 20
IVDGS = 17 A = 10 V ID = 17 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s
1.4
15
1.2
10
1.0
TJ = 125 [ o] C
5
0.8
TJ = 25 [o] C
0.6 0
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 15. Normalized On-Resistance Figure 16. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
40 40
PULSE DURATION = 80 μ s VGS = 0 V
DUTY CYCLE = 0.5% MAX
10
VDS = 5 V
30
TJ = 125 [o] C
TJ = 125 [o] C
1
20
TJ = 25 [ o] C
TJ = 25 [o] C
0.1
10
TJ = -55 [o] C TJ = -55 [o] C
0 0.01
1.5 2.0 2.5 3.0 3.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 17. Transfer Characteristics Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
NORMALIZED
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON-RESISTANCE
)
Ω
m
(
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
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©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 www.fairchildsemi.com **7** ## **Typical Characteristics (Q2 N-Channel)** TJ = 25[o] C unless otherwise noted **==> picture [469 x 583] intentionally omitted <==** **----- Start of picture text -----**
10 5000
ID = 17A
8 Ciss
VDD = 10 V
6 1000
C oss
VDD = 15 V
4
VDD = 20 V
2
100 f = 1 MHz
0 60 VGS = 0 V Crss
0 10 20 30 40 50 0.1 1 10 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 19. Gate Charge Characteristics Figure 20. Capacitance vs Drain
to Source Voltage
80 100
VGS = 10 V R θ JC = 3.5 [o] C/W
60 10
1 ms
VGS = 4.5 V
10 ms
40 1 THIS AREA IS
LIMITED BY rDS(on) 100 ms
SINGLE PULSE 1s
20 Limited by package 0.1 TJ = MAX RATED 10s
R θ JA = 140 [o] C/W
DC
T A = 25 [o] C
0 0.01
25 50 75 100 125 150 0.01 0.1 1 10 100 200
TC, CASE TEMPERATURE (oC) VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 21. Maximun Continuous Drain Figure 22. Forward Bias Safe
Current vs Case Temperature Operating Area
300
SINGLE PULSE
R θ JA = 140 [o] C/W
100
TA = 25 [o] C
10
1
0.001 0.01 0.1 1 10 100 1000
t, PULSE WIDTH (sec)
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
I, D , DRAIN CURRENT (A)ID
PEAK TRANSIENT POWER (W)
P)(PK,
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**Figure 23. Single Pulse Maximum Power Dissipation** www.fairchildsemi.com ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 **8** **==> picture [363 x 13] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics (Q2 N-Channel) TJ = 25 [o] C unless otherwise noted
**----- End of picture text -----**
**==> picture [444 x 162] intentionally omitted <==** **----- Start of picture text -----**
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1 0.05
0.02 PDM
0.01
t1
0.01 SINGLE PULSE t2
R θ JA = 140 [o] C/W NOTES:DUTY FACTOR: D = t 1 /t 2
Note 1d PEAK T J = P DM x Z θJA x R θJA + T A
0.001
10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
Z JA θ
IMPEDANCE,
NORMALIZED THERMAL
**----- End of picture text -----**
**Figure24. Junction-to-Ambient Transient Thermal Response Curve** **==> picture [72 x 6] intentionally omitted <==** **----- Start of picture text -----**
www.fairchildsemi.com
**----- End of picture text -----**
©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 **9** ## **Typical Characteristics** (continued) ## **SyncFET[TM] Schottky body diode Characteristics** Fairchild’s SyncFET[TM] process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 25 shows the reverse recovery characteristic of the FDML7610S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. **==> picture [450 x 172] intentionally omitted <==** **----- Start of picture text -----**
20 10000
15 T J = 125 [o] C
1000
di/dt = 300 A/ μ s TJ = 100 [o] C
10
100
5
10
0 TJ = 25 [o] C
-5 1
0 50 100 150 200 250 0 5 10 15 20 25 30
TIME (ns) VDS, REVERSE VOLTAGE (V)
CURRENT (A)
, REVERSE LEAKAGE CURRENT (A)
IDSS
**----- End of picture text -----**
**Figure 25. FDML7610S SyncFET[TM] body diode reverse recovery characteristic** **Figure 26. SyncFET[TM] body diode reverse leakage versus drain-source voltage** ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 www.fairchildsemi.com **10** ## **Application Information** ## **1. Switch Node Ringing Suppression** Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. > 1||I }ty | lI | | i[ !| Chl Sov M20.0neS0G54 IT 8.0nehx M20.Onr 5.005% IT B.Opetat AChi + SOY AChI5.0" **Power Stage Device Competitors solution** *Patent Pending FDML7610S Rev.C1 ©2013 Fairchild Semiconductor Corporation www.fairchildsemi.com **11** ## **2. Recommended PCB Layout Guidelines** As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. **==> picture [189 x 10] intentionally omitted <==** ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 **==> picture [9 x 6] intentionally omitted <==** **----- Start of picture text -----**
12
**----- End of picture text -----**
www.fairchildsemi.com ## **Following is a guideline, not a requirement which the PCB designer should consider:** 1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage. 3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness. 4. The PowerTrench[®] Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing. 5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part. 6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET. 7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. ©2013 Fairchild Semiconductor Corporation FDML7610S Rev.C1 www.fairchildsemi.com **13** **==> picture [220 x 209] intentionally omitted <==** **==> picture [180 x 229] intentionally omitted <==** **==> picture [220 x 60] intentionally omitted <==** **==> picture [251 x 229] intentionally omitted <==** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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