# Power MOSFET, Shielded Gate, N Channel, 150 V, 25 A, 0.034 ohm, PQFN, Surface Mount ![Product image](https://novapart.co/image/farnell:3003970RL/) **URL**: https://novapart.co/products/FDMC86260/power-mosfet-shielded-gate-n-channel-150-v-25-a **SKU**: FDMC86260 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.9920 **Stock**: 1000+ **Lead Time**: 134 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:25A; Drain Source Voltage Vds:150V; On Resistance Rds(on):0.027ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:2.7V; Powe ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 8Pins | | Channel Type | N Channel | | Product Range | PowerTrench | | Qualification | - | | Power Dissipation | 54W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | PQFN | | Drain Source Voltage Vds | 150V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 25A | | Drain Source On State Resistance | 0.034ohm | | Gate Source Threshold Voltage Max | 2.7V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3003970RL/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [70 x 10] intentionally omitted <==** **----- Start of picture text -----**
September 2016
**----- End of picture text -----**
## **FDMC86260** ## **N-Channel Shielded Gate PowerTrench[®] MOSFET 150 V, 25 A, 34 m** Ω ## **Features** i[|] Shielded Gate MOSFET Technology i[|] Max rDS(on) = 34 mΩ at VGS = 10 V, ID = 5.4 A i[|] Max rDS(on) = 44 mΩ at VGS = 6 V, ID = 4.8 A High Performance Technology for Extremely Low rDS(on) 100% UIL Tested Termination is Lead-free RoHS Compliant ## **General Description** This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced PowerTrench **[®]** process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. ## **Application** DC-DC Conversion ||**Pin 1**
**D D**|**Pin 1**
**D**
**S**
**D**|**S**|**S**|**S**|**G**||**S**
**S**
**S**
**G**||7
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**D**
**D**
**D**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||**Top**|**Bottom**||||||||||||| ||**Power 33**|||||||||||||| |**MOSFET Maximum Ratings**|**MOSFET Maximum Ratings **TA= 25 °C unless otherwise noted.|= 25 °C unless otherwise noted.||||||||||||| |**Symbol**||**Parameter**||||||||**Ratings**||||**Units**| |VDS|Drain to Source Voltage|||||||||150||||V| |VGS|Gate to Source Voltage|||||||||±20||||V| ||Drain Current -Continuous T||Drain Current -Continuous TC|= 25 °C|||= 25 °C(Note 5|Note 5)||25||||| |ID|-Continuous T
-Continuous T||-Continuous TC
-Continuous TA|= 100°C
A= 25 °C|||= 100°C(Note 5)
= 25 °C(Note 1a)|||16
5.4||||A| ||-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed|-Pulsed(Note 4)|||135||||| |EAS|Single Pulse Avalanche Energy||||||(Note 3)|||121||||mJ| |PD|Power Dissipation T
Power Dissipation T|ation T
ation T|ation TC= 25 °C
ation TA= 25 °C|= 25 °C
= 25 °C|||= 25 °C(Note 1a|Note 1a)||54
2.3||||W| |TJ, TSTG|Operatingand Storage Junction Tem|e Junction Temperature Range||||||||-55 to +150||||°C| |**Thermal Characteristics**||||||||||||||| |RθJC
RθJA|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|Thermal Resistance, Junction to Case (Note 1)
Thermal Resistance, Junction to Ambient (Note 1a)|||2.3
53||||°C/W| |**Package Marking and Ordering Information**||||||||||||||| |**Device Marking**
**Device**||**Package**||||**Reel Size**||||**Tape Width**||**Quantity**||| |FDMC86260
FDMC86260||Power33|||||13 ’’|||12 mm||3000 units||3000 units| **MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted. ## **Thermal Characteristics** ## **Package Marking and Ordering Information** www.fairchildsemi.com **1** ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. |**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
150
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
110
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 120 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
2
2.7
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-9
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 5.4 A
27
34
mΩ
VGS= 6 V, ID= 4.8 A
31
44
VGS= 10 V, ID= 5.4 A, TJ= 125 °C
55
69
gFS
Forward Transconductance
VDD= 10 V, ID= 5.4 A
19
S
Ciss
Input Capacitance
VDS= 75 V, VGS= 0 V,
f = 1 MHz
1000
1330
pF
Coss
Output Capacitance
105
140
pF
Crss
Reverse Transfer Capacitance
4.8
10
pF
Rg
Gate Resistance
0.1
0.6
1.8
Ω
td(on)
Turn-On DelayTime
VDD= 75 V, ID= 5.4 A,
VGS= 10 V, RGEN= 6Ω
9.5
19
ns
tr
Rise Time
2
10
ns
td(off)
Turn-Off DelayTime
17
30
ns
tf
Fall Time
3.3
10
ns
Qg(TOT)
Total Gate Charge
VGS = 0 V to 10 V
VDD= 75 V,
ID= 5.4 A
15
21
nC
Qg(TOT)
Total Gate Charge
VGS = 0 V to 6 V
9.7
14
nC
Qgs
Total Gate Charge
4.0
nC
Qgd
Gate to Drain “Miller” Charge
3.1
nC
~~——SSESEE~~
~~a~~
~~So~~
~~=~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min.**
**Typ.**
**Max.**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= 250μA, VGS= 0 V
150
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 250μA, referenced to 25 °C
110
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 120 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS= ±20 V, VDS = 0 V
±100
nA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250μA
2
2.7
4
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 250μA, referenced to 25 °C
-9
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 5.4 A
27
34
mΩ
VGS= 6 V, ID= 4.8 A
31
44
VGS= 10 V, ID= 5.4 A, TJ= 125 °C
55
69
gFS
Forward Transconductance
VDD= 10 V, ID= 5.4 A
19
S
Ciss
Input Capacitance
VDS= 75 V, VGS= 0 V,
f = 1 MHz
1000
1330
pF
Coss
Output Capacitance
105
140
pF
Crss
Reverse Transfer Capacitance
4.8
10
pF
Rg
Gate Resistance
0.1
0.6
1.8
Ω
td(on)
Turn-On DelayTime
VDD= 75 V, ID= 5.4 A,
VGS= 10 V, RGEN= 6Ω
9.5
19
ns
tr
Rise Time
2
10
ns
td(off)
Turn-Off DelayTime
17
30
ns
tf
Fall Time
3.3
10
ns
Qg(TOT)
Total Gate Charge
VGS = 0 V to 10 V
VDD= 75 V,
ID= 5.4 A
15
21
nC
Qg(TOT)
Total Gate Charge
VGS = 0 V to 6 V
9.7
14
nC
Qgs
Total Gate Charge
4.0
nC
Qgd
Gate to Drain “Miller” Charge
3.1
nC
~~——SSESEE~~
~~a~~
~~So~~
~~=~~| |---|---| |**Drain-Source Diode Characteristics**|| |VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 5.4 A (Note 2)
0.77
1.3
V
VGS = 0 V, IS = 1.9 A (Note 2)
0.72
1.2
V
trr
Reverse RecoveryTime
IF= 5.4 A, di/dt = 100 A/μs
64
102
ns
Qrr
Reverse RecoveryCharge
85
137
nC
~~ne~~|| |Notes:|| |1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined by|is determined by| |the user's board design.|| |53 °C/W when mounted on a
1 in2pad of 2 oz copper
125 °C/W when mounted on
a minimum pad of 2 oz copper
a.
b.|| |**G**
**DF**
**DS**
**SF**
**SS**|| |**G**
**DF**
**DS**
**SF**
**SS**|| 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 121 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 9 A, VDD = 150 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 22 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 **2** www.fairchildsemi.com ## **Typical Characteristics** TJ = 25 °C unless otherwise noted. **==> picture [469 x 576] intentionally omitted <==** **----- Start of picture text -----**
48 4
VGS = 10 V VGS = 5.5 V VGS = 4.5 V
VGS = 6 V VGS = 5 V
36 3
VGS = 5.5 V
24 VGS = 5 V 2
PULSE DURATION = 80 μ s VGS = 6 V
DUTY CYCLE = 0.5% MAX
12 1
VGS = 4.5 V PULSE DURATION = 80 μ s VGS = 10 V
DUTY CYCLE = 0.5% MAX
0 0
0 1 2 3 4 5 0 12 24 36 48
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
2.8 120
2.4 ID = 5.4 A ID = 5.4 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s
VGS = 10 V 90
2.0
TJ = 125 [o] C
1.6 60
1.2
30
0.8 TJ = 25 [o] C
0.4 0
-75 -50 -25 0 25 50 75 100 125 150 3 4 5 6 7 8 9 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On- Resistance Figure 4. On-Resistance vs. Gate to
vs. Junction Temperature Source Voltage
48 100
PULSE DURATION = 80 μ s VGS = 0 V
DUTY CYCLE = 0.5% MAX
10
36
VDS = 5 V TJ = 150 [o] C
1
24 TJ = 25 [ o] C
TJ = 150 [o] C 0.1
12 TJ = 25 [o] C TJ = -55 [o] C
0.01
TJ = -55 [o] C
0 0.001
2 3 4 5 6 7 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
NORMALIZED
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON-RESISTANCE
) Ω
(m
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 **3** www.fairchildsemi.com **Typical Characteristics** TJ = 25 °C unless otherwise noted. **==> picture [469 x 575] intentionally omitted <==** **----- Start of picture text -----**
10 2000
ID = 5.4 A VDD = 75 V 1000 Ciss
8
VDD = 50 V VDD = 100 V
6 100 Coss
4
10
2 f = 1 MHz
VGS = 0 V C rss
0 1
0 4 8 12 16 0.1 1 10 100
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain
to Source Voltage
30
20
25
10
20
TJ = 25 [ o] C VGS = 10 V
15
TJ = 100 [o] C
VGS = 6 V
10
TJ = 125 [o] C R θ JC = 2.3 [o] C/W
5
0
1
25 50 75 100 125 150
0.001 0.1 1 10 20
tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)
Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain
Switching Capability Current vs. Case Temperature
200
100 2000
1000 SINGLE PULSE
10 R θ JA = 125 [o] C/W
TA = 25 [o] C
1 100 µ s 100
1 ms
THIS AREA IS
10 ms
0.1 LIMITED BY r DS(on) 100 ms 10
SINGLE PULSE
1 s
0.01 T J = MAX RATED 10 s
R θ JA = 125 [ o] C/W CURVE IS BENT DC
TA = 25 [o] C TO ACTUAL DATA 1
0.001
0.01 0.1 1 10 100 800 0.510-4 10-3 10-2 10-1 1 10 100 1000
VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum
Operating Area Power Dissipation
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
,
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)
ID
PEAK TRANSIENT POWER (W)
P)(PK,
**----- End of picture text -----**
©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 **4** www.fairchildsemi.com **==> picture [470 x 196] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TJ = 25 °C unless otherwise noted.
2
1 DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.1 0.05 P DM
0.02
0.01
t1
0.01 t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
R θ JA = 125 [o] C/W PEAK TJ = PDM x Z θJA x R θJA + TA
0.001
0.0005
10-4 10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
Z JA θ
IMPEDANCE,
NORMALIZED THERMAL
**----- End of picture text -----**
©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 **5** www.fairchildsemi.com ## **Dimensional Outline and Pad Layout** **==> picture [381 x 475] intentionally omitted <==** **----- Start of picture text -----**
3.40 A 2.37 MIN
3.20
PKG SYM
CL B (0.45) 8 CL 5
8 5
PKG CL 3.403.20 PKG CL (0.40) 2.15 MIN
(0.65)
0.70 MIN
1 4
PIN 1 1 4
INDICATOR 0.65 0.42 MIN
1.95 (8X)
SEE
DETAIL A LAND PATTE RN
RECOM MENDATION
0.10 C A B 1.95
0.37
0.27 [ (8X)] 0.65
0.50
1 4 0.30
PKG LC
2.05
1.85
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34) 8 5 A) PACKAGE STANDARD REFERENCE:
(0.33) TYP JEDEC MO-240, ISSUE A, VAR. BA,
(0.52 TYP) (2.27) DATED OCTOBER 2002.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
0.10 C D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
0.80 E) DRAWING FILE NAME: PQFN08HREV1
0.70
0.08 C 0.05 C
0.00
0.25
0.15 SEATING
PLANE
DETAIL A
SCALE: 2X
**----- End of picture text -----**
_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 **6** www.fairchildsemi.com ## **TRADEMARKS** The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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notice to improve design.| |No Identification Needed|Full Production|Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.| |Obsolete|Not In Production|Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.| Rev. I77 ©2012 Fairchild Semiconductor Corporation FDMC86260 Rev. 1.2 **7** www.fairchildsemi.com **==> picture [204 x 175] intentionally omitted <==** **----- Start of picture text -----**
3.40
A
3.20
PKG
CL
B
8 5
3.40
PKG [C] L 3.20
1 4
PIN 1
INDICATOR
**----- End of picture text -----**
**==> picture [43 x 19] intentionally omitted <==** **----- Start of picture text -----**
SEE
DETAIL A
**----- End of picture text -----**
**==> picture [180 x 192] intentionally omitted <==** **----- Start of picture text -----**
2.37 MIN
SYM
[C] L
(0.45) 8 5
2.15 MIN
(0.40)
PKG
CL
(0.65)
0.70 MIN
1 4
0.65 0.42 MIN
1.95 (8X)
**----- End of picture text -----**
LAND PATTERN RECOMMENDATION **==> picture [212 x 186] intentionally omitted <==** **----- Start of picture text -----**
0.10 C A B 1.95
0.37
0.65
0.27 [ (8X)]
0.50
1 4 0.30
PKG LC
2.05
1.85
8 5
(0.34)
(0.33) TYP
(0.52 TYP) (2.27)
**----- End of picture text -----**
NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. BA, DATED OCTOBER 2002. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. **==> picture [225 x 122] intentionally omitted <==** **----- Start of picture text -----**
0.10 C
0.80
0.70
0.08 C 0.05
C
0.00
0.25
SEATING
0.15
PLANE
SCALE: 2X
**----- End of picture text -----**
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