# MOSFET, N CHANNEL, 25V, 0.0025OHM, 40A, POWER 33-8 ![Product image](https://novapart.co/image/farnell:2459641/) **URL**: https://novapart.co/products/FDMC7572S/mosfet-n-channel-25v-00025ohm-40a-power-33-8 **SKU**: FDMC7572S **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €1.1700 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 8Pins | | Channel Type | N Channel | | Power Dissipation | 52W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 52W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.0025ohm | | Transistor Case Style | Power 33 | | Drain Source Voltage Vds | 25V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 40A | | Drain Source On State Resistance | 0.0025ohm | | Gate Source Threshold Voltage Max | 1.7V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2459641/) ## **Is Now Part of** **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **August 2011** ## ## **N-Channel Power Trench[®] SyncFET[TM] 25 V, 40 A, 3.15 m** Ω ## **Features** Max rDS(on) = 3.15 mΩ at VGS = 10 V, ID = 22.5 A Max rDS(on) = 4.7 mΩ at VGS = 4.5 V, ID = 18 A Advanced Package and Silicon combination for low rDS(on) and high efficiency SyncFET Schottky Body Diode 100% UIL Tested RoHS Compliant ## **General Description** The FDMC7572S has been designed to minimize losses in power conversion application. Advancements in both silicon and package technologies have been combined to offer the lowest rDS(on) while maintaining excellent switching performance. This device has the added benefit of an efficient monolithic Schottky body diode. ## **Applications** Synchronous Rectifier for DC/DC Converters Notebook Vcore/ GPU low side switch Networking Point of Load low side switch Telecom secondary side rectification **==> picture [472 x 376] intentionally omitted <==** **----- Start of picture text -----**
||||||| |---|---|---|---|---|---| |Top|Bottom| |Pin 1| |S|D|5|4|G| |S| |S| |G|D|6|3|S| |D|7|2|S| |D| |D|D|8|1|S| |es|D| |D| |Power 33| |MOSFET Maximum Ratings|TA = 25 °C unless otherwise noted| |Symbol|Parameter|Ratings|Units| |VDS|Drain to Source Voltage|25|V| |VGS|Gate to Source Voltage (Note 4)|±20|V| |Drain Current -Continuous (Package limited) TC|= 25 °C|40| |ID|-Continuous T -Continuous (Silicon limited)|TCA = 25 °C = 25 °C (Note 1a)|22.5103|A| |-Pulsed|120| |EAS|Single Pulse Avalanche Energy|(Note 3)|84|mJ| |PD|Power DissiPower Dissippation Tation|TAC = 25 °C= 25 °C (Note 1a)|2.352|W| |TJ, TSTG|Operating and Storage Junction Temperature Range|-55 to +150|°C| |Thermal Characteristics| |RθJC|Thermal Resistance, Junction to Case|2.4| |°C/W| |RθJA|Thermal Resistance, Junction to Ambient (Note 1a)|53| |ee| |Package Marking and Ordering Information| |Device Marking|Device|Package|Reel Size|Tape Width|Quantity| |FDMC7572S|FDMC7572S|Power 33|13 ’’|12 mm|3000 units| |J}ff}f+|f+ —_| **----- End of picture text -----**
www.fairchildsemi.com ©2011 Fairchild Semiconductor Corporation **1** FDMC7572S Rev.C1 **Electrical Characteristics** TJ = 25 °C unless otherwise noted |**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
**Off Characteristics**
BVDSS
Drain to Source Breakdown Voltage
ID= 1 mA, VGS= 0 V
25
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 10 mA, referenced to 25 °C
21
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 20 V, VGS = 0 V
500
μA
IGSS
Gate to Source Leakage Current, Forward VGS= 20 V, VDS = 0 V
100
nA
**On Characteristics**
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 1 mA
1.2
1.7
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 10 mA, referenced to 25 °C
-5
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 22.5 A
2.5
3.15
mΩ
VGS= 4.5 V, ID= 18 A
3.6
4.7
VGS= 10 V, ID= 22.5 A, TJ = 125 °C
3.5
4.5
gFS
Forward Transconductance
VDS= 5 V, ID= 22.5 A
122
S
**Dynamic Characteristics**
Ciss
Input Capacitance
VDS= 13 V, VGS= 0 V,
f = 1 MHz
2031
2705
pF
Coss
Output Capacitance
596
795
pF
Crss
Reverse Transfer Capacitance
134
205
pF
Rg
Gate Resistance
1.1
2.4
Ω
~~DD~~
~~— fo a~~
~~ee~~
~~po~~
~~a~~|**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
**Off Characteristics**
BVDSS
Drain to Source Breakdown Voltage
ID= 1 mA, VGS= 0 V
25
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 10 mA, referenced to 25 °C
21
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 20 V, VGS = 0 V
500
μA
IGSS
Gate to Source Leakage Current, Forward VGS= 20 V, VDS = 0 V
100
nA
**On Characteristics**
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 1 mA
1.2
1.7
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 10 mA, referenced to 25 °C
-5
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 22.5 A
2.5
3.15
mΩ
VGS= 4.5 V, ID= 18 A
3.6
4.7
VGS= 10 V, ID= 22.5 A, TJ = 125 °C
3.5
4.5
gFS
Forward Transconductance
VDS= 5 V, ID= 22.5 A
122
S
**Dynamic Characteristics**
Ciss
Input Capacitance
VDS= 13 V, VGS= 0 V,
f = 1 MHz
2031
2705
pF
Coss
Output Capacitance
596
795
pF
Crss
Reverse Transfer Capacitance
134
205
pF
Rg
Gate Resistance
1.1
2.4
Ω
~~DD~~
~~— fo a~~
~~ee~~
~~po~~
~~a~~|**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
**Off Characteristics**
BVDSS
Drain to Source Breakdown Voltage
ID= 1 mA, VGS= 0 V
25
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 10 mA, referenced to 25 °C
21
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 20 V, VGS = 0 V
500
μA
IGSS
Gate to Source Leakage Current, Forward VGS= 20 V, VDS = 0 V
100
nA
**On Characteristics**
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 1 mA
1.2
1.7
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 10 mA, referenced to 25 °C
-5
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 22.5 A
2.5
3.15
mΩ
VGS= 4.5 V, ID= 18 A
3.6
4.7
VGS= 10 V, ID= 22.5 A, TJ = 125 °C
3.5
4.5
gFS
Forward Transconductance
VDS= 5 V, ID= 22.5 A
122
S
**Dynamic Characteristics**
Ciss
Input Capacitance
VDS= 13 V, VGS= 0 V,
f = 1 MHz
2031
2705
pF
Coss
Output Capacitance
596
795
pF
Crss
Reverse Transfer Capacitance
134
205
pF
Rg
Gate Resistance
1.1
2.4
Ω
~~DD~~
~~— fo a~~
~~ee~~
~~po~~
~~a~~|**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
**Off Characteristics**
BVDSS
Drain to Source Breakdown Voltage
ID= 1 mA, VGS= 0 V
25
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= 10 mA, referenced to 25 °C
21
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= 20 V, VGS = 0 V
500
μA
IGSS
Gate to Source Leakage Current, Forward VGS= 20 V, VDS = 0 V
100
nA
**On Characteristics**
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= 1 mA
1.2
1.7
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= 10 mA, referenced to 25 °C
-5
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= 10 V, ID= 22.5 A
2.5
3.15
mΩ
VGS= 4.5 V, ID= 18 A
3.6
4.7
VGS= 10 V, ID= 22.5 A, TJ = 125 °C
3.5
4.5
gFS
Forward Transconductance
VDS= 5 V, ID= 22.5 A
122
S
**Dynamic Characteristics**
Ciss
Input Capacitance
VDS= 13 V, VGS= 0 V,
f = 1 MHz
2031
2705
pF
Coss
Output Capacitance
596
795
pF
Crss
Reverse Transfer Capacitance
134
205
pF
Rg
Gate Resistance
1.1
2.4
Ω
~~DD~~
~~— fo a~~
~~ee~~
~~po~~
~~a~~| |---|---|---|---| |**Switching Characteristics**|||| |td(on)
Turn-On DelayTime
VDD= 13 V, ID= 22.5 A,
VGS= 10 V, RGEN= 6Ω
11
22
tr
Rise Time
3.6
10
td(off)
Turn-Off DelayTime
26
41
tf
Fall Time
3
10
Qg
Total Gate Charge
VGS= 0 V to 10 V
VDD= 13 V
ID= 22.5 A
31
44
Qg
Total Gate Charge
VGS= 0 V to 4.5 V
14
20
Qgs
Gate to Source Gate Charge
6.5
Qgd
Gate to Drain “Miller” Charge
3.9
~~ee~~
~~ee~~
~~ee ee ee ~~
~~ee~~
~~ee ee ee ~~
~~ee~~
~~ee ee ee ~~
~~ee~~
~~ee ee ee ~~
~~es~~
~~ee ee ee ~~
~~ee~~
~~ee ee ee ~~
~~ee~~
~~ee~~
~~ee ee ee ~~
~~ee~~
~~ee ee ee~~|





|ns
ns
ns
ns
nC
nC
nC
nC
~~ee~~
~~ee~~
~~ee~~
~~ee~~
~~ee~~
~~ee~~
~~ee~~|| |**Drain-Source Diode Characteristics**|||| |VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 22.5 A(Note 2)
0.79
1.2
VGS = 0 V, IS = 2 A(Note 2)
0.47
0.8||V|| |trr
Reverse RecoveryTime
IF= 22.5 A, di/dt = 300 A/μs
24
39
Qrr
Reverse RecoveryCharge
19
34||ns
nC|| NOTES: 1. RθJA is determined with the device mounted on a 1in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. **==> picture [276 x 14] intentionally omitted <==** **----- Start of picture text -----**
53 °C/W when mounted on a 125 °C/W when mounted on
1 in [2 ] pad of 2 oz copper a minimum pad of 2 oz copper
**----- End of picture text -----**
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 84 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 13 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 20 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. www.fairchildsemi.com FDMC7572S Rev.C1 **2** **Typical Characteristics** TJ = 25 °C unless otherwise noted **==> picture [469 x 576] intentionally omitted <==** **----- Start of picture text -----**
120 8
VGS = 10 V
90 VGSVGS = = 3.5 V4.5 V VGS = 3 V 76 VGS = 2.5 V PULSE DURATION DUTY CYCLE = 0.5% MAX= 80 μ s
PULSE DURATION = 80 μ s 5
DUTY CYCLE = 0.5% MAX VGS = 3 V
60 4
3
VGS = 3.5 V
30 2 V GS = 4.5 V
VGS = 2.5 V
1
VGS = 10 V
0 0
0 1 2 3 4 5 0 30 60 90 120
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.5 12
1.4 ID = 22.5 A ID = 22.5 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s
VGS = 10 V 10
1.3
8
1.2
6
1.1
TJ = 125 [o] C
4
1.0
0.9 2
TJ = 25 [o] C
0.8 0
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On- Resistance Figure 4. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
120 200
PULSE DURATION = 80 μ s 100 VGS = 0 V
DUTY CYCLE = 0.5% MAX
90 10
VDS = 5 V TJ = 125 [o] C
1
60
TJ = 125 [o] C TJ = 25 [ o] C
0.1
30 TJ = 25 [o] C TJ = -55 [o] C
0.01
TJ = -55 [o] C
0 0.001
1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
NORMALIZED
DRAIN CURRENT (A)
,
ID
DRAIN TO SOURCE ON-RESISTANCE
)
Ω
m
(
DRAIN TO
NORMALIZED
rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
ID
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
www.fairchildsemi.com FDMC7572S Rev.C1 **3** **Typical Characteristics** TJ = 25 °C unless otherwise noted **==> picture [472 x 575] intentionally omitted <==** **----- Start of picture text -----**
10 3000
ID = 22.5 A
8 Ciss
VDD = 10 V VDD = 16 V 1000
6
VDD = 13 V Coss
4
2
100 f = 1 MHz
VGS = 0 V Crss
0 60
0 4 8 12 16 20 24 28 32 0.1 1 10 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain
to Source Voltage
30 120
TJ = 25 [ o] C
10 80 VGS = 10 V
TJ = 100 [o] C
VGS = 4.5 V
TJ = 125 [o] C 40
Limited by Package R θ JC = 2.4 oC/W
1 0
0.01 0.1 1 10 100 25 50 75 100 125 150
tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)
Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain
Switching Capability Current vs Case Temperature
200 2000
100 1000 VGS = 10 V SINGLE PULSE
100 us R θ JA = 125 [o] C/W
10 T A = 25 [o] C
1 ms 100
10 ms
THIS AREA IS
1 LIMITED BY rDS(on) 100 ms
SINGLE PULSE 10
1 s
0.1 TJ = MAX RATED
R θ JA = 125 [o] C/W 10 s
T A = 25 [o] C DC 1
0.01 0.5
0.01 0.1 1 10 100 10-4 10-3 10-2 10-1 1 10 100 1000
VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum
Operating Area Power Dissipation
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
DRAIN CURRENT (A)
,
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)
ID
, PEAK TRANSIENT POWER (W)
(PK)
P
**----- End of picture text -----**
www.fairchildsemi.com FDMC7572S Rev.C1 **4** **==> picture [470 x 199] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1 0.05
0.02 PDM
0.01
t1
0.01 t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
R θ JA = 125 [o] C/W PEAK TJ = PDM x Z θJA x R θJA + TA
0.001
10-4 10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
Z JA θ
IMPEDANCE,
NORMALIZED THERMAL
**----- End of picture text -----**
www.fairchildsemi.com FDMC7572S Rev.C1 **5** ## **Typical Characteristics** (continued) ## **SyncFET Schottky body diode Characteristics** Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 13 shows the reverses recovery characteristic of the FDMC7572S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. **==> picture [464 x 171] intentionally omitted <==** **----- Start of picture text -----**
25 10-2
20
10-3 TJ = 125 [o] C
15 TJ = 100 [o] C
di/dt = 300 A/ μ s
10 10-4
5
10-5
0 TJ = 25 [o] C
-5 10-6
0 50 100 150 200 0 5 10 15 20 25
TIME (ns) VDS, REVERSE VOLTAGE (V)
CURRENT (A)
, REVERSE LEAKAGE CURRENT (A)
IDSS
**----- End of picture text -----**
**Figure 13. FDMC7572S SyncFET body diode reverse recovery characteristic** **Figure 14. SyncFET body diode reverses leakage versus drain-source voltage** www.fairchildsemi.com FDMC7572S Rev.C1 **6** ## **Dimensional Outline and Pad Layout** **==> picture [393 x 515] intentionally omitted <==** **----- Start of picture text -----**
3.40
3.40
A 2.37 MIN
3.20
KEEP
PKG SYM OUT
CL B (0.45) 8 [C] L 5 AREA
8 5
2.15 MIN
1.70
PKG [C] L 3.40
3.20
0.70 MIN
(0.40)
(0.65)
1 4
1 4
0.65 0.42 MIN
SEE
DETAIL A 1.95
LAND PATTERN
RECOMMENDATION
0.10 C A B 1.95
0.37
0.65
0.27
0.50
1 4 0.30
PKG (0.20)
[C] L
2.09
(1.65) 1.89
(0.67)
8 5 NOTES: UNLESS OTHERWISE SPECIFIED
(0.39) A) PACKAGE STANDARD REFERENCE:
0.52 (2.27) JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
0.10 C
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
1.00 D) DIMENSIONING AND TOLERANCING PER
0.85 ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
0.08 C
C F) DRAWING FILE NAME: PQFN08BREV2
0.05
0.23 0.00
0.18 SEATING
PLANE
DETAIL A
SCALE: 2X
**----- End of picture text -----**
www.fairchildsemi.com FDMC7572S Rev.C1 **7** ## **TRADEMARKS** The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. |2Cool™
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