# Power MOSFET, P Channel, 12 V, 12 A, 0.0125 ohm, MicroFET, Surface Mount ![Product image](https://novapart.co/image/farnell:2822533RL/) **URL**: https://novapart.co/products/FDMA908PZ/power-mosfet-p-channel-12-v-a-00125-ohm-microfet **SKU**: FDMA908PZ **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.5750 **Stock**: 1000+ **Lead Time**: 2 days (indicative) ## Description Transistor Polarity:P Channel; Continuous Drain Current Id:-12A; Drain Source Voltage Vds:-12V; On Resistance Rds(on):0.01; Available until stocks are exhausted Alternative available ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 6Pins | | Channel Type | P Channel | | Product Range | PowerTrench | | Qualification | - | | Power Dissipation | 2.4W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 4.5V | | Transistor Case Style | MicroFET | | Drain Source Voltage Vds | 12V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 12A | | Drain Source On State Resistance | 0.0125ohm | | Gate Source Threshold Voltage Max | 600mV | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2822533RL/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [62 x 10] intentionally omitted <==** **----- Start of picture text -----**
February 2014
**----- End of picture text -----**
## ## **Single P-Channel PowerTrench[® ] MOSFET** **-12 V, -12 A, 12.5 m** Ω ## **Features** Max rDS(on) = 12.5 mΩ at VGS = -4.5 V, ID = -12 A Max rDS(on) = 18 mΩ at VGS = -2.5 V, ID = -10 A Max rDS(on) = 28 mΩ at VGS = -1.8 V, ID = -8 A Low Profile - 0.8 mm maximum in the new package MicroFET 2x2 mm HBM ESD protection level > 2.8 kV typical (Note 3) Free from halogenated compounds and antimony oxides RoHS Compliant ## **General Description** This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications. It features a MOSFET with low on-state resistance and zener diode protection against ESD. The MicroFET 2X2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. **==> picture [366 x 130] intentionally omitted <==** **----- Start of picture text -----**
Pin 1 D D G
Bottom Drain Contact
D
D
Drain Source
D D
G S
D D S
MicroFET 2X2 (Bottom View)
**----- End of picture text -----**
## **MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted |**Symbol**
**Parameter**|||**Ratings**||**Units**| |---|---|---|---|---|---| |VDS
Drain to Source Voltage|||-12||V| |VGS
Gate to Source Voltage|||±8||V| |ID
Drain Curre -Continuous TA= 25 °C(Note 1a)
-Pulsed|||-12
-40||A| |PD
Power Dissipation TA= 25 °C(Note 1a)
Power Dissipation TA= 25 °C(Note 1b)|||2.4
0.9||W| |TJ, TSTG
Operatingand Storage Junction Temperature Range|||-55 to +150||°C| |**Thermal Characteristics**|||||| |**Package Marking and Ordering Information**
RθJA
Thermal Resistance, Junction to Ambient(Note 1a)
52
°C/W
RθJA
Thermal Resistance, Junction to Ambient(Note 1b)
145
~~—ae~~|||||| |**Device Marking**
**Device**
**Package**
**Reel Size**
**Tape Width**
**Quantity**
908
FDMA908PZ
MicroFET 2X2
7 ”
12 mm
3000 units
~~ee~~|||||| ©2013 Fairchild Semiconductor Corporation **1** FDMA908PZ Rev.E3 www.fairchildsemi.com ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted |**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= -250μA, VGS= 0 V
-12
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= -250μA, referenced to 25 °C
-10
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= -9.6 V, VGS = 0 V
-1
μA
IGSS
Gate to Source Leakage Current
VGS= ±8 V, VDS = 0 V
±10
μA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= -250μA
-0.4
-0.6
-1
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= -250μA, referenced to 25 °C
2.8
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= -4.5 V, ID= -12 A
10
12.5
mΩ
VGS= -2.5 V, ID= -10 A
13
18
VGS= -1.8 V, ID= -8 A
18
28
VGS= -4.5 V, ID= -12 A,
TJ= 125 °C
13
16
gFS
Forward Transconductance
VDD= -5 V, ID= -12 A
63
S
Ciss
Input Capacitance
VDS= -6 V, VGS= 0 V,
f = 1 MHz
2638
3957
pF
Coss
Output Capacitance
649
974
pF
Crss
Reverse Transfer Capacitance
602
903
pF
~~re~~
~~SE~~
~~=————— eo~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= -250μA, VGS= 0 V
-12
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= -250μA, referenced to 25 °C
-10
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= -9.6 V, VGS = 0 V
-1
μA
IGSS
Gate to Source Leakage Current
VGS= ±8 V, VDS = 0 V
±10
μA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= -250μA
-0.4
-0.6
-1
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= -250μA, referenced to 25 °C
2.8
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= -4.5 V, ID= -12 A
10
12.5
mΩ
VGS= -2.5 V, ID= -10 A
13
18
VGS= -1.8 V, ID= -8 A
18
28
VGS= -4.5 V, ID= -12 A,
TJ= 125 °C
13
16
gFS
Forward Transconductance
VDD= -5 V, ID= -12 A
63
S
Ciss
Input Capacitance
VDS= -6 V, VGS= 0 V,
f = 1 MHz
2638
3957
pF
Coss
Output Capacitance
649
974
pF
Crss
Reverse Transfer Capacitance
602
903
pF
~~re~~
~~SE~~
~~=————— eo~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= -250μA, VGS= 0 V
-12
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= -250μA, referenced to 25 °C
-10
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= -9.6 V, VGS = 0 V
-1
μA
IGSS
Gate to Source Leakage Current
VGS= ±8 V, VDS = 0 V
±10
μA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= -250μA
-0.4
-0.6
-1
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= -250μA, referenced to 25 °C
2.8
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= -4.5 V, ID= -12 A
10
12.5
mΩ
VGS= -2.5 V, ID= -10 A
13
18
VGS= -1.8 V, ID= -8 A
18
28
VGS= -4.5 V, ID= -12 A,
TJ= 125 °C
13
16
gFS
Forward Transconductance
VDD= -5 V, ID= -12 A
63
S
Ciss
Input Capacitance
VDS= -6 V, VGS= 0 V,
f = 1 MHz
2638
3957
pF
Coss
Output Capacitance
649
974
pF
Crss
Reverse Transfer Capacitance
602
903
pF
~~re~~
~~SE~~
~~=————— eo~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= -250μA, VGS= 0 V
-12
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= -250μA, referenced to 25 °C
-10
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= -9.6 V, VGS = 0 V
-1
μA
IGSS
Gate to Source Leakage Current
VGS= ±8 V, VDS = 0 V
±10
μA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= -250μA
-0.4
-0.6
-1
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= -250μA, referenced to 25 °C
2.8
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= -4.5 V, ID= -12 A
10
12.5
mΩ
VGS= -2.5 V, ID= -10 A
13
18
VGS= -1.8 V, ID= -8 A
18
28
VGS= -4.5 V, ID= -12 A,
TJ= 125 °C
13
16
gFS
Forward Transconductance
VDD= -5 V, ID= -12 A
63
S
Ciss
Input Capacitance
VDS= -6 V, VGS= 0 V,
f = 1 MHz
2638
3957
pF
Coss
Output Capacitance
649
974
pF
Crss
Reverse Transfer Capacitance
602
903
pF
~~re~~
~~SE~~
~~=————— eo~~|**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Switching Characteristics**
**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Units**
BVDSS
Drain to Source Breakdown Voltage
ID= -250μA, VGS= 0 V
-12
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID= -250μA, referenced to 25 °C
-10
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS= -9.6 V, VGS = 0 V
-1
μA
IGSS
Gate to Source Leakage Current
VGS= ±8 V, VDS = 0 V
±10
μA
VGS(th)
Gate to Source Threshold Voltage
VGS= VDS, ID= -250μA
-0.4
-0.6
-1
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID= -250μA, referenced to 25 °C
2.8
mV/°C
rDS(on)
Static Drain to Source On Resistance
VGS= -4.5 V, ID= -12 A
10
12.5
mΩ
VGS= -2.5 V, ID= -10 A
13
18
VGS= -1.8 V, ID= -8 A
18
28
VGS= -4.5 V, ID= -12 A,
TJ= 125 °C
13
16
gFS
Forward Transconductance
VDD= -5 V, ID= -12 A
63
S
Ciss
Input Capacitance
VDS= -6 V, VGS= 0 V,
f = 1 MHz
2638
3957
pF
Coss
Output Capacitance
649
974
pF
Crss
Reverse Transfer Capacitance
602
903
pF
~~re~~
~~SE~~
~~=————— eo~~| |---|---|---|---|---| |td(on)
Turn-On DelayTime
tr
Rise Time
td(off)
Turn-Off DelayTime||VDD= -6 V, ID= -12 A,
VGS= -4.5 V, RGEN= 6Ω|11
21
12
23
131
223|ns
ns
ns| |tf
Fall Time|||71
121|ns| |Qg
Total Gate Charge||VGS= -4.5 V, VDD= -6 V,|24
34|nC| |Qgs
Gate to Source Charge||ID= -12 A|3.4|nC| |Qgd
Gate to Drain “Miller” Charge|||5.3|nC| |**Drain-Source Diode Characteristics**||||| |VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = -2 A(Note 2)
-0.6
-1.2
V
VGS = 0 V, IS = -12 A(Note 2)
-0.8
-1.2
V
trr
Reverse RecoveryTime
IF= -12 A, di/dt = 100 A/μs
26
42
ns
Qrr
Reverse RecoveryCharge
8.5
17
nC
~~—————————~~||||| |NOTES:||||| |1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined by||||| |the user's board design.||||| **==> picture [330 x 109] intentionally omitted <==** **----- Start of picture text -----**
a. 52 °C/W when mounted b. 145 °C/W when mounted on a
on a 1 in [2 ] pad of 2 oz copper. minimum pad of 2 oz copper.
fl
G DF DS SF SS
G DF DS SF SS
**----- End of picture text -----**
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. www.fairchildsemi.com **2** ©2013 Fairchild Semiconductor Corporation FDMA908PZ Rev.E3 **Typical Characteristics** TJ = 25 °C unless otherwise noted **==> picture [469 x 576] intentionally omitted <==** **----- Start of picture text -----**
40 3
VGS = -4.5 V
VGS = -3 V VGS = -1.5 V
30
VGS = -2.5 V 2
VGS = -1.8 V VGS = -1.8 V
20 VGS = -2.5 V VGS = -3 V
1
VGS = -1.5 V
10 VGS = -4.5 V
PULSE DURATION = 80 μ s
PULSE DURATION = 80 μ s DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
0 0
0.0 0.5 1.0 1.5 2.0 0 10 20 30 40
-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics Figure 2. Normalized On- Resistance
vs Drain Current and Gate Voltage
60
1.4
ID = -12A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s
1.3 VGS = -4.5V
ID = -12 A
1.2 40
1.1
1.0 TJ = 125 [o] C
20
0.9
0.8 TJ = 25 [o] C
0
0.7 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
-75 -50 -25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On- Resistance Figure 4. On-Resistance vs Gate to
vs Junction Temperature Source Voltage
40 100
PULSE DURATION = 80 μ s VGS = 0 V
DUTY CYCLE = 0.5% MAX
10
30
VDS = -5 V TJ = 150 [o] C 1 T J = 150 [o] C
20
TJ = 25 [o] C 0.1 TJ = 25 [ o] C
10
TJ = -55 [o] C 0.01 TJ = -55 [o] C
0 0.001
0.0 0.5 1.0 1.5 2.0 0.0 0.4 0.8 1.2
-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
NORMALIZED
, DRAIN CURRENT (A)
D
-I
DRAIN TO SOURCE ON-RESISTANCE
) Ω
(m
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON-RESISTANCE
DRAIN TO SOURCE ON-RESISTANCE
, DRAIN CURRENT (A)
D
-I , REVERSE DRAIN CURRENT (A)
S
-I
**----- End of picture text -----**
www.fairchildsemi.com **3** ©2013 Fairchild Semiconductor Corporation FDMA908PZ Rev.E3 ## **Typical Characteristics** TJ = 25 °C unless otherwise noted **==> picture [468 x 385] intentionally omitted <==** **----- Start of picture text -----**
4.5 5000
ID = -12A Ciss
VDD = -4V
3.0
VDD = -6V
Coss
1000
VDD = -8V
1.5
f = 1 MHz C rss
VGS = 0 V
0.0 300
0.1 1 10 20
0 5 10 15 20 25
Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain
to Source Voltage
10-3 60
VDS = 0 V
10-4
10
10-5 TJ = 125 [ o] C 1 ms
10-6 10 ms
1
THIS AREA IS
10-7 LIMITED BY rDS(on) 100 ms
10-8 TJ = 25 [o] C 0.1 SINGLE PULSETJ = MAX RATED 1 s 10 s
DC
10-9 R θ JA = 145 [ o] C/W CURVE BENT TO
TA = 25 [o] C MEASURED DATA
10-10 0.01
0 5 10 15 0.01 0.1 1 10 50
-VGS, GATE TO SOURCE VOLTAGE (V) -VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Gate Leakage Current Figure 10. Gate Leakage Current
vs Gate to Source Voltage vs Gate to Source Voltage
CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
-V
, DRAIN CURRENT (A)
D
-I
GATE LEAKAGE CURRENT (A)
,
g
-I
**----- End of picture text -----**
**==> picture [470 x 184] intentionally omitted <==** **----- Start of picture text -----**
100
SINGLE PULSE
R θ JA = 145 [o] C/W
10 TA = 25 [o] C
1
0.1
10-3 10-2 10-1 1 10 100 1000
t, PULSE WIDTH (sec)
Figure 11. Single Pulse Maximum Power Dissipation
, PEAK TRANSIENT POWER (W)
(PK)
P
**----- End of picture text -----**
www.fairchildsemi.com **4** ©2013 Fairchild Semiconductor Corporation FDMA908PZ Rev.E3 **==> picture [457 x 194] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05 PDM
0.02
0.01
0.1
t1
SINGLE PULSE t 2
NOTES:
R θ JA = 145 [o] C/W DUTY FACTOR: D = t1/t2
(Note 1b) PEAK TJ = PDM x Z θJA x R θJA + TA
0.01
10-3 10-2 10-1 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
Z JA θ
IMPEDANCE,
NORMALIZED THERMAL
**----- End of picture text -----**
www.fairchildsemi.com **5** ©2013 Fairchild Semiconductor Corporation FDMA908PZ Rev.E3 **==> picture [502 x 533] intentionally omitted <==** **----- Start of picture text -----**
2.05 A
0.05 C (0.20)
B (0.45)
2X
1.00
eo _—_ a 3
6 5 4
be
2.05
1.05 0.66
0.05 C 0.475(6X)
PIN #1 LOCATION Z. 2X je t 1 2 3
TOP VIEW
0.65 Pout
0.8 +0.05
0.10 C
0.20+0.05 Pin # Function
i S] 0.08 C L 1 Drain
2 Drain
C 3 Gate
s a PLANESEATING at SIDE VIEW 4 Source
5 Drain
6 Drain
7 Drain
8 Source
0.025.025 too =
p.902010 4 2 oo t
(0.200) 4X NOTES:
(0.15)
PIN #1 IDENT (0.50) A. PACKAGE DOES NOT CONFORM TO
E 1 le 2 3 (0.30) ANY JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
0.265+0.065 MY aim 0.61 +0.05
(6X) ASME Y14.5M, 2009.
(0.50) 7 8 D. LAND PATTERN RECOMMENDATION IS
r 5 +Om- Pt1 .0020.05 2.0820 .05 EXISTING INDUSTRY LAND PATTERN.
6 5 4
0.65 | = 0.30+0.05(6X)
0.10 C A B
1.30
0.05 C
a | @
**----- End of picture text -----**
**==> picture [166 x 157] intentionally omitted <==** **----- Start of picture text -----**
(0.20)
(0.45)
1.00
3
6 5 4
be
2.30
1.05 0.66
1.35
0.475(6X)
0.65 je Pout 1 2 3 0.40 (6X)
**----- End of picture text -----**
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