# Power MOSFET, N Channel, 40 V, 10 A, 0.014 ohm, WDFN, Surface Mount ![Product image](https://novapart.co/image/farnell:2992326/) **URL**: https://novapart.co/products/FDMA8051L/power-mosfet-n-channel-40-v-10-a-0014-ohm-wdfn **SKU**: FDMA8051L **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.2740 **Stock**: 1000+ **Lead Time**: 141 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:10A; Drain Source Voltage Vds:40V; On Resistance Rds(on):0.011ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.6V; ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | No SVHC (25-Jun-2025) | | No. Of Pins | 6Pins | | Channel Type | N Channel | | Product Range | PowerTrench | | Qualification | - | | Power Dissipation | 2.4W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | WDFN | | Drain Source Voltage Vds | 40V | | Operating Temperature Max | 150°C | | Continuous Drain Current Id | 10A | | Drain Source On State Resistance | 0.014ohm | | Gate Source Threshold Voltage Max | 1.6V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2992326/) ## FDMA8051L ## MOSFET, Single N-Channel, POWERTRENCH ## **40 V, 10 A, 14 m** ## **General Description** **==> picture [95 x 106] intentionally omitted <==** **----- Start of picture text -----**
www.onsemi.com
Bottom Drain Contact
D D
D D
G S
**----- End of picture text -----**
This device has been designed to provide maximum efficiency and thermal performance for synchronous buck converters. The low rDS(on) and gate charge provide excellent switching performance. ## **ELECTRICAL CONNECTION** ## **Features** - Max rDS(on) = 14 m at VGS = 10 V, ID = 10 A - Max rDS(on) = 18 m at VGS = 4.5 V, ID = 8.5 A - Low Profile − 0.8 mm maximum in the new package MicroFET 2 x 2 mm - Free from halogenated compounds and antimony oxides • RoHS Compliant **Single N-Channel MOSFET Application Pin 1 D D G** • DC−DC Buck Converters **Drain Source MOSFET MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) **Symbol Parameter Ratings Unit D D S** VDS Drain to Source Voltage 40 V VGS Gate to Source Voltage ± 20 V **MicroFET 2x2** ID Drain Current − Continuous TA = 25 ° C 10 A **(WDFN6 2x2, 0.65P)** (Note 1a) **CASE 511DB** − Pulsed (Note 3) 80 **MARKING DIAGRAM** PD Power dissipation TA = 25 ° C (Note 1a) 2.4 W Power dissipation TA = 25 ° C (Note 1b) 0.9 &Z&2&K TJ, Operating and Storage Junction Temperature −55 to ° C 051 TSTG Range +150 ~~=~~ Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be = assumed, damage may occur and reliability may be affected. &Z = Assembly Plant Code &2 = Numeric Date Code **THERMAL CHARACTERISTICS** &K = Lot Code **Symbol Parameter Ratings Unit** 051 = Specific Device Code |**Symbol**|**Parameter**|**Ratings**|**Unit**| |---|---|---|---| |R JA|Thermal Resistance, Junction to Ambient
(Note 1a)|52|°C/W| |R JA|Thermal Resistance, Junction to Ambient
(Note 1b)|145|| ## **ORDERING INFORMATION** See detailed ordering and shipping information on page 1 of this data sheet. |**PACKAGE MARKING AND ORDERING INFORMATION**| |---| |**Device Marking**
**Device**
**Package**
**Shipping**†
051
FDMA8051L
MicroFET 2x2
3000 Units/
Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
~~a~~| Publication Order Number: **FDMA8051L/D** **1** © Semiconductor Components Industries, LLC, 2013 **August, 2018 − Rev. 3** **FDMA8051L** **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) |**ELECTRIC**|**ELECTRIC**|**AL CHARACTERISTICS**(TJ= 25°C unles|s otherwise noted)||||| |---|---|---|---|---|---|---|---| |**Symbol**||**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||||| ||BVDSS|Drain to Source Breakdown Voltage|ID= 250�A, VGS= 0 V|40|||V| ||�BVDSS
�TJ|Breakdown Voltage Temperature
Coefficient|ID= 250�A, referenced to 25°C||22||mV/°C| ||IDSS|Zero Gate Voltage Drain Current|VDS= 32 V, VGS= 0 V|||1|�A| ||IGSS|Gate−to−Source Leakage Current|VGS=±20 V, VDS= 0 V|||100|nA| |**ON CHARACTERISTICS**|||||||| ||VGS(th)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250�A|1.0|1.6|3.0|V| ||�VGS(th)
�TJ|Gate to Source Threshold Voltage
Temperature Coefficient|ID= 250�A, referenced to 25°C||−5||mV/°C| ||rDS(on)|Static Drain to Source On Resistance|VGS= 10 V, ID= 10 A||11|14|m�| ||||VGS= 4.5 V, ID= 8.5 A||14|18|| ||||VGS= 10 V, ID= 10 A, TJ= 125°C||15|19|| ||gFS|Forward Transconductance|VDD= 5 V, ID= 10 A||35||S| |**DYNAMIC CHARACTERISTICS**|||||||| |Ciss||Input Capacitance|VDS= 20 V, VGS= 0 V, f = 1MHz||901|1260|pF| |Coss||Output Capacitance|||251|350|| |Crss||Reverse Transfer Capacitance|||16|25|| |Rg||Gate Resistance||0.1|0.6|1.8|�| |**SWITCHING CHARACTERISTICS**|||||||| |td(on)||Turn�On Delay Time|VDD= 20 V, ID= 10 A,
VGS= 10 V, RGEN= 6�||6.4|13|ns| |tr||Rise Time|||1.8|10|| |tD(off)||Turn�Off Delay Time|||17|31|| |tf||Fall Time|||1.8|10|| |Qg||Total Gate Charge|VGS= 0V to 10 V
VGS= 0V to 4.5 V
VDD= 20 V,
iD= 10 A||14|20|nC| |Qg||Total Gate Charge|||6.4|9.0|| |Qgs||Total Gate Charge|||2.4|3.7|| |Qgd||Gate to Source Charge|||1.8|2.5|| |**DRAIN−SOURCE DIODE CHARACTERISTICS**|||||||| |VSD||Source to Drain Diode Forward Voltage|VGS= 0 V, IS= 2 A (Note 2)||0.7|1.2|V| ||||VGS= 0 V, IS= 10 A (Note 2)||0.8|1.2|| |trr||Reverse Recovery Time|IF= 10 A, di/dt = 100 A/�s||23|37|ns| |Qrr||Reverse Recovery Charge|||6.7|14|nC| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. **www.onsemi.com** **2** **FDMA8051L** ## NOTES: 1. R JA is determined with the device mounted on a 1 in[2] pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR−4 material. R JC is guaranteed by design while R JA is determined by the user’s board design. **==> picture [416 x 110] intentionally omitted <==** **----- Start of picture text -----**
a) 52 ° C/W when mounted on b) 145 ° C/W when mounted on
a 1 in [2] pad of 2 oz copper. a minimum pad of 2 oz copper.
G DF DS SF SS
G DF DS SF SS
**----- End of picture text -----**
2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%. 3. Pulsed ID limited by junction temperature, td<= 100 S, please refer to SOA curve for more details. ## **TYPICAL CHARACTERISTICS** TJ = 25 ° C unless otherwise noted **==> picture [208 x 152] intentionally omitted <==** **----- Start of picture text -----**
5
VGS = 3 VGS = 3 V = 3 V
4 V GS = 3.5 V
3 peop de
VGS = 4 VGS = 4 V = 4 V
2 a
1
PULSE DURATION = 80 sDUTY CYCLE = 0.5% MAX VGS = 10 VGS = 10 V = 10 V
—————a DUTY CYCLE = 0.5% MAX VGS = 4.5 VGS = 4.5 V = 4.5 V
0
0 20 40 60 80
IDD , DRAIN CURRENT (A)DRAIN CURRENT (A)
NORMALIZED
DRAIN TO SOURCE ON−RESISTANCE
**----- End of picture text -----**
**==> picture [444 x 153] intentionally omitted <==** **----- Start of picture text -----**
80 5
VGS = 10 V
VGS = 3 VGS = 3 V = 3 V
VGS = 4.5 V 4 V GS = 3.5 V
60
Dane VGS = 4 V 3 peop de
VGS = 4 VGS = 4 V = 4 V
40
a 2 a
VGS = 3.5 V
20
1
0 apT VGS = 3 V PULSE DURATIONV = 80 sDUTY CYCLE = 0.5% MAX 0 —————a PULSE DURATION = 80 sDUTY CYCLE = 0.5% MAX VGS = 4.5 VGS = 4.5 V = 4.5 V VGS = 10 VGS = 10 V = 10 V
0 1 2 3 4 0 20 40 60
VDS , DRAIN TO SOURCE VOLTAGE (V) IDD , DRAIN CURRENT (A)DRAIN CURRENT (A)
NORMALIZED
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON−RESISTANCE
**----- End of picture text -----**
**Figure 1. On Region Characteristics** **Figure 2. Normalized On−Resistance vs. Drain Current and Gate Voltage** **==> picture [448 x 153] intentionally omitted <==** **----- Start of picture text -----**
1.6 40
ID = 10 A PULSE DURATION = 80 s
VGS = 10 V DUTY CYCLE = 0.5% MAX
1.4 TT eT 30 ID = 10 A
1.2
Saanneeae 20 me TJ = 125 ° C _
1.0
0.8 Sane? anne 10 Se TJ = 25 ° C
0.6 TELECer TC 0 ===_
−75 −50 −25 0 25 50 75 100 125 150 2 4 6 8 10
TJ , JUNCTION TEMPERATURE ( [o] C) VGS , GATE TO SOURCE VOLTAGE (V)
)
m
(
DRAIN TO
NORMALIZED rDS(on),
SOURCE ON−RESISTANCE
DRAIN TO SOURCE ON−RESISTANCE
**----- End of picture text -----**
**Figure 3. Normalized On Resistance vs. Junction Temperature** **Figure 4. On−Resistance vs. Gate to Source Voltage** **www.onsemi.com** **3** **FDMA8051L** ## **TYPICAL CHARACTERISTICS** TJ = 25 ° C unless otherwise noted (continued) **==> picture [202 x 152] intentionally omitted <==** **----- Start of picture text -----**
80
PULSE DURATIONV = 80 � s
DUTY CYCLE = 0.5% MAX
60 VDS = 5 V
40
TJ = 150 ° C
20 TJ = 25 ° C
TJ = −55 ° C
0
1 2 3 4 5
VGS, GATE TO SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**==> picture [207 x 148] intentionally omitted <==** **----- Start of picture text -----**
80 VGS = 0 V
10
1 TJ = 150 ° C
0.1 TJ = 25 ° C
0.01
TJ = −55 ° C
0.001
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
, REVERSE DRAIN CURRENT (A)
IS
**----- End of picture text -----**
**Figure 5. Transfer Characteristics** **Figure 6. Source to Drain Diode Forward Voltage vs. Source Current** **==> picture [203 x 153] intentionally omitted <==** **----- Start of picture text -----**
10
ID = 10 A
8
VDD = 15 V
6
VDD = 20 V
4
VDD = 25 V
2
0
0 3 6 9 12 15
Qg, GATE CHARGE (nC)
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**Figure 7. Gate Charge Characteristics** **==> picture [202 x 152] intentionally omitted <==** **----- Start of picture text -----**
2000
1000 C iss
100 Coss
f = 1 Mhz
10 VGS = 0 V Crss
50.1 1 10 40
VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
**----- End of picture text -----**
**Figure 8. Capacitance vs. Drain to Source Voltage** **==> picture [202 x 151] intentionally omitted <==** **----- Start of picture text -----**
300
100
10
100 � s
1 1 ms
10 ms
THIS AREA IS 100 ms
0.1 LIMITED BY rDS(on) 1 s
10 s
SINGLE PULSE DC
0.01 TJ = MAX RATED
R � JA = 145 ° C/W CURVE BENT TO
T A = 25 ° C MEASURED DATA
0.001
0.01 0.1 1 10 100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
**----- End of picture text -----**
**==> picture [211 x 150] intentionally omitted <==** **----- Start of picture text -----**
1000
SINGLE PULSE
R � JA = 145 ° C/W
TA = 25 ° C
100
10
1
0.1
10 [−4] 10 [−3] 10 [−2] 10 [−1] 1 10 100 1000
t, PULSE WIDTH (sec)
PEAK TRANSIENT POWER (W)
(PK),
P
**----- End of picture text -----**
**Figure 9. Forward Bias Safe Operating Area** **Figure 10. Single Pulse Maximum Power Dissipation** **www.onsemi.com** **4** **FDMA8051L** ## **TYPICAL CHARACTERISTICS** TJ = 25 ° C unless otherwise noted (continued) **==> picture [443 x 163] intentionally omitted <==** **----- Start of picture text -----**
2
DUTY CYCLE−DESCENDING ORDER
1
D = 0.5
0.2 P DM
0.1 0.1
0.05
0.02 t1
0.01
t2
0.01 NOTES:
SINGLE PULSE ZR � � JAJA (t) = 145= r(t) ° C/W × R � JA
PEAK TJ = PDM × Z � JA (t) + TA
Duty cycle, D = t1/t2
0.001
10 [−4] 10 [−3] 10 [−2] 10 [−1] 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE TRANSIENT
**----- End of picture text -----**
**Figure 11. Single Pulse Junction−to−Ambient Transient Thermal Response Curve** POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. **www.onsemi.com** **5** MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **WDFN6 2x2, 0.65P** CASE 511DB ISSUE O DATE 31 AUG 2016 **DOCUMENT NUMBER: 98AON13617G** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed **STATUS: ON SEMICONDUCTOR STANDARD** versions are uncontrolled except when stamped “CONTROLLED COPY” in red. ~~**NEW STANDARD:**~~ © Semiconductor Components Industries, LLC, 2002 **http://onsemi.com** Case Outline Number: **October, 2002 − Rev. 0DESCRIPTION: WDFN6 2X2, 0.65P 1 PAGE 1 OF 2XXX** |~~eT ©~~|~~eT ©~~|**DOCUMENT NUMBER:**
**98AON13617G**
**PAGE 2 OF 2**
~~——~~| |---|---|---| |**ISSUE**|**REVISION**|**DATE**| |O|RELEASED FOR PRODUCTION FROM FAIRCHILD MLP06P TO ON|31 AUG 2016| ||SEMICONDUCTOR. REQ. BY B. MARQUIS.|| **ON Semiconductor** and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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