# Power MOSFET, P Channel, 20 V, 7.8 A, 0.027 ohm, µFET, Surface Mount

![Product image](https://novapart.co/image/farnell:2323178/)

**URL**: https://novapart.co/products/FDMA510PZ/power-mosfet-p-channel-20-v-78-a-0027-ohm-fet
**SKU**: FDMA510PZ
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2790
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 6Pins |
| Channel Type | P Channel |
| Power Dissipation | 2.4W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | P Channel |
| Power Dissipation Pd | 2.4W |
| Rds(On) Test Voltage | 4.5V |
| On Resistance Rds(On) | 0.027ohm |
| Transistor Case Style | µFET |
| Drain Source Voltage Vds | 20V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 7.8A |
| Drain Source On State Resistance | 0.027ohm |
| Gate Source Threshold Voltage Max | 700mV |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2323178/)

## **Is Now Part of** 

**To learn more about ON Semiconductor, please visit our website at www.onsemi.com** 

ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

**June 2014** 

## **FDMA510PZ** 

**Single P-Channel PowerTrench[®] MOSFET –20V, –7.8A, 30m** 

## **Features** 

Max rDS(on) = 30m at VGS = –4.5V, ID = –7.8A Max rDS(on) = 37m at VGS = –2.5V, ID = –6.6A 

Max rDS(on) = 50m at VGS = –1.8V, ID = –5.5A Max rDS(on) = 90m at VGS = –1.5V, ID = –2.0A 

Low profile - 0.8mm maximum - in the new package MicroFET 2X2 mm 

## **General Description** 

This device is designed specifically for battery charge or load switching in cellular handset and other ultraportable applications. It features a MOSFET with low on-state resistance. The MicroFET 2X2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. 

HBM ESD protection level > 3KV typical (Note 3) 

Free from halogenated compounds and antimony oxides 

RoHS Compliant 

**==> picture [382 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin 1 D D G<br>Bottom Drain Contact<br>D 1 6 D<br>Drain Source<br>D 2 5 D<br>G 3 4 S<br>D D S<br>MicroFET 2X2 (Bottom View)<br>**----- End of picture text -----**<br>


## **MOSFET Maximum Ratings** TA = 25°C unless otherwise noted 

|**Symbol**|**Parameter**|||**Ratings**|**Ratings**||**Units**|
|---|---|---|---|---|---|---|---|
|VDS|Drain to Source Voltage||||–20||V|
|VGS|Gate to Source Voltage||||±8||V|
|ID|Drain Current     -Continuous                                                                       (Note 1a)<br>-Pulsed|Drain Current     -Continuous                                                                       (Note 1a)|||–7.8<br>–24||A|
|PD|Power Dissipation                                                                                         (Note 1a)<br>Power Dissipation                                                                                         (Note 1b)|Power Dissipation                                                                                         (Note 1a)<br>Power Dissipation                                                                                         (Note 1b)|||2.4<br>0.9||W|
|TJ, TSTG|Operating and Storage Junction Temperature Range|||–55 to +150|–55 to +150||°C|
|**Thermal Characteristics**||||||||
|R JA|Thermal Resistance, Junction to Ambient                                                 (Note 1a)|Thermal Resistance, Junction to Ambient                                                 (Note 1a)|||52||°C/W|
|R JA|Thermal Resistance, Junction to Ambient                                                 (Note 1b)|Thermal Resistance, Junction to Ambient                                                 (Note 1b)|||145|||
|**Package Marking and Ordering Information**||||||||
|**Device Marking**<br>**Device**<br>**Package**<br>**Reel Size**<br>**Tape Width**<br>**Quantity**<br>510<br>FDMA510PZ<br>MicroFET 2X2<br>7’’<br>8mm<br>3000units<br>he<br>————||||||||



©2009 Fairchild Semiconductor Corporation **1** FDMA510PZ Rev.B3 

www.fairchildsemi.com 

**Electrical Characteristics** TJ = 25°C unless otherwise noted 

|**Electrical Characteristics**TJ = 25°C unless otherwise notedJ = 25°C unless otherwise noted= 25°C unless otherwise noted|**Electrical Characteristics**TJ = 25°C unless otherwise notedJ = 25°C unless otherwise noted= 25°C unless otherwise noted|
|---|---|
|**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>**Off Characteristics**<br>BVDSS<br>Drain to Source Breakdown Voltage<br>ID= –250 A, VGS= 0V<br>–20<br>V<br>BVDSS<br>TJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= –250 A, referenced to 25°C<br>–13<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= –16V, VGS= 0V<br>–1<br>A<br>IGSS<br>Gate to Source Leakage Current<br>VGS= ±8V, VDS= 0V<br>±10<br>A<br>**On Characteristics**<br>VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS, ID= –250 A<br>–0.4<br>–0.7<br>–1.5<br>V<br>VGS(th)<br>TJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= –250 A, referenced to 25°C<br>3<br>mV/°C<br>rDS(on)<br>Static Drain to Source On Resistance<br>VGS= –4.5V, ID= –7.8A<br>27<br>30<br>m<br>VGS= –2.5V, ID= –6.6A<br>34<br>37<br>VGS= –1.8V, ID= –5.5A<br>46<br>50<br>VGS= –1.5V, ID= –2.0A<br>60<br>90<br>VGS= –4.5V, ID= –7.8A ,TJ= 125°C<br>36<br>40<br>gFS<br>Forward Transconductance<br>VDD= –5V, ID= –7.8A<br>26<br>S<br>**Dynamic Characteristics**<br>Ciss<br>Input Capacitance<br>VDS= –10V, VGS= 0V,<br>f = 1MHz<br>1110<br>1480<br>pF<br>Coss<br>Output Capacitance<br>205<br>275<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>185<br>280<br>pF<br>**Switching Characteristics**<br>a<br>eG<br>~~i~~<br>ee<br>ee<br>ee<br>~~El~~<br>ee<br>ee<br>ee<br>ee<br>ee<br>aa<br>GF<br>DO||
|td(on)<br>Turn-On Delay Time<br>VDD= –10V, ID= –7.8A<br>VGS= –4.5V, RGEN= 6<br>7<br>14<br>ns<br>tr<br>Rise Time<br>9<br>18<br>ns<br>td(off)<br>Turn-Off Delay Time<br>125<br>200<br>ns<br>tf<br>Fall Time<br>64<br>103<br>ns<br>Qg<br>Total Gate Charge<br>VDD= –5V, ID= –7.8A<br>VGS= –4.5V<br>19<br>27<br>nC<br>Qgs<br>Gate to Source Charge<br>2.1<br>nC<br>Qgd<br>Gate to Drain “Miller” Charge<br>4.2<br>nC<br>ee<br>ee ee ee ee<br>ee<br>o<br>ee ee ee ee<br>ee<br>ee ee ee ee<br>ee<br>ee ee ee ee<br>ee<br>ee ee ee ee<br>ee<br>ee ee ee ee<br>ee<br>ee ee ee ee||
|**Drain-Source Diode Characteristics**||
|IS<br>Maximum Continuous Drain-Source Diode Forward Current<br>–2<br>A<br>a||
|VSD<br>Source to Drain Diode  Forward Voltage<br>VGS= 0V, IS= –2A<br>–0.8<br>–1.2<br>V<br>trr<br>Reverse Recovery Time<br>IF= –7.8A, di/dt = 100A/ s<br>66<br>106<br>ns<br>Qrr<br>Reverse Recovery Charge<br>44<br>71<br>nC<br>aGO<br>Seeee<br>eeeee<br>a<br>a a||



## **Notes:** 

1. R JA is determined with the device mounted on a 1in[2] the user's board design. 

JC is guaranteed by design while R CA is determined by 

a. 52°C/W when mounted  on a 1 in[2] pad of  2 oz  copper. 

b. 145°C/W when mounted on  a minimum pad of 2 oz copper. 

2. Pulse Test: Pulse Width < 300 mm s, Duty cycle < 2.0%. 

3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 

www.fairchildsemi.com 

**2** 

©2009 Fairchild Semiconductor Corporation FDMA510PZ Rev.B3 

## **Typical Characteristics** TJ = 25°C unless otherwise noted 

**==> picture [469 x 576] intentionally omitted <==**

**----- Start of picture text -----**<br>
24<br>2.5<br>20 VGS = -4.5V VGS = -1.8V VGS = -1.5V VGS = -1.8V<br>VGS = -2.5V 2.0<br>16<br>VGS = -2V<br>12 VGS = -2V<br>1.5<br>VGS = -1.5V VGS = -2.5V<br>8<br>1.0<br>4 PULSE DURATION = 80DUTY CYCLE = 0.5%MAX � s PULSE DURATION = 80 � s VGS = -4.5V<br>DUTY CYCLE = 0.5%MAX<br>0<br>0.5<br>0 1 2 3 4<br>0 4 8 12 16 20 24<br>-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT(A)<br>Figure 1.  On-Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 200<br> ID = -7.8A PULSE DURATION = 80 � s<br>1.4 VGS = -4.5V DUTY CYCLE = 0.5%MAX<br>150<br>ID = -7.8A<br>1.2<br>100<br>1.0<br>TJ = 125 [o] C<br>50<br>0.8<br>TJ = 25 [o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On- Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>24 10<br>20 PULSE DURATION = 80DUTY CYCLE = 0.5%MAX � s VGS = 0V<br>VDD = -5V 1<br>16<br>12 0.1 TJ = 150 [o] C<br>8 TJ = 25 [o] C<br>TJ = -55 [o] C 0.01<br>4 TJ = 25 [o] C TJ = -55 [o] C<br>TJ = 150 [o] C<br>0 1E-3<br>0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>DRAIN CURRENT (A)<br>D,<br>-I<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>�<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>D<br>-I , REVERSE DRAIN CURRENT (A)<br>S<br>-I<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

**3** 

©2009 Fairchild Semiconductor Corporation FDMA510PZ Rev.B3 

## **Typical Characteristics** TJ = 25°C unless otherwise noted 

**==> picture [469 x 559] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.5 3000<br>ID = -7.8A<br>Ciss<br>3.0 1000<br>VDD = -3V<br>VDD = -5V<br>Coss<br>VDD = -7V<br>1.5<br>f = 1MHz<br>VGS = 0V Crss<br>0.0 100<br>0 5 10 15 20 0.1 1 10 20<br>Qg, GATE CHARGE(nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>10-1 30<br>10-2 VDS = 0V 10 100us<br>10-3<br>1ms<br>10-4<br>1<br>10-5 TJ = 125 [o] C 10ms<br>THIS AREA IS<br>10-6 LIMITED BY rDS(on) 100ms<br>10-7 0.1 SINGLE PULSE 1s<br>TJ = MAX RATED 10s<br>10-8 TJ = 25 [o] C R � JA = 145 [o] C/W DC<br>10-9 TA = 25 [o] C<br>0.01<br>10-10 0.1 1 10 60<br>0 3 6 9 12 15<br>-VDS, DRAIN to SOURCE VOLTAGE (V)<br>-VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 9.  Gate Leakage Current vs Gate to           Figure 10.  Forward Bias Safe<br>Source Voltage Operating Area<br>400<br>SINGLE PULSE<br>100 R � JA = 145 [o] C/W<br>TA = 25 [o] C<br>VGS = -4.5V<br>10<br>1<br>0.5<br>10-4 10-3 10-2 10-1 100 101 102 103<br>t, PULSE WIDTH (s)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE(V)<br>GS<br>-V<br>A)( , DRAIN CURRENT (A)<br>D<br> -I<br>GATE LEAKAGE CURRENT<br>g,<br>-I<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


**Figure 11.  Single  Pulse Maximum Power  Dissipation** 

www.fairchildsemi.com 

**4** 

©2009 Fairchild Semiconductor Corporation FDMA510PZ Rev.B3 

**==> picture [470 x 208] intentionally omitted <==**

**----- Start of picture text -----**<br>
Typical Characteristics  TJ = 25°C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05<br>0.1       0.02 PDM<br>      0.01<br>t1<br>0.01 t2<br>NOTES:<br>SINGLE PULSE DUTY FACTOR: D = t1/t2<br>R � JA = 145 [o] C/W PEAK TJ = PDM x Z �JA  x R �JA  + TA<br>1E-3<br>10-4 10-3 10-2 10-1 100 101 102 103<br>t, RECTANGULAR PULSE DURATION (s)<br>Figure 12.  Transient Thermal Response Curve<br>ZJA �<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**==> picture [138 x 14] intentionally omitted <==**

**----- Start of picture text -----**<br>
©2009 Fairchild Semiconductor Corporation<br>FDMA510PZ Rev.B3<br>**----- End of picture text -----**<br>


**==> picture [253 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
5 www.fairchildsemi.com<br>**----- End of picture text -----**<br>


## **Dimensional Outline and Pad Layout** 

_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ 

_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLDEB-C06_ 

www.fairchildsemi.com 

**6** 

©2009 Fairchild Semiconductor Corporation FDMA510PZ Rev.B3 

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## **Definition of Terms** 

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Rev. I68 

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