# Power MOSFET, N Channel, 30 V, 58 A, 9000 µohm, TO-252AA, Surface Mount ![Product image](https://novapart.co/image/farnell:2453402RL/) **URL**: https://novapart.co/products/FDD8880/power-mosfet-n-channel-30-v-58-a-9000-ohm-to-252aa **SKU**: FDD8880 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4310 **Stock**: 1000+ **Lead Time**: 2 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:58A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.007ohm; Available until stocks are exhausted Alternative available ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 55W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252AA | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 58A | | Drain Source On State Resistance | 9000µohm | | Gate Source Threshold Voltage Max | 2.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2453402RL/) **DATA SHEET www.onsemi.com** ## MOSFET – N-Channel, POWERTRENCH[�] ## 30 V, 58 A, 9 m **�** |**VDSS MAX**|**rDS(ON) MAX**|**ID MAX**| |---|---|---| |30 V|9 m�@ 10 V|58 A| ||12 m�@ 4.5 V|| ## FDD8880, FDD8880-G ## **General Description** This N−Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. **==> picture [61 x 57] intentionally omitted <==** **----- Start of picture text -----**
D
G
S
DPAK3
(TO−252 3 LD)
CASE 369AS
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## **Features** - rDS(ON) = 9 m�, VGS = 10 V, ID = 35 A - rDS(ON) = 12 m�, VGS = 4.5 V, ID = 35 A - High Performance Trench Technology for Extremely Low rDS(ON) - Low Gate Charge - High Power and Current Handling Capability - These Devices are Pb−Free and are RoHS Compliant ## **Applications** - DC/DC Converters **MOSFET MAXIMUM RATINGS** (TC = 25 ° C unless otherwise noted) |**MOSFE**|**T MAXIMUM RATINGS**(TC= 25°C unless|**T MAXIMUM RATINGS**(TC= 25°C unless|otherwise n|oted)| |---|---|---|---|---| |**Symbol**|**Parameter**||**Ratings**|**Unit**| |VDSS|Drain to Source Voltage||30|V| |VGS|Gate to Source Voltage||±20|V| |ID|Drain
Current|Continuous (TA= 25°C,
VGS= 10 V) (Note 1)|58|A| |||Continuous (TA= 25°C,
VGS= 4.5 V) (Note 1)|51|A| |||Continuous (Tamb= 25°C,
VGS= 10 V, with R�JA= 52°C/W)
(Note 1)|13|A| |||Pulsed|Figure 4|A| |EAS|Single Pulse Avalanche Energy (Note 2)||53|mJ| |PD|Power Dissipation||55|W| ||Derate above 25°C||0.37|mW/°C| |TJ, TSTG|Operating and Storage Temperature||–55 to 175|°C| ## **MARKING DIAGRAM** **==> picture [166 x 136] intentionally omitted <==** **----- Start of picture text -----**
$Y&Z&3&K
FDD
8880
$Y = onsemi Logo
&Z = Assembly Plant Code
&3 = 3−Digit Date Code Format
&K = 2−Digits Lot Run Traceability Code
FDD8880 = Device Code
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D
G
S
N−Channel
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## **ORDERING INFORMATION** See detailed ordering and shipping information on page 12 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Package current limitation is 35A. 2. Starting TJ = 25 ° C, L = 0.14 mH, IAS = 28 A, VDD = 27 V, VGS = 10 V. Publication Order Number: **1** © Semiconductor Components Industries, LLC, 2008 **March, 2022 − Rev. 3** **FDD8880/D** **FDD8880, FDD8880−G** ## **THERMAL CHARACTERISTICS** |**Symbol**|**Parameter**|**Ratings**|**Unit**| |---|---|---|---| |R�JC|Thermal Resistance, Junction to Case TO−252|2.73|°C/W| |R�JA|Thermal Resistance, Junction to Ambient TO−252|100|°C/W| |R�JA|Thermal Resistance, Junction to Ambient TO−252, 1 in2Copper Pad Area|52|°C/W| **ELECTRICAL CHARACTERISTICS** (TC = 25 ° C unless otherwise noted) |**ELECTRIC**|**AL CHARACTERISTICS**(TC= 25°C u|nless otherwise noted)||||| |---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250�A, VGS= 0 V|30|−|−|V| |IDSS|Zero Gate Voltage Drain Current|VDS= 24 V, VGS= 0 V|−|−|1|�A| |||VDS= 24 V, VGS= 0 V, TC= 150°C|−|−|250|| |IGSS|Gate to Source Leakage Current|VGS=±20 V|−|−|±100|nA| |**ON CHARACTERISTICS**||||||| |VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250�A|1.2|−|2.5|V| |rDS(ON)|Drain to Source On Resistance|ID= 35 A, VGS= 10 V|−|0.007|0.009|�| |||ID= 35 A, VGS= 4.5 V|−|0.009|0.012|| |||ID= 35 A, VGS= 10 V, TJ= 175°C|−|0.013|0.015|| |**DYNAMIC CHARACTERISTICS**||||||| |CISS|Input Capacitance|VDS= 15 V, VGS= 0 V, f = 1 MHz|−|1260|−|pF| |COSS|Output Capacitance||−|260|−|pF| |CRSS|Reverse Transfer Capacitance||−|150|−|pF| |RG|Gate Resistance|VGS= 0.5 V, f = 1 MHz|−|2.3|−|�| |Qg(TOT)|Total Gate Charge at 10 V|VGS= 0 V to 10 V, VDD= 15 V,
ID= 35 A, Ig= 1.0 mA|−|23|31|nC| |Qg(5)|Total Gate Charge at 5 V|VGS= 0 V to 5 V, VDD= 15 V,
ID= 35 A, Ig= 1.0 mA|−|13|17|nC| |Qg(TH)|Threshold Gate Charge|VGS= 0 V to 1 V, VDD= 15 V,
ID= 35 A, Ig= 1.0 mA|−|1.3|1.7|nC| |Qgs|Gate to Source Gate Charge|VDD= 15 V, ID= 35 A, Ig= 1.0 mA|−|3.8|−|nC| |Qgs2|Gate Charge Threshold to Plateau||−|2.5|−|nC| |Qgd|Gate to Drain “Miller” Charge||−|5.0|−|nC| |**SWITCHING CHARACTERISTICS**(VGS= 10 V)||||||| |tON|Turn−On Time|VDD= 15 V, ID= 35 A, VGS= 10 V,
RGS= 10�|−|−|147|ns| |td(ON)|Turn−On Delay Time||−|8|−|ns| |tr|Rise Time||−|91|−|ns| |td(OFF)|Turn−Off Delay Time||−|38|−|ns| |tf|Fall Time||−|32|−|ns| |tOFF|Turn−Off Time||−|−|108|ns| |**DRAIN−SOURCE DIODE CHARACTERISTICS**||||||| |VSD|Source to Drain Diode Voltage|ISD= 35 A|−|−|1.25|V| |||ISD= 15 A|−|−|1.0|V| |trr|Reverse Recovery Time|ISD= 35 A, dISD/dt = 100 A/�s|−|−|27|ns| |QRR|Reverse Recovered Charge|ISD= 35 A, dISD/dt = 100 A/�s|−|−|14|nC| Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. **www.onsemi.com** **2** **FDD8880, FDD8880−G** ## **TYPICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) **==> picture [464 x 384] intentionally omitted <==** **----- Start of picture text -----**
1.2 60
CURRENT LIMITED
BY PACKAGE
1.0 50
0.8 40
VGS = 10 VGS = 10 V = 10 V
0.6 30
VGS = 4.5 VGS = 4.5 V = 4.5 V
0.4 20
0.2 10
0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150
TC, CASE TEMPERATURE ( ° C) TC, CASE TEMPERATURE (C, CASE TEMPERATURE (, CASE TEMPERATURE ( ° C)
Figure 1. Normalized Power Dissipation vs. Figure 2. Maximum Continuous Drain Current vs.
Case Temperature Case Temperature
2
DUTY CYCLE−DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01 PDM
0.01
t1
t2
NOTES:
DUTY FACTOR: D = t1 / t2
SINGLE PULSE PEAK TJ = PDM x Z � JC x R � JC + TC
0.001
10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
, DRAIN CURRENT (A)
IDD
POWER DISSIPATION MULTIPLIER
, NORMALIZED THERMAL IMPEDANCE
JC
�
Z
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60
CURRENT LIMITED
BY PACKAGE
50
40
VGS = 10 VGS = 10 V = 10 V
30
VGS = 4.5 VGS = 4.5 V = 4.5 V
20
10
0
25 50 75 100 125 150 175
TC, CASE TEMPERATURE (C, CASE TEMPERATURE (, CASE TEMPERATURE ( ° C)
, DRAIN CURRENT (A)
IDD
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**Figure 2. Maximum Continuous Drain Current vs. Case Temperature** **Figure 3. Normalized Maximum Transient Thermal Impedance** **==> picture [463 x 174] intentionally omitted <==** **----- Start of picture text -----**
500
TRANSCONDUCTANCE TC = 25 ° C
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION ABOVE 25 ° C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10 V
175 � TC
VGS = 4.5 V I � I25 � 150
� �
100
30
10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
, PEAK CURRENT (A)
IDM
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**Figure 4. Peak Current Capability** **www.onsemi.com** **3** **FDD8880, FDD8880−G** ## **TYPICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) (continued) **==> picture [218 x 146] intentionally omitted <==** **----- Start of picture text -----**
1000
10 � s
100
100 � s
10
OPERATION IN
THIS AREA MAY BE
LIMITED BY rDS(ON) 1 ms
1
SINGLE PULSE
10 ms
TTJC = MAX RATED = 25 ° C DC
0.1
1 10 60
, DRAIN CURRENT (A)
ID
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**==> picture [146 x 9] intentionally omitted <==** **----- Start of picture text -----**
VDS, DRAIN TO SOURCE VOLTAGE (V)
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**Figure 5. Forward Bis Safe Operating Area** **==> picture [217 x 162] intentionally omitted <==** **----- Start of picture text -----**
500
If R = 0
tAV = (L) (IAS) / (1.3 x RATED BVDSS − VDD)
If R ≠ 0
100 tAV = (L / R) ln [(IAS x R) / (1.3 x RATED BVDSS − VDD) +1]
STARTING TJ = 25 ° C
10
STARTING TJ = 150 ° C
1
0.01 0.1 1 10
tAV, TIME IN AVALANCHE (ms)
, AVALANCHE CURRENT (A)
IAS
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NOTE: Refer to **onsemi** Application Notes AN−7514 and AN−7515 **Figure 6. Unclamped Inductive Switching Capability** **==> picture [230 x 374] intentionally omitted <==** **----- Start of picture text -----**
80
PULSE DURATION = 80 � s
DUTY CYCLE = 0.5% MAX
60 VDD = 15 V
40
TJ = 25 ° C
20
TJ = 175 ° C TJ = −55 ° C
0
1.5 2.0 2.5 3.0 3.5 4.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics
25
PULSE DURATION = 80 � s
DUTY CYCLE = 0.5% MAX
20
ID = 35 A
15
ID = 1 A
10
5
2 4 6 8 10
VGS, GATE TO SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
) �
, DRAIN TO SOURCE
ON RESISTANCE (m
rDS(ON)
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**Figure 9. Drain to Source On Resistance vs. Gate Voltage and Drain Current** **==> picture [218 x 165] intentionally omitted <==** **----- Start of picture text -----**
80
VGS = 5 V
60
VGS = 10 V VGS = 4 V
40
VGS = 3 V
20
TC = 25 ° C
PULSE DURATION = 80 � s
DUTY CYCLE = 0.5% MAX
0
0 0.25 0.5 0.75 1.0
VDS, DRAIN TO SOURCE VOLTAGE (V)
, DRAIN CURRENT (A)
ID
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**Figure 8. Saturation Characteristics** **==> picture [229 x 165] intentionally omitted <==** **----- Start of picture text -----**
1.8
PULSE DURATION = 80 � s
1.6 DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
VGS = 10 V, ID = 35 A
0.6
−80 −40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( ° C)
NORMALIZED DRAIN TO
SOURCE ON RESISTANCE
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**Figure 10. Normalized Drain to Source On Resistance vs. Junction Temperature** **www.onsemi.com** **4** **FDD8880, FDD8880−G** ## **TYPICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) (continued) **==> picture [230 x 147] intentionally omitted <==** **----- Start of picture text -----**
1.2
VGS = VDS, ID = 250 � A
1.0
0.8
0.6
0.4
−80 −40 0 40 80 120 160 200
VOLTAGE
NORMALIZED GATE THRESHOLD
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**Figure 11. Normalized Gate Threshold Voltage vs. Junction Temperature** **==> picture [218 x 163] intentionally omitted <==** **----- Start of picture text -----**
2000
1000 CISS = CGS + CGD
CRSS = CGD COSS ≅ CDS + CGD
VGS = 0 V, f = 1 MHz
100
0.1 1 10 30
VDS, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
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**Figure 13. Capacitance vs. Drain to Source Voltage** **==> picture [229 x 376] intentionally omitted <==** **----- Start of picture text -----**
1.10
ID = 250 � A
1.05
1.00
0.95
0.90
−80 −40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( ° C)
Figure 12. Normalized Drain to Source
Breakdown Voltage vs. Junction Temperature
10
VDD = 15 V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
2
ID = 35 A
ID = 1 A
0
0 5 10 15 20 25
Qg, GATE CHARGE (nC)
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
, GATE TO SOURCE VOLTAGE (V)
GS
V
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**Figure 14. Gate Charge Waveforms for Constant Gate Current** **www.onsemi.com** **5** **FDD8880, FDD8880−G** ## **TEST CIRCUITS AND WAVEFORMS** **==> picture [213 x 136] intentionally omitted <==** **----- Start of picture text -----**
V DS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS RG +VDD
VGS −
DUT
t P
0 V IAS
0.01 �
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**Figure 15. Unclamped Energy Test Circuit** **==> picture [199 x 141] intentionally omitted <==** **----- Start of picture text -----**
BVDSS
t P
VDS
IAS
VDD
0
t AV
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**Figure 16. Unclamped Energy Waveforms** **==> picture [189 x 136] intentionally omitted <==** **----- Start of picture text -----**
VDS
L
VGS +
VDD
−
DUT
Ig(REF)
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**Figure 17. Gate Charge Test Circuit** **==> picture [219 x 142] intentionally omitted <==** **----- Start of picture text -----**
VDD Qg(TOT)
VDS VGS
VGS = 10 V
Qg(5)
Qgs2 VGS = 5 V
VGS = 1 V
0
Qg(TH)
Qgs Qgd
Ig(REF)
0
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**Figure 18. Gate Charge Waveforms** **==> picture [202 x 136] intentionally omitted <==** **----- Start of picture text -----**
VDS
RL
VGS +VDD
−
DUT
RGS
VGS
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**Figure 19. Switching Time Test Circuit** **==> picture [202 x 140] intentionally omitted <==** **----- Start of picture text -----**
t ON t OFF
t d(ON) t d(OFF)
tr tf
VDS
90% 90%
10% 10%
0
90%
VGS 50% 50%
PULSE WIDTH
10%
0
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**Figure 20. Switching Time Waveforms** **www.onsemi.com** **6** **FDD8880, FDD8880−G** ## **THERMAL RESISTANCE VS. MOUNTING PAD AREA** The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient ° ° temperature, TA ( C), and thermal resistance R�JA ( C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. **==> picture [225 x 24] intentionally omitted <==** In using surface mount devices such as the TO−252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. **onsemi** provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R�JA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR−4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the **onsemi** device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and Equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. **==> picture [225 x 72] intentionally omitted <==** **----- Start of picture text -----**
23.84
R � JA � 33.32 �
(0.268 � Area) Area in Inches Squared
(eq. 2)
154
R � JA � 33.32 �
(1.73 � Area) Area in Inches Squared
(eq. 3)
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125
R � JA = 33.32 + 23.84 / (0.268 + Area) eq.2
R � JA = 33.32 + 154 / (1.73 + Area) eq.3
100
75
50
25
0.01 0.1 1 10
(0.0645) (0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
C/W)
°
(
JA
�
R
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**Figure 21. Thermal Resistance vs. Mounting Pad Area** **www.onsemi.com** **7** **FDD8880, FDD8880−G** ## **PSPICE ELECTRICAL MODEL** .SUBCKT FDD8880 2 1 3 ; rev April 2004 Ca 12 8 9.5e−10 Cb 15 14 9.5e−10 Cin 6 8 1.15e−9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 33.15 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.3e−9 Ldrain 2 5 1.0e−9 Lsource 3 7 1.7e−9 RLgate 1 9 53 RLdrain 2 5 10 RLsource 3 7 17 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.2e−3 Rgate 9 20 2.2 RSLC1 5 51 RSLCMOD 1e−6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 3.2e−3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*170),5))} .MODEL DbodyMOD D (IS=2E−12 IKF=10 N=1.01 RS=3.76e−3 TRS1=8e−4 TRS2=2e−7 + CJO=4.8e−10 M=0.55 TT=1e−17 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e−3 TRS2=−8.9e−6) .MODEL DplcapMOD D (CJO=5.5e−10 IS=1e−30 N=10 M=0.45) .MODEL MmedMOD NMOS (VTO=2.0 KP=10 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=2.2) .MODEL MstroMOD NMOS (VTO=2.5 KP=170 IS=1e−30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=1.69 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1) **www.onsemi.com** **8** **FDD8880, FDD8880−G** .MODEL RbreakMOD RES (TC1=8.3e−4 TC2=−8e−7) .MODEL RdrainMOD RES (TC1=1.8e−3 TC2=8e−6) .MODEL RSLCMOD RES (TC1=9e−4 TC2=1e−6) .MODEL RsourceMOD RES (TC1=5e−3 TC2=1e−6) .MODEL RvthresMOD RES (TC1=−1e−3 TC2=−8.2e−6) .MODEL RvtempMOD RES (TC1=−2.6e−3 TC2=2e−7) .MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−3.5) .MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−3.5 VOFF=−4) .MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.3 VOFF=−0.8) .MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−0.8 VOFF=−1.3) .ENDS NOTE: For further discussion of the PSPICE model, consult **A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. **==> picture [319 x 258] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
515 ESLC 11
ESG +− 68 EVTHRES RDRAIN50 16 EBREAK +−1718 DBODY
LGATE EVTEMP + 198 − 21 MWEAK
GATE RGATE + 18 − 6
1 9 20 22 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT −19
EGS 68 EDS 58 + VBAT
− − 8
22
RVTHRES
+
−
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**Figure 22.** **www.onsemi.com** **9** **FDD8880, FDD8880−G** ## **SABER ELECTRICAL MODEL** rev April 2004 template FDD8880 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e−12,ikf=10,nl=1.01,rs=3.76e−3,trs1=8e−4,trs2=2e−7,cjo=4.8e−10,m=0.55,tt=1e−17,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e−3,trs2=−8.9e−6) dp..model dplcapmod = (cjo=5.5e−10,isl=10e−30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=2.0,kp=10,is=1e−30, tox=1) m..model mstrongmod = (type=_n,vto=2.5,kp=170,is=1e−30, tox=1) m..model mweakmod = (type=_n,vto=1.69,kp=0.05,is=1e−30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−3.5) sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−3.5,voff=−4) sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.3,voff=−0.8) sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=−0.8,voff=−1.3) c.ca n12 n8 = 9.5e−10 c.cb n15 n14 = 9.5e−10 c.cin n6 n8 = 1.15e−9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 33.15 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.3e−9 l.ldrain n2 n5 = 1.0e−9 l.lsource n3 n7 = 1.7e−9 res.rlgate n1 n9 = 53 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 17 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=8.3e−4,tc2=−8e−7 res.rdrain n50 n16 = 3.2e−3, tc1=1.8e−3,tc2=8e−6 res.rgate n9 n20 = 2.2 res.rslc1 n5 n51 = 1e−6, tc1=9e−4,tc2=1e−6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.2e−3, tc1=5e−3,tc2=1e−6 res.rvthres n22 n8 = 1, tc1=−1e−3,tc2=−8.2e−6 res.rvtemp n18 n19 = 1, tc1=−2.6e−3,tc2=2e−7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod **www.onsemi.com** **10** ## **FDD8880, FDD8880−G** v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5)) } } **==> picture [319 x 258] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51
RSLC2
ISCL
− 50 DBREAK
6 RDRAIN
ESG + 8 EVTHRES 16 11 DBODY
LGATE EVTEMP + 198 − 21 MWEAK
GATE1 9RGATE20+ 1822 − 6 MMED EBREAK+
RLGATE MSTRO 17
CIN 8 −18 7 LSOURCE SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT −19
EGS 68 EDS 58 + VBAT
− − 8
22
RVTHRES
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**Figure 23.** **www.onsemi.com** **11** **FDD8880, FDD8880−G** ## **SPICE THERMAL MODEL** REV 23 April 2004 FDD8880T CTHERM1 TH 6 8e−4 CTHERM2 6 5 1e−3 CTHERM3 5 4 2.5e−3 CTHERM4 4 3 2.6e−3 CTHERM5 3 2 8e−3 CTHERM6 2 TL 1.5e−2 RTHERM1 TH 6 1.44e−1 RTHERM2 6 5 1.9e−1 RTHERM3 5 4 3.0e−1 RTHERM4 4 3 4.0e−1 RTHERM5 3 2 5.7e−1 RTHERM6 2 TL 5.8e−1 ## **SABER THERMAL MODEL** SABER thermal model FDD8880T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =8e−4 ctherm.ctherm2 6 5 =1e−3 ctherm.ctherm3 5 4 =2.5e−3 ctherm.ctherm4 4 3 =2.6e−3 ctherm.ctherm5 3 2 =8e−3 ctherm.ctherm6 2 tl =1.5e−2 rtherm.rtherm1 th 6 =1.44e−1 rtherm.rtherm2 6 5 =1.9e−1 rtherm.rtherm3 5 4 =3.0e−1 rtherm.rtherm4 4 3 =4.0e−1 rtherm.rtherm5 3 2 =5.7e−1 rtherm.rtherm6 2 tl =5.8e−1 } **==> picture [159 x 407] intentionally omitted <==** **----- Start of picture text -----**
th JUNCTION
RTHERM1 CTHERM1
6
RTHERM2 CTHERM2
5
RTHERM3 CTHERM3
4
RTHERM4 CTHERM4
3
RTHERM5 CTHERM5
2
RTHERM6 CTHERM6
tl CASE
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**Figure 24.** ## **PACKAGE MARKING AND ORDERING INFORMATION** |**Device**|**Device Marking**|**Package Type**|**Reel Size**|**Tape Width**|**Shipping**†| |---|---|---|---|---|---| |FDD8880|FDD8880|DPAK3 (TO−252 3 LD)
(TO−252AA)
(Pb−Free)|13”|16 mm|2500 / Tape & Reel| |FDD8880−G|FDD8880|DPAK3 (TO−252 3 LD)
(TO−252AA)
(Pb−Free)|13”|16 mm|2500 / Tape & Reel| †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **www.onsemi.com** **12** ## MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** **==> picture [94 x 29] intentionally omitted <==** **----- Start of picture text -----**
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE O
**----- End of picture text -----**
**==> picture [80 x 8] intentionally omitted <==** **----- Start of picture text -----**
DATE 30 SEP 2016
**----- End of picture text -----**
## **DOCUMENT NUMBER:** ## **DESCRIPTION:** ## **98AON13810G** ## **DPAK3 (TO−252 3 LD)** Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. ## **PAGE 1 OF 1** **onsemi** and are trademarks of Semiconductor Components Industries, LLC dba onsemi **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. www.onsemi.com © Semiconductor Components Industries, LLC, 2019 **onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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