# Power MOSFET, N Channel, 100 V, 44 A, 0.028 ohm, TO-252 (DPAK), Surface Mount
**URL**: https://novapart.co/products/FDD3672/power-mosfet-n-channel-100-v-44-a-0028-ohm-to-252
**SKU**: FDD3672
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.6940
**Stock**: 1000+
**Lead Time**: 148 days (indicative)
## Description
Transistor Polarity:N Channel; Continuous Drain Current Id:44A; Drain Source Voltage Vds:100V; On Resistance Rds(on):0.024ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Power Dissipa
## Specifications
| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | Lead (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 135mW |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | TO-252 (DPAK) |
| Drain Source Voltage Vds | 100V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 44A |
| Drain Source On State Resistance | 0.028ohm |
| Gate Source Threshold Voltage Max | 4V |
## Datasheet
📄 [Download PDF](https://novapart.co/datasheet/farnell:1495260/)
## **Is Now Part of**
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## **March 2015 FDD3672 N-Channel UltraFET**[®] **Trench MOSFET 100V, 44A, 28m** Ω
## **Applications**
- **Features Applications** • rDS(ON) = 24m Ω (Typ.), VGS = 10V, ID = 44A • DC/DC converters and Off-Line UPS • Qg(tot) = 24nC (Typ.), VGS = 10V • Distributed Power Architectures and VRMs • Low Miller Charge • Primary Switch for 24V and 48V Systems
- Low Miller Charge
- • Low Qrr Body Diode
- Optimized efficiency at high frequencies • High Voltage Synchronous Rectifier
- UIS Capability (Single Pulse and Repetitive Pulse)
**==> picture [316 x 108] intentionally omitted <==**
**----- Start of picture text -----**
Formerly developmental type 82760
D
DRAIN
(FLANGE)
GATE
SOURCE G
TO-252AA
S
**----- End of picture text -----**
## **MOSFET Maximum Ratings** TC = 25°C unless otherwise noted
|**MOSFET Maximum Ratings** TC = 25°C unless otherwise notedC = 25°C unless otherwise noted= 25°C unless otherwise noted||||
|---|---|---|---|
|**Symbol**
**Parameter**||**Ratings**|**Units**|
|VDSS
Drain to Source Voltage||100|V|
|VGS
Gate to Source Voltage||±20|V|
|Drain Current||||
|Continuous(TC= 25oC, VGS= 10V)||44|A|
|ID
Continuous(TC= 100oC, VGS= 10V)||31|A|
|Continuous(Tamb= 25oC, VGS= 10V, RθJA= 52oC/W)||6.5|A|
|Pulsed||Figure 4|A|
|EAS
Single Pulse Avalanche Energy (Note 1)||120|mJ|
|PD
Power dissipation
Derate above 25oC||135
0.9|W
W/oC|
|TJ, TSTG
Operatingand Storage Temperature||-55 to 175|oC|
|**Thermal Characteristics**||||
|RθJC
Thermal Resistance Junction to Case TO-252
1.11
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-252
100
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-252, 1in2copperpad area
52
oC/W
~~————_——————~~||||
|**Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.**||||
|**All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems**||**All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems**||
|**certification.**||||
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|||||
|---|---|---|---|---|---|---|---|---|---|---|
|**Device Marking**||**Device**|**Package**||**Reel Size**||**Tape Width**||**Quantity**||
|FDD3672||FDD3672|TO-252AA||330mm||16mm||2500 units||
|**Electrical Characteristics**TC= 25°C unless otherwise noted|||||||||||
|**Symbol**|**Parameter**|||**Test Conditions**|||**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**|||||||||||
|BVDSS|Drain to Source Breakdown Voltage|||ID= 250µA, VGS||= 0V|100|-|-|V|
|IDSS|Zero Gate Voltage Drain Current|||VDS= 80V
VGS= 0V|||-|-|1|µA|
|||||||TC= 150oC|-|-|250||
|IGSS|Gate to Source Leakage Current|||VGS=±20V|||-|-|±100|nA|
|**On Characteristics**|||||||||||
|VGS(TH)|Gate to Source Threshold Voltage|||VGS= VDS, ID= 250µA|||2|-|4|V|
|rDS(ON)|Drain to Source On Resistance|||ID = 44A, VGS= 10V|||-|0.024|0.028|Ω|
|||||ID= 21A, VGS= 6V,|||-|0.031|0.047||
|||||ID=44A, VGS=10V, TC=175oC|||-|0.054|0.068||
|**Dynamic Characteristics**|||||||||||
|CISS|Input Capacitance|||VDS= 25V, VGS= 0V,
f = 1MHz|||-|1710|-|pF|
|COSS|Output Capacitance||||||-|247|-|pF|
|CRSS|Reverse Transfer Capacitance||||||-|62|-|pF|
|Qg(TOT)|Total Gate Charge at 10V|||VGS= 0V to 10V|||-|24|36|nC|
|Qg(TH)|Threshold Gate Charge|||VGS= 0V to 2V|||-|3|4.5|nC|
|Qgs|Gate to Source Gate Charge||||||-|8.6|-|nC|
|Qgs2|Gate Charge Threshold to Plateau||||||-|5.6|-|nC|
|Qgd|Gate to Drain “Miller” Charge||||||-|5.6|-|nC|
|**Resistive Switching Characteristics**(VGS=||||10V)|||||||
|tON|Turn-On Time|||VDD= 50V, ID= 44A
VGS= 10V, RGS= 11.0Ω|||-|-|104|ns|
|td(ON)|Turn-On DelayTime||||||-|11|-|ns|
|tr|Rise Time||||||-|59|-|ns|
|td(OFF)|Turn-Off DelayTime||||||-|26|-|ns|
|tf|Fall Time||||||-|44|-|ns|
|tOFF|Turn-Off Time||||||-|-|104|ns|
|**Drain-Source Diode Characteristics**|||||||||||
|VSD|Source to Drain Diode Voltage|||ISD= 44A|||-|-|1.25|V|
|||||ISD= 21A|||-|-|1.0|V|
|trr|Reverse Recovery Time|||ISD= 44A, dISD/dt =100A/µs|||-|-|52|ns|
|QRR|Reverse Recovery Charge|||ISD= 44A, dISD/dt =100A/µs|||-|-|80|nC|
**Notes:**
**1:** Starting TJ = 25°C, L = 0.6mH, IAS = 20A.
- **2:** Pulse Width = 100s
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
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Typical Characteristics TC = 25°C unless otherwise noted
1.2 50
VGS = 10V
1.0
40
0.8
30
0.6
20
0.4
0.2 10
0 0
0 25 50 75 100 125 150 175
25 50 75 100 125 150 175
TC , CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
0.05
0.02
0.01
PDM
0.1
t 1
t 2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TRANSCONDUCTANCE T C = 25 [o] C
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION ABOVE 25 [o] C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V I = I25 175 - TC
150
100
30
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
FDD3672
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJC θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
**----- End of picture text -----**
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
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**----- Start of picture text -----**
Typical Characteristics TC = 25°C unless otherwise noted
300 80
t If R = 0AV = (L)(I AS )/(1.3*RATED BV DSS - V DD ) DUTY CYCLE = 0.5% MAXPULSE DURATION = 80 µ s
100 If RtAV = ≠ 0(L/R)ln[(IAS * R)/(1.3 * RATED BVDSS - VDD) +1] VDD = 15V
60
STARTING TJ = 25 [o] C TJ = 175 [o] C
40
10
TJ = 25 [o] C
STARTING TJ = 150 [o] C 20
TJ = -55 [o] C
1 0
0.001 0.01 0.1 1 10 3.5 4.0 4.5 5.0 5.5 6.0 6.5
tAV, TIME IN AVALANCHE (ms) VGS , GATE TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Transfer Characteristics
Figure 5. Unclamped Inductive Switching
Capability
80 40
PULSE DURATION = 80 µ s
TC = 25 [o] C VGS = 10V VGS = 7V DUTY CYCLE = 0.5% MAX
35
60 VGS = 6V VGS = 6V
30
40
PULSE DURATION = 80DUTY CYCLE = 0.5% MAX µ s 25 V GS = 10V
20
20
VGS = 5V
0 15
0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 50
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Drain
Current
2.5 1.2
PULSE DURATION = 80 µ s VGS = VDS, ID = 250 µ A
DUTY CYCLE = 0.5% MAX
2.0 1.0
1.5 0.8
1.0 0.6
VGS = 10V, ID = 44A
0.5 0.4
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Normalized Drain to Source On Figure 10. Normalized Gate Threshold Voltage vs
Resistance vs Junction Temperature Junction Temperature
FDD3672
, DRAIN CURRENT (A)
, AVALANCHE CURRENT (A)IAS ID
) Ω
, DRAIN CURRENT (A)
ID
DRAIN TO SOURCE ON RESISTANCE (m
ON RESISTANCE NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
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©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
## **Typical Characteristics** TC = 25°C unless otherwise noted
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**----- Start of picture text -----**
1.2 3000
ID = 250 µ A
1000 CISS = CGS + CGD
1.1 COSS ≅ CDS + CGD
CRSS = CGD
100
1.0
VGS = 0V, f = 1MHz
0.9 10
-80 -40 0 40 80 120 160 200 0.1 1 10 100
TJ, JUNCTION TEMPERATURE ( [o] C) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain to Source Figure 12. Capacitance vs Drain to Source
Breakdown Voltage vs Junction Temperature Voltage
10 200
VDD = 50V 100
8
100 us
6 10
THIS AREA IS
LIMITED BY r
DS(on)
4
SINGLE PULSE 1 ms
1
TJ = MAX RATED
2 WAVEFORMS INDESCENDING ORDER: R � JC = 1.11 [o] C/W 10 ms
ID = 44A TC = 25 [o] C DC
ID = 21A 0.1
0 1 10 100 300
0 5 10 15 20 25
VDS, DRAIN to SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
BREAKDOWN VOLTAGE C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
, DRAIN CURRENT (A)
ID
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**Figure 13. Gate Charge Waveforms for Constant Gate Currents**
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**----- Start of picture text -----**
Figure 14. Forward Bias Safe
Operating Area
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©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
## **Test Circuits and Waveforms**
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VDS BVDSS
tP
L VDS
IAS
VARY tP TO OBTAIN + VDD
REQUIRED PEAK IAS RG VDD
VGS -
DUT
tP
0V IAS 0
0.01 Ω
tAV
**----- End of picture text -----**
**Figure 14. Unclamped Energy Test Circuit**
**Figure 15. Unclamped Energy Waveforms**
**==> picture [413 x 139] intentionally omitted <==**
**----- Start of picture text -----**
VDS VDD Qg(TOT)
VDS
L
VGS = 10V
VGS +
- VDD VGS
DUT VGS = 2V
Ig(REF) Qg(TH)0 Q gs 2
Qgs Qgd
Ig(REF)
0
**----- End of picture text -----**
**Figure 16. Gate Charge Test Circuit**
**Figure 17. Gate Charge Waveforms**
**==> picture [421 x 141] intentionally omitted <==**
**----- Start of picture text -----**
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 0 10%
**----- End of picture text -----**
**Figure 18. Switching Time Test Circuit**
**Figure 19. Switching Time Waveforms**
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
## _**Thermal Resistance vs. Mounting Pad Area**_
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance R θ JA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
**==> picture [193 x 22] intentionally omitted <==**
In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board.
**==> picture [206 x 161] intentionally omitted <==**
**----- Start of picture text -----**
125
R θ JA = 33.32+ 23.84/(0.268+Area) EQ.2
100 R θ JA = 33.32+ 154/(1.73+Area) EQ.3
75
50
25
0.01 0.1 1 10
(0.0645) (0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
oC/W)(RJA θ
**----- End of picture text -----**
**Figure 20. Thermal Resistance vs Mounting Pad Area**
2. The number of copper layers and the thickness of the board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in.
Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 20 defines the R θ JA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads.
**==> picture [197 x 70] intentionally omitted <==**
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
## _**PSPICE Electrical Model**_
.SUBCKT FDD3672 2 1 3 ; rev May 2002 CA 12 8 5.8e-10 Cb 15 14 6.8e-10 Cin 6 8 1.6e-9
**==> picture [319 x 257] intentionally omitted <==**
**----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
515 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE1 9RGATE20+ 1822 - 6 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 105 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 9.56e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.45e-9
RLgate 1 9 95.6 RLdrain 2 5 10 RLsource 3 7 44.5
Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 6.0e-3 Rgate 9 20 1.5 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 9.5e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))}
.MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6 + CJO=1.2e-9 M=0.58 TT=3.75e-8 XTI=4.0) .MODEL DbreakMOD D (RS=15 TRS1=4.0e-3 TRS2=-5.0e-6) .MODEL DplcapMOD D (CJO=3.8e-10 IS=1.0e-30 N=10 M=0.60)
.MODEL MmedMOD NMOS (VTO=3.6 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.5) .MODEL MstroMOD NMOS (VTO=4.3 KP=59 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.09 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1)
.MODEL RbreakMOD RES (TC1=9.0e-4 TC2=-1.0e-7) .MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6) .MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-3.5e-3 TC2=-1.5e-5) .MODEL RvtempMOD RES (TC1=-4.3e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
## _**SABER Electrical Model**_
REV May 2002 template FDD3672 n2,n1,n3 electrical n2,n1,n3 { var i iscl
dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0) dp..model dbreakmod = (rs=15,trs1=4.0e-3,trs2=-5.0e-6)
dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60)
m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1)
**==> picture [433 x 258] intentionally omitted <==**
**----- Start of picture text -----**
m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5) DPLCAP 5 DRAIN2
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0) 10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3) RSLC1 RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5) 51
c.ca n12 n8 = 5.8e-10 RSLC2
c.cb n15 n14 = 6.8e-10 ISCL
c.cin n6 n8 = 1.6e-9
- 50 DBREAK
dp.dbody n7 n5 = model=dbodymoddp.dbreak n5 n11 = model=dbreakmod ESG + 68 EVTHRES RDRAIN16 11 DBODY
dp.dplcap n10 n5 = model=dplcapmod LGATE EVTEMP + 198 - 21 MWEAK
spe.ebreak n11 n7 n17 n18 = 105spe.eds n14 n8 n5 n8 = 1 GATE1 9RGATE20+ 1822 - 6 MMED EBREAK+
spe.egs n13 n8 n6 n8 = 1 RLGATE MSTRO 17
spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1 CIN 8 -18 7 LSOURCE SOURCE3
spe.evtemp n20 n6 n18 n22 = 1 RSOURCE
RLSOURCE
i.it n8 n17 = 1 S1A S2A
12 13 14 15 17 RBREAK 18
l.lgate n1 n9 = 95.6e-9 8 13
l.ldrain n2 n5 = 1.0e-9 S1B S2B RVTEMP
l.lsource n3 n7 = 4.45e-9 CA 13+ CB+ 14 IT -19
res.rlgate n1 n9 = 9.56res.rldrain n2 n5 = 10 EGS 68 EDS 58 + VBAT
res.rlsource n3 n7 = 44.5 - - 8
22
RVTHRES
**----- End of picture text -----**
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e-7 res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5 res.rgate n9 n20 = 1.5 res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=1.0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5 res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3)) }
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
|**_SPICE Thermal Model_**
REV May 2002
FDD3672
CTHERM1 TH 6 3.2e-3
CTHERM2 6 5 3.3e-3
CTHERM3 5 4 3.4e-3
CTHERM4 4 3 3.5e-3
CTHERM5 3 2 6.4e-3
CTHERM6 2 TL 1.9e-2
RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.4e-1
RTHERM6 2 TL 3.5e-1
**_SABER Thermal Model_**
SABER thermal model FDD3672
template thermal_model th tl
thermal_c th, tl
{
cctherm.ctherm1 th 6 =3.2e-3
ctherm.ctherm2 6 5 =3.3e-3
ctherm.ctherm3 5 4 =3.4e-3
ctherm.ctherm4 4 3 =3.5e-3
ctherm.ctherm5 3 2 =6.4e-3
ctherm.ctherm6 2 tl =1.9e-2
rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =5.0e-3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =10.5e-2
rtherm.rtherm5 3 2 =3.4e-1
rtherm.rtherm6 2 tl =3.5e-1
}
**RTHERM4**
**RTHERM6**
**RTHERM5**
**RTHERM3**
**RTHERM2**
**RTHERM1**|**CTHERM4**
**CTHERM6**
**CTHERM5**
**CTHERM3**
**CTHERM2**
**CTHERM1**
**tl**
**2**
**3**
**4**
**5**
**6**
**th**
**JUNCTION**
**CASE**|
|---|---|
©2010 Fairchild Semiconductor Corporation
FDD3672 Rev. 1.2
## ~~—~~
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## **PRODUCT STATUS DEFINITIONS**
|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications may change
in anymanner without notice.|
|Preliminary|First Production|Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
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The datasheet is for reference information only.|
Rev. I73
FDD3672 Rev. 1.2
©2010 Fairchild Semiconductor Corporation
**==> picture [37 x 58] intentionally omitted <==**
**==> picture [37 x 54] intentionally omitted <==**
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