# Power MOSFET, N Channel, 150 V, 21 A, 0.058 ohm, TO-252AA, Surface Mount ![Product image](https://novapart.co/image/farnell:2454151RL/) **URL**: https://novapart.co/products/FDD2582/power-mosfet-n-channel-150-v-21-a-0058-ohm-to **SKU**: FDD2582 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4130 **Stock**: 1000+ **Lead Time**: 141 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:21A; Drain Source Voltage Vds:150V; On Resistance Rds(on):0.058ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 95W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 95W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.058ohm | | Transistor Case Style | TO-252AA | | Drain Source Voltage Vds | 150V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 21A | | Drain Source On State Resistance | 0.058ohm | | Automotive Qualification Standard | - | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2454151RL/) ## **Is Now Part of** **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [419 x 39] intentionally omitted <==** **----- Start of picture text -----**
March 2015
FDD2582
N-Channel PowerTrench [®] MOSFET
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## **150V, 21A, 66m** Ω ## **Features Applications** - rDS(ON) = 58mΩ (Typ.), VGS = 10V, ID = 7A - Qg(tot) = 19nC (Typ.), VGS = 10V - Low Miller Charge - DC/DC converters and Off-Line UPS - Distributed Power Architectures and VRMs - Primary Switch for 24V and 48V Systems - Low QRR[Body Diode] - UIS Capability (Single Pulse and Repetitive Pulse) - Qualified to AEC Q101 Formerly developmental type 82855 - High Voltage Synchronous Rectifier - Direct Injection / Diesel Injection System - 42V Automotive Load Control - Electronic Valve Train System **==> picture [349 x 102] intentionally omitted <==** **----- Start of picture text -----**
DRAIN
(FLANGE) D
GATE
G
SOURCE
TO-252AA
S
FDD SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
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|**MOSFET Maximum Ratings **TC = 25°C unless otherwise notedC = 25°C unless otherwise noted= 25°C unless otherwise noted||| |---|---|---| |**Symbol**
**Parameter**|**Ratings**|**Units**| |VDSS
Drain to Source Voltage|150|V| |VGS
Gate to Source Voltage|±20|V| |Drain Current||| |ID
Continuous(TC= 25oC, VGS= 10V)
Continuous(TC= 100oC, VGS= 10V)|21
15|A| |Continuous(Tamb= 25oC, VGS= 10V, RθJA= 52oC/W)|3.7|A| |Pulsed|Figure 4|A| |EAS
Single Pulse Avalanche Energy (Note 1)|59|mJ| |PD
Power dissipation
Derate above 25oC|95
0.63|W
W/oC| |TJ, TSTG
Operatingand Storage Temperature|-55 to 175|oC| |**Thermal Characteristics**||| |RθJC
Thermal Resistance Junction to Case TO-252
1.58
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-252
100
oC/W
RθJA
Thermal Resistance Junction to Ambient TO-252, 1in2copper pad area
52
oC/W
~~————_——————~~||| |**This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a**||| |**copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/**||| |**Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.**||| |**All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems**||| |**certification.**||| FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation |**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**|**Package Marking and Ordering Information**||||| |---|---|---|---|---|---|---|---|---|---|---| |**Device Marking**||**Device**|**Package**||**Reel Size**||**Tape Width**||**Quantity**|| |FDD2582||FDD2582|TO-252AA||330mm||16mm||2500 units|| |**Electrical Characteristics**TC= 25°C unless otherwise noted||||||||||| |**Symbol**|**Parameter**|||**Test Conditions**|||**Min**|**Typ**|**Max**|**Units**| |**Off Characteristics**||||||||||| |BVDSS|Drain to Source Breakdown Voltage|||ID= 250µA, VGS||= 0V|150|-|-|V| |IDSS|Zero Gate Voltage Drain Current|||VDS= 120V
VGS= 0V|||-|-|1|µA| |||||||TC= 150oC|-|-|250|| |IGSS|Gate to Source Leakage Current|||VGS=±20V|||-|-|±100|nA| |**On Characteristics**||||||||||| |VGS(TH)|Gate to Source Threshold Voltage|||VGS= VDS, ID= 250µA|||2|-|4|V| |rDS(ON)|Drain to Source On Resistance|||ID= 7A, VGS= 10V|||-|0.058|0.066|Ω| |||||ID= 4A, VGS= 6V,|||-|0.066|0.099|| |||||ID= 7A, VGS= 10V,
TC= 175oC|||-|0.151|0.172|| |**Dynamic Characteristics**||||||||||| |CISS|Input Capacitance|||VDS= 25V, VGS= 0V,
f = 1MHz|||-|1295|-|pF| |COSS|Output Capacitance||||||-|145|-|pF| |CRSS|Reverse Transfer Capacitance||||||-|30|-|pF| |Qg(TOT)|Total Gate Charge at 10V|||VGS= 0V to 10V|||-|19|25|nC| |Qg(TH)|Threshold Gate Charge|||VGS= 0V to 2V|||-|2.4|3.2|nC| |Qgs|Gate to Source Gate Charge||||||-|6.2|-|nC| |Qgs2|Gate Charge Threshold to Plateau||||||-|3.8|-|nC| |Qgd|Gate to Drain “Miller” Charge||||||-|4.2|-|nC| |**Resistive Switching Characteristics**(VGS=||||10V)||||||| |tON|Turn-On Time|||VDD= 75V, ID= 7A
VGS= 10V, RGS= 16Ω|||-|-|41|ns| |td(ON)|Turn-On Delay Time||||||-|8|-|ns| |tr|Rise Time||||||-|19|-|ns| |td(OFF)|Turn-Off Delay Time||||||-|32|-|ns| |tf|Fall Time||||||-|19|-|ns| |tOFF|Turn-Off Time||||||-|-|77|ns| |**Drain-Source Diode Characteristics**||||||||||| |VSD|Source to Drain Diode Voltage|||ISD= 7A|||-|-|1.25|V| |||||ISD= 4A|||-|-|1.0|V| |trr|Reverse RecoveryTime|||ISD= 7A, dISD/dt = 100A/µs|||-|-|67|ns| |QRR|Reverse Recovered Charge|||ISD= 7A, dISD/dt = 100A/µs|||-|-|134|nC| **Notes:** **1:** Starting TJ = 25°C, L = 1.17 mH, IAS = 10A. FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation **==> picture [433 x 600] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TC = 25°C unless otherwise noted
1.2 25
VGS = 10V
1.0
20
0.8
15
0.6
10
0.4
0.2 5
0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
SINGLE PULSE DUTY FACTOR: D = t 1 /t 2
PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
300
TRANSCONDUCTANCE TC = 25 [o] C
MAY LIMIT CURRENT FOR TEMPERATURES
IN THIS REGION ABOVE 25 [o] C DERATE PEAK
CURRENT AS FOLLOWS:
100 I = I25 175 - TC
150
VGS = 10V
20
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJC θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
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FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation **==> picture [256 x 12] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TC = 25°C unless otherwise noted
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**==> picture [430 x 588] intentionally omitted <==** **----- Start of picture text -----**
200 100
10 µ s If R = 0
100 t AV = (L)(I AS )/(1.3*RATED BV DSS - V DD )
If R ≠ 0
100 µ s tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
10 1ms
OPERATION IN THIS 10ms 10 STARTING TJ = 25 [o] C
AREA MAY BE
1 LIMITED BY rDS(ON)
SINGLE PULSE DC
T J = MAX RATED STARTING TJ = 150 [o] C
T C = 25 [o] C
0.1 1
1 10 100 300 0.001 0.01 0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
50 50
PULSE DURATION = 80 µ s VGS = 10V
DUTY CYCLE = 0.5% MAX
40 V DD = 15V 40 PULSE DURATION = 80 µ s VGS = 7V
DUTY CYCLE = 0.5% MAX
TC = 25 [o] C
30 30
TJ = 175 [o] C VGS = 6V
20 20
TJ = 25 [o] C TJ = -55 [o] C
VGS = 5V
10 10
0 0
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0 1 2 3 4 5
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
90 3.0
PULSE DURATION = 80DUTY CYCLE = 0.5% MAX µ s PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
2.5
80
VGS = 6V 2.0
70
1.5
60 VGS = 10V
1.0
VGS = 10V, ID = 21A
50 0.5
0 5 10 15 20 25 -80 -40 0 40 80 120 160 200
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature
, DRAIN CURRENT (A)
ID , AVALANCHE CURRENT (A)IAS
, DRAIN CURRENT (A) , DRAIN CURRENT (A)
ID ID
) Ω
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
DRAIN TO SOURCE ON RESISTANCE (m
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FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [426 x 358] intentionally omitted <==** **----- Start of picture text -----**
1.2 1.2
VGS = VDS, ID = 250 µ A ID = 250 µ A
1.0
1.1
0.8
1.0
0.6
0.4 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
2000 10
VDD = 75V
1000
CISS = CGS + CGD 8
COSS ≅ CDS + CGD
6
100 C RSS = C GD
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 21A
VGS = 0V, f = 1MHz ID = 7A
10 0
0.1 1 10 150 0 5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
NORMALIZED GATE
THRESHOLD VOLTAGE BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
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**Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source Junction Temperature Breakdown Voltage vs Junction Temperature** **Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Currents** FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation ## **Test Circuits and Waveforms** **==> picture [421 x 139] intentionally omitted <==** **----- Start of picture text -----**
VDS BVDSS
tP
L VDS
IAS
VARY tP TO OBTAIN + VDD
REQUIRED PEAK IAS RG VDD
VGS -
DUT
tP
0V IAS 0
0.01 Ω
tAV
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**Figure 15. Unclamped Energy Test Circuit** **Figure 16. Unclamped Energy Waveforms** **==> picture [184 x 133] intentionally omitted <==** **----- Start of picture text -----**
VDS
L
VGS +
VDD
-
DUT
Ig(REF)
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**==> picture [197 x 139] intentionally omitted <==** **----- Start of picture text -----**
VDD Qg(TOT)
VDS
VGS = 10V
VGS
VGS = 2V
0 Qgs2
Qg(TH)
Qgs Qgd
Ig(REF)
0
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**Figure 17. Gate Charge Test Circuit** **Figure 18. Gate Charge Waveforms** **==> picture [420 x 141] intentionally omitted <==** **----- Start of picture text -----**
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
VDD 10% 10%
- 0
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 0 10%
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**Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms** FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation ## _**Thermal Resistance vs. Mounting Pad Area**_ The max imum r ated j unction t emperature, T JM, an d t he thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. T herefore t he a pplication’s amb ient temperature, T A ([o] C), and thermal resistance R θJA ([o] C/W) must be reviewed to ensure t hat T JM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. **==> picture [193 x 23] intentionally omitted <==** In us ing su rface mount de vices suc h as t he TO-252 package, the environment in which it is applied will have a significant in fluence o n t he p art’s cur rent and max imum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. **==> picture [206 x 161] intentionally omitted <==** **----- Start of picture text -----**
125
R θ JA = 33.32+ 23.84/(0.268+Area) EQ.2
100 R θ JA = 33.32+ 154/(1.73+Area) EQ.3
75
50
25
0.01 0.1 1 10
(0.0645) (0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
oC/W)(RJA θ
**----- End of picture text -----**
**Figure 21. Thermal Resistance vs Mounting Pad Area** 2. The number of copper layers and t he thickness of t he board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. F or no n s teady st ate ap plications, t he pu lse w idth, t he duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild p rovides t hermal information to as sist t he designer’s preliminary ap plication ev aluation. F igure 21 defines t he R θJA f or t he de vice as a f unction of t he t op copper ( component si de) ar ea. T his is f or a h orizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction t emperature o r p ower di ssipation. P ulse applications ca n be ev aluated us ing t he F airchild device Spice t hermal model or m anually u tilizing t he no rmalized maximum transient thermal impedance curve. Thermal resistances co rresponding to ot her co pper areas can be obtained f rom F igure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. **==> picture [197 x 71] intentionally omitted <==** FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation ## _**PSPICE Electrical Model**_ .SUBCKT FDD2582 2 1 3 ; rev July 2002 Ca 12 8 4e-10 Cb 15 14 4.6e-10 Cin 6 8 1.24e-9 **==> picture [319 x 257] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
515 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE1 9RGATE20+ 1822 - 6 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 160.4 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4.88e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.24e-9 RLgate 1 9 48.8 RLdrain 2 5 10 RLsource 3 7 22.4 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 37e-3 Rgate 9 20 1.8 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 11.9e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*42),2.5))} .MODEL DbodyMOD D (IS=2.3E-12 RS=5.3e-3 TRS1=2.2e-3 TRS2=4.5e-7 + CJO=8.8e-10 M=0.64 TT=3.8e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.4 TRS1=1.4e-3 TRS2=-5e-5) .MODEL DplcapMOD D (CJO=2.75e-10 IS=1.0e-30 N=10 M=0.67) .MODEL MmedMOD NMOS (VTO=3.76 KP=2.7 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.64) .MODEL MstroMOD NMOS (VTO=4.25 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=3.2 KP=0.068 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16.4 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1.1e-8) .MODEL RdrainMOD RES (TC1=1.0e-2 TC2=2.6e-5) .MODEL RSLCMOD RES (TC1=2.7e-3 TC2=2.0e-6) .MODEL RsourceMOD RES (TC1=1.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-3.9e-3 TC2=-1.7e-5) .MODEL RvtempMOD RES (TC1=-3.7e-3 TC2=1.9e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-2.0) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-5.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.4) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation ## _**SABER Electrical Model**_ REV July 2002 ttemplate FDD2582 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.3e-12,rs=5.3e-3,trs1=2.2e-3,trs2=4.5e-7,cjo=8.8e-10,m=0.64,tt=3.8e-8,xti=4.2) dp..model dbreakmod = (rs=0.4,trs1=1.4e-3,trs2=-5.0e-5) dp..model dplcapmod = (cjo=2.75e-10,isl=10.0e-30,nl=10,m=0.67) m..model mmedmod = (type=_n,vto=3.76,kp=2.7,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.25,kp=30,is=1e-30, tox=1) **==> picture [428 x 272] intentionally omitted <==** **----- Start of picture text -----**
m..model mweakmod = (type=_n,vto=3.2,kp=0.068,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-2.0)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-5.0) DPLCAP 5 LDRAIN DRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.3) 2
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.4) 10
c.ca n12 n8 = 4e-10 RSLC1 RLDRAIN
c.cb n15 n14 = 4.6e-10 51
c.cin n6 n8 = 1.24e-9 RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymoddp.dbreak n5 n11 = model=dbreakmod - 50 DBREAK
dp.dplcap n10 n5 = model=dplcapmod ESG + 68 EVTHRES RDRAIN16 11 DBODY
spe.ebreak n11 n7 n17 n18 = 160.4spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 GATE1 RLGATELGATE 9RGATE20+EVTEMP1822 - 6 + 198 CIN- MSTRO21 8 MMED MWEAKEBREAK+-1718 7 LSOURCE SOURCE3
i.it n8 n17 = 1 RSOURCE
RLSOURCE
l.lgate n1 n9 = 4.88e-9l.ldrain n2 n5 = 1.0e-9 12S1A13 14S2A 15 17 RBREAK 18
8 13
l.lsource n3 n7 = 2.24e-9
S1B S2B RVTEMP
res.rlgate n1 n9 = 48.8res.rldrain n2 n5 = 10 CA 13+ CB+ 14 IT -19
res.rlsource n3 n7 = 22.4 EGS 68 EDS 58 + VBAT
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u - - 8 22
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u RVTHRES
**----- End of picture text -----**
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1.1e-8 res.rdrain n50 n16 = 37e-3, tc1=1.0e-2,tc2=2.6e-5 res.rgate n9 n20 = 1.8 res.rslc1 n5 n51 = 1.0e-6, tc1=2.7e-3,tc2=2.0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 11.9e-3, tc1=1.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-3.9e-3,tc2=-1.7e-5 res.rvtemp n18 n19 = 1, tc1=-3.7e-3,tc2=1.9e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/42))** 2.5)) } } FDD2582 Rev. 1.2 ©2002 Fairchild Semiconductor Corporation |**_SPICE Thermal Model_**
REV 19 July 2002
FDD2582
CTHERM1 TH 6 1.6e-3
CTHERM2 6 5 4.5e-3
CTHERM3 5 4 5.0e-3
CTHERM4 4 3 8.0e-3
CTHERM5 3 2 8.2e-3
CTHERM6 2 TL 4.7e-2
RTHERM1 TH 6 3.3e-2
RTHERM2 6 5 7.9e-2
RTHERM3 5 4 9.5e-2
RTHERM4 4 3 1.4e-1
RTHERM5 3 2 2.9e-1
RTHERM6 2 TL 6.7e-1
**_SABER Thermal Model_**
SABER thermal model FDD2582
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1.6e-3
ctherm.ctherm2 6 5 =4.5e-3
ctherm.ctherm3 5 4 =5.0e-3
ctherm.ctherm4 4 3 =8.0e-3
ctherm.ctherm5 3 2 =8.2e-3
ctherm.ctherm6 2 tl =4.7e-2
rrtherm.rtherm1 th 6 =3.3e-2
rtherm.rtherm2 6 5 =7.9e-2
rtherm.rtherm3 5 4 =9.5e-2
rtherm.rtherm4 4 3 =1.4e-1
rtherm.rtherm5 3 2 =2.9e-1
rtherm.rtherm6 2 tl =6.7e-1
}
**RTHERM4**
**RTHERM6**
**RTHERM5**
**RTHERM3**
**RTHERM2**
**RTHERM1**|**CTHERM4**
**CTHERM6**
**CTHERM5**
**CTHERM3**
**CTHERM2**
**CTHERM1**
**tl**
**2**
**3**
**4**
**5**
**6**
**th**
**JUNCTION**
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