# Power MOSFET, N Channel, 150 V, 29 A, 0.045 ohm, TO-252AA, Surface Mount ![Product image](https://novapart.co/image/farnell:3003965/) **URL**: https://novapart.co/products/FDD2572-F085/power-mosfet-n-channel-150-v-29-a-0045-ohm-to **SKU**: FDD2572-F085 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.8790 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | PowerTrench FDD | | Qualification | AEC-Q101 | | Power Dissipation | 135W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 135W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.045ohm | | Transistor Case Style | TO-252AA | | Drain Source Voltage Vds | 150V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 29A | | Drain Source On State Resistance | 0.045ohm | | Automotive Qualification Standard | AEC-Q101 | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:3003965/) ## **- FDD2572 F085** **==> picture [434 x 538] intentionally omitted <==** **----- Start of picture text -----**
N-Channel PowerTrench [®] MOSFET
150V, 29A, 54m Ω
Features Applications
• rDS(ON) = 45mΩ (Typ.), VGS = 10V, ID = 9A • DC/DC converters and Off-Line UPS
• Qg(tot) = 26nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Low QRR Body Diode • Primary Switch for 24V and 48V Systems
• UIS Capability (Single Pulse and Repetitive Pulse) • High Voltage Synchronous Rectifier
poHs
•• RoHS CompliantQualified to AEC Q101 sywh c4,“ • Direct Injection / Diesel Injection Systems
c • 42V Automotive Load Control
Formerly developmental type 82860
>
2 • Electronic Valve Train Systems
y
DRAIN D
(FLANGE)
GATE
G
SOURCE
TO-252AA
FDD SERIES
S
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 150 V
VGS Gate to Source Voltage ±20 V
Drain Current
Continuous (TC = 25 [o] C, VGS = 10V) 29 A
ID Continuous (TC = 100 [o] C, VGS = 10V) 20 A
Continuous (Tamb = 25 [o] C, VGS = 10V, RθJA = 52 [o] C/W) 4
Pulsed Figure 4 A
EAS Single Pulse Avalanche Energy (Note 1) 36 mJ
Power dissipation 135 W
PD Derate above 25 [o] C 0.9 W/ [o] C
TJ, TSTG Operating and Storage Temperature -55 to 175 oC
Thermal Characteristics
RθJC Thermal Resistance Junction to Case TO-252 1.11 oC/W
RθJA Thermal Resistance Junction to Ambient TO-252 100 oC/W
RθJA Thermal Resistance Junction to Ambient TO-252, 1in [2] copper pad area 52 oC/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
All ON Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
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©2008 Semiconductor Components Industries, LLC. September-2017, Rev.1 **==> picture [7 x 6] intentionally omitted <==** **----- Start of picture text -----**
1
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Publication Order Number: FDD2572-F085/D ## **Package Marking and Ordering Information** |**Device Marking**|**Device Marking**|**Device**|**Package**|**Package**|**Reel Size**|**Reel Size**|**Tape Width**|**Tape Width**|**Quantity**|**Quantity**| |---|---|---|---|---|---|---|---|---|---|---| |FDD2572||FDD2572-F085|TO-252AA||330mm||16mm||2500 units|| |**Electrical Characteristics**TC= 25°C unless otherwise noted||||||||||| |**Symbol**|**Parameter**|||**Test Conditions**|||**Min**|**Typ**|**Max**|**Units**| |**Off Characteristics**||||||||||| |BVDSS|Drain to Source Breakdown Voltage|||ID= 250µA, VGS||= 0V|150|-|-|V| |IDSS|Zero Gate Voltage Drain Current|||VDS= 120V
VGS= 0V|||-|-|1|µA| |||||||TC= 150o|-|-|250|| |IGSS|Gate to Source Leakage Current|||VGS=±20V|||-|-|±100|nA| |**On Characteristics**||||||||||| |VGS(TH)|Gate to Source Threshold Voltage|||VGS= VDS, ID= 250µA|||2|-|4|V| |rDS(ON)|Drain to Source On Resistance|||ID=9A, VGS=10V|||-|0.045|0.054|Ω| |||||ID= 4A, VGS= 6V,|||-|0.050|0.075|| |||||ID=9A, VGS=10V, TC=175oC|||-|0.126|0.146|| |**Dynamic Characteristics**||||||||||| |CISS|Input Capacitance|||VDS= 25V, VGS= 0V,
f = 1MHz|||-|1770|-|pF| |COSS|Output Capacitance||||||-|183|-|pF| |CRSS|Reverse Transfer Capacitance||||||-|40|-|pF| |Qg(TOT)|Total Gate Charge at 10V|||VGS= 0V to 10V|||-|26|34|nC| |Qg(TH)|Threshold Gate Charge|||VGS= 0V to 2V|||-|3.3|4.3|nC| |Qgs|Gate to Source Gate Charge||||||-|8|-|nC| |Qgs2|Gate Charge Threshold to Plateau||||||-|5|-|nC| |Qgd|Gate to Drain “Miller” Charge||||||-|6|-|nC| |**Resistive Switching Characteristics**(VGS=||||10V)||||||| |tON|Turn-On Time|||VDD= 75V, ID= 9A
VGS= 10V, RGS= 11.0Ω|||-|-|36|ns| |td(ON)|Turn-On DelayTime||||||-|11|-|ns| |tr|Rise Time||||||-|14|-|ns| |td(OFF)|Turn-Off DelayTime||||||-|31|-|ns| |tf|Fall Time||||||-|14|-|ns| |tOFF|Turn-Off Time||||||-|-|66|ns| |**Drain-Source Diode Characteristics**||||||||||| |VSD|Source to Drain Diode Voltage|||ISD= 9A|||-|-|1.25|V| |||||ISD= 4A|||-|-|1.0|V| |trr|Reverse Recovery Time|||ISD= 9A, dISD/dt =100A/µs|||-|-|74|ns| |QRR|Reverse Recovered Charge|||ISD= 9A, dISD/dt =100A/µs|||-|-|169|nC| **Notes:** **1:** Starting TJ = 25°C, L = 0.2mH, IAS = 19A. www.onsemi.com 2 ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [425 x 572] intentionally omitted <==** **----- Start of picture text -----**
1.2 40
35 VGS = 10V
1.0
30
0.8
25
0.6 20
0.4 15
10
0.2
5
0
0
0 25 50 75 100 125 150 175
25 50 75 100 125 150 175
TC , CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature Case Temperature
2.0
1.0 DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
SINGLE PULSE t1
t 2
NOTES:
DUTY FACTOR: D = t 1 /t 2
PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TC = 25 [o] C
FOR TEMPERATURES
TRANSCONDUCTANCE ABOVE 25 [o] C DERATE PEAK
MAY LIMIT CURRENT
IN THIS REGION CURRENT AS FOLLOWS:
I = I25 175 - TC
150
100
VGS = 10V
20
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJC θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
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**Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs Ambient Temperature Case Temperature** www.onsemi.com 3 ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [430 x 588] intentionally omitted <==** **----- Start of picture text -----**
1000 100
10 µ s STARTING TJ = 25 [o] C
100 100 µ s
10
1ms
10
OPERATION IN THIS
LIMITED BY rAREA MAY BE DS(ON) 10ms 1 STARTING TJ = 150 [o] C
1
If R = 0
SINGLE PULSE DC tAV = (L)(IAS)/(1.3 * RATED BVDSS - VDD)
TJ = MAX RATED If R ≠ 0
T C = 25 [o] C tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0.1 0.1
1 10 100 200 0.001 0.01 0.1 1
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to ON Semiconductor Application ON Semiconductor ApplicationApplication Notes AN7514 and
Figure 6. Unclamped Inductive Switching
Capability
60 60
DUTY CYCLE = 0.5% MAXPULSE DURATION = 80 µ s TC = 25 [o] C VGS = 10V
50 V DD = 15V 50
40 40
VGS = 7V
TJ = 175 [o] C
30 30 VGS = 6V
20 T J = 25 [o] C 20 V GS = 5V
TJ = -55 [o] C
10 10
PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
0 0
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0 1 2 3 4 5
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
60 3.0
PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
2.5
55 VGS = 6V
2.0
50 1.5
VGS = 10V
1.0
45
0.5
VGS = 10V, ID =9A
40
0
0 10 20 30 -80 -40 0 40 80 120 160 200
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature
, DRAIN CURRENT (A)
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)ID , DRAIN CURRENT (A)ID
) Ω
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE (m NORMALIZED DRAIN TO SOURCE
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NOTE: Refer to ON Semiconductor Application ON Semiconductor ApplicationApplication Notes AN7514 and AN7515 **Figure 6. Unclamped Inductive Switching Capability** www.onsemi.com 4 ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [426 x 358] intentionally omitted <==** **----- Start of picture text -----**
1.4 1.2
VGS = VDS, ID = 250 µ A ID = 250 µ A
1.2
1.1
1.0
0.8
1.0
0.6
0.4 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
1000 10
VDD = 75V
1000 C ISS = C GS + C GD 8
C OSS ≅ C DS + C GD
6
CRSS = CGD
100 4
WAVEFORMS IN
2
DESCENDING ORDER:
VGS = 0V, f = 1MHz IIDD = 9A = 4A
10 0
0.1 1 10 150 0 5 10 15 20 25 30
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
NORMALIZED GATE
THRESHOLD VOLTAGE BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
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**Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature** **Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Currents** www.onsemi.com 5 ## **Test Circuits and Waveforms** **==> picture [421 x 139] intentionally omitted <==** **----- Start of picture text -----**
VDS BVDSS
tP
L VDS
IAS
VARY tP TO OBTAIN + VDD
REQUIRED PEAK IAS RG VDD
VGS -
DUT
tP
0V IAS 0
0.01 Ω
tAV
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**Figure 15. Unclamped Energy Test Circuit** **Figure 16. Unclamped Energy Waveforms** **==> picture [184 x 166] intentionally omitted <==** **----- Start of picture text -----**
VDS
L
VGS +
VDD
-
DUT
Ig(REF)
Figure 17. Gate Charge Test Circuit
**----- End of picture text -----**
**==> picture [197 x 139] intentionally omitted <==** **----- Start of picture text -----**
VDD Qg(TOT)
VDS
VGS = 10V
VGS
VGS = 2V
0 Qgs2
Qg(TH)
Qgs Qgd
Ig(REF)
0
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**Figure 18. Gate Charge Waveforms** **==> picture [420 x 141] intentionally omitted <==** **----- Start of picture text -----**
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
VDD 10% 10%
-
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
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**Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms** www.onsemi.com 6 **==> picture [470 x 650] intentionally omitted <==** **----- Start of picture text -----**
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the 125
thermal resistance of the heat dissipating path determinesthe maximum allowable device power dissipation, PDM, in an R θ JA = 33.32+ 23.84/(0.268+Area) EQ.2
application. Therefore the application’s ambient 100 R θ JA = 33.32+ 154/(1.73+Area) EQ.3
temperature, TA ( [o] C), and thermal resistance RθJA ( [o] C/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part. 75
PDM = ----------------------------- ( TJM – TA ) (EQ. 1) 50
R θ JA
In using surface mount devices such as the TO-252 25
package, the environment in which it is applied will have a 0.01 0.1 1 10
significant influence on the part’s current and maximum (0.0645) (0.645) (6.45) (64.5)
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors: AREA, TOP COPPER AREA in [2] (cm [2] )
Figure 21. Thermal Resistance vs Mounting
1. Mounting pad area onto which the device is attached and Pad Area
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
ON Semiconductor provides thermal information to
assist the designer’s preliminary application evaluation.
Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds of
steady state power with no air flow. This graph provides the
necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the ON
Semiconductor device Spice thermal model or manually
utilizing the normalized maximum transient thermal
impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area
defined in inches square and equation 3 is for area in
centimeter square. The area, in square inches or square
centimeters is the top copper area including the gate and
source pads.
R θ JA = 33.32 + ----------------------------------- ( 0.26823.84+ Area - ) (EQ. 2)
Area in Inches Squared
R θ JA = 33.32 + -------------------------------- ( 1.73154+ Area - ) (EQ. 3)
Area in Centimeters Squared
FDD2572
-
oC/W)(RJA θ
F085 N-Channel PowerTrench
®
MOSFET
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www.onsemi.com 7 ## _**PSPICE Electrical Model**_ .SUBCKT FDD2572 2 1 3 ; rev April 2002 CA 12 8 5.5e-10 Cb 15 14 7.4e-10 Cin 6 8 1.7e-9 **==> picture [319 x 257] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
515 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE1 9RGATE20+ 1822 - MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 160 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 1.21e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 4.45e-9 RLgate 1 9 12.1 RLdrain 2 5 10 RLsource 3 7 44.5 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 35e-3 Rgate 9 20 1.6 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 3.0e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*52),3))} .MODEL DbodyMOD D (IS=6.0E-11 N=1.14 RS=3.9e-3 TRS1=3.5e-3 TRS2=3.0e-6 + CJO=1.1e-9 M=0.63 TT=6.2e-8 XTI=4.5) .MODEL DbreakMOD D (RS=10 TRS1=5.0e-3 TRS2=-5.0e-6) .MODEL DplcapMOD D (CJO=3.5e-10 IS=1.0e-30 N=10 M=0.65) .MODEL MmedMOD NMOS (VTO=3.55 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.6) .MODEL MstroMOD NMOS (VTO=4.0 KP=25 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.95 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=16 RS=0.1) .MODEL RbreakMOD RES (TC1=1.15e-3 TC2=-9.5e-7) .MODEL RdrainMOD RES (TC1=9.0e-3 TC2=2.5e-5) .MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.5e-6) .MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6) .MODEL RvthresMOD RES (TC1=-4.1e-3 TC2=-1.0e-5) .MODEL RvtempMOD RES (TC1=-4.0e-3 TC2=1.0e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 8 ## _**SABER Electrical Model**_ REV April 2002 ttemplate FDD2572 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=6.0e-11,nl=1.14,rs=3.9e-3,trs1=3.5e-3,trs2=3.0e-6,cjo=1.1e-9,m=0.63,tt=6.2e-8,xti=4.5) dp..model dbreakmod = (rs=10,trs1=5.0e-3,trs2=-5.0e-6) dp..model dplcapmod = (cjo=3.5e-10,isl=10.0e-30,nl=10,m=0.65) m..model mmedmod = (type=_n,vto=3.55,kp=3,is=1e-40, tox=1) m..model mstrongmod = (type=_n,vto=4.0,kp=25,is=1e-30, tox=1) **==> picture [433 x 258] intentionally omitted <==** **----- Start of picture text -----**
m..model mweakmod = (type=_n,vto=2.95,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5) DPLCAP 5 DRAIN2
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0) 10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3) RSLC1 RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5) 51
c.ca n12 n8 = 5.5e-10 RSLC2
c.cb n15 n14 = 7.4e-10 ISCL
c.cin n6 n8 = 1.7e-9
- 50 DBREAK
dp.dbody n7 n5 = model=dbodymoddp.dbreak n5 n11 = model=dbreakmod ESG + 68 EVTHRES RDRAIN16 11 DBODY
dp.dplcap n10 n5 = model=dplcapmod LGATE EVTEMP + 198 - 21 MWEAK
spe.ebreak n11 n7 n17 n18 = 160spe.eds n14 n8 n5 n8 = 1 GATE1 9RGATE20+ 1822 - 6 MMED EBREAK+
spe.egs n13 n8 n6 n8 = 1 RLGATE MSTRO 17
spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1 CIN 8 -18 7 LSOURCE SOURCE3
spe.evtemp n20 n6 n18 n22 = 1 RSOURCE
RLSOURCE
i.it n8 n17 = 1 S1A S2A
12 13 14 15 17 RBREAK 18
l.lgate n1 n9 = 1.21e-9 8 13
l.ldrain n2 n5 = 1.0e-9 S1B S2B RVTEMP
l.lsource n3 n7 = 4.45e-9 CA 13+ CB+ 14 IT -19
res.rlgate n1 n9 = 12.1res.rldrain n2 n5 = 10 EGS 68 EDS 58 + VBAT
res.rlsource n3 n7 = 44.5 - - 8
22
RVTHRES
**----- End of picture text -----**
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.15e-3,tc2=-9.5e-7 res.rdrain n50 n16 = 35e-3, tc1=9.0e-3,tc2=2.5e-5 res.rgate n9 n20 = 1.6 res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=2.5e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 3.0e-3, tc1=4.0e-3,tc2=1.0e-6 res.rvthres n22 n8 = 1, tc1=-4.1e-3,tc2=-1.0e-5 res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=1.0e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/52))** 3))} } www.onsemi.com 9 |**_SPICE Thermal Model_**
REV 26 April 2002
FDD2572
CTHERM1 TH 6 3.8e-3
CTHERM2 6 5 4.0e-3
CTHERM3 5 4 4.2e-3
CTHERM4 4 3 4.3e-3
CTHERM5 3 2 8.5e-3
CTHERM6 2 TL 3.0e-2
RTHERM1 TH 6 5.5e-4
RTHERM2 6 5 5.0e-3
RTHERM3 5 4 4.5e-2
RTHERM4 4 3 10.5e-2
RTHERM5 3 2 3.7e-1
RTHERM6 2 TL 3.8e-1
**_SABER Thermal Model_**
SABER thermal model FDD2572
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.8e-3
ctherm.ctherm2 6 5 =4.0e-3
ctherm.ctherm3 5 4 =4.2e-3
ctherm.ctherm4 4 3 =4.3e-3
ctherm.ctherm5 3 2 =8.5e-3
ctherm.ctherm6 2 tl =3.0e-2
rtherm.rtherm1 th 6 =5.5e-4
rtherm.rtherm2 6 5 =5.0e-3
rtherm.rtherm3 5 4 =4.5e-2
rtherm.rtherm4 4 3 =10.5e-2
rtherm.rtherm5 3 2 =3.7e-1
rtherm.rtherm6 2 tl =3.8e-1
}
**RTHERM4**
**RTHERM6**
**RTHERM5**
**RTHERM3**
**RTHERM2**
**RTHERM1**|**CTHERM4**
**CTHERM6**
**CTHERM5**
**CTHERM3**
**CTHERM2**
**CTHERM1**
**tl**
**2**
**3**
**4**
**5**
**6**
**th**
**JUNCTION**
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