# Power MOSFET, N Channel, 60 V, 50 A, 0.0135 ohm, TO-252AA, Surface Mount ![Product image](https://novapart.co/image/farnell:1700666/) **URL**: https://novapart.co/products/FDD13AN06A0/power-mosfet-n-channel-60-v-50-a-00135-ohm-to **SKU**: FDD13AN06A0 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.7170 **Stock**: 100+ **Lead Time**: 148 days (indicative) ## Description Transistor Polarity:N Channel; Continuous Drain Current Id:50A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.0115ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:4V; Power D ## Specifications | Parameter | Value | |---|---| | Msl | MSL 1 - Unlimited | | Svhc | Lead (25-Jun-2025) | | No. Of Pins | 3Pins | | Channel Type | N Channel | | Product Range | - | | Qualification | - | | Power Dissipation | 115W | | Transistor Mounting | Surface Mount | | Rds(On) Test Voltage | 10V | | Transistor Case Style | TO-252AA | | Drain Source Voltage Vds | 60V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 50A | | Drain Source On State Resistance | 0.0135ohm | | Gate Source Threshold Voltage Max | 4V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:1700666/) ## **Is Now Part of** ## **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor product management systems do not have the ability to manage part nomenclature that utilizes an underscore (_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please email any questions regarding the system integration to Fairchild_questions@onsemi.com. ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. **==> picture [75 x 9] intentionally omitted <==** **----- Start of picture text -----**
November 2013
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## **FDD13AN06A0** ## **N-Channel PowerTrench[®] MOSFET 60 V, 50 A, 13 m** Ω ## **Features** - RDS(on) = 11.5 m Ω ( Typ.) @ VGS = 10 V, ID = 50 A - QG(tot) = 22 nC ( Typ.) @ VGS = 10 V - Low Miller Charge - Low Qrr Body Diode - UIS Capability (Single Pulse and Repetitive Pulse) ## **Applications** - Consumer Appliances - LED TV - Synchronous Rectification - Battery Protection Circuit - Motor Drives and Uninterruptible Power Supplies Formerly developmental type 82555 **==> picture [218 x 96] intentionally omitted <==** **----- Start of picture text -----**
D
D
G
G
S D-PAK
S
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## **MOSFET Maximum Ratings** TC = 25°C unless otherwise noted |**Symbol**|**Parameter**|**Parameter**|**FDD13AN06A0**|**FDD13AN06A0**|**FDD13AN06A0**|**Unit**| |---|---|---|---|---|---|---| |VDSS|Drain to Source Voltage|||60||V| |VGS|Gate to Source Voltage|||±20||V| ||Drain Current|||||| |ID|Continuous(TC< 80oC, VGS= 10V)
Continuous(TA= 25oC, VGS= 10V, RθJA= 52oC/W)|||50
9.9||A
A| ||Pulsed|||Figure 4|ure 4|A| |EAS|Single Pulse Avalanche Energy (Note 1|Note 1)||56||mJ| |PD|Power dissipation
Derate above 25oC|||115
0.77||W
oC
W/| |TJ, TSTG|Operatingand Storage Temperature|||-55 to 175||oC| |**Thermal Characteristics**|**Thermal Characteristics**|||||| |RθJC|Thermal Resistance Junction to Case, Max.|Thermal Resistance Junction to Case, Max.D-PAK|||1.3|oC/W| |Rθ|Thermal Resistance Junction to Ambient, Max.D-PAK||||100|oC/W| |RθJA|Thermal Resistance Junction to Ambient, Max.D-PAK, 1in2copperpad area||||52|oC/W| www.fairchildsemi.com ©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 **1** ## **Package Marking and Ordering Information** |**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Unit**
**Electrical Characteristics**TC= 25°C unless otherwise noted
**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Device Marking**
**Device**
**Package**
**Reel Size**
**Tape Width**
**Quantity**
FDD13AN06A0
FDD13AN06A0
D-PAK
330 mm
16 mm
2500 units
BVDSS
Drain to Source Breakdown Voltage
ID= 250µA, VGS= 0V
60
-
-
V
IDSS
Zero Gate Voltage Drain Current
VDS= 50V
-
-
1
µA
VGS= 0V
-
TC= 150oC
-
250
IGSS
Gate to Source Leakage Current
VGS=±20V
-
-
±100
nA
VGS(TH)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250µA
2
-
4
V
rDS(ON)
Drain to Source On Resistance
ID= 50A, VGS= 10V
-
0.0115
0.0135
Ω
ID= 25A, VGS= 6V
-
0.022
0.034
ID= 50A, VGS= 10V,
TJ= 175oC
-
0.026
0.030
CISS
Input Capacitance
VDS= 25V, VGS= 0V,
f = 1MHz
-
1350
-
pF
COSS
Output Capacitance
-
260
-
pF
CRSS
Reverse Transfer Capacitance
-
90
-
pF
Qg(TOT)
Total Gate Charge at 10V
VGS= 0V to 10V
22
29
nC
~~SSS~~
~~i~~
~~oe~~|**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Unit**
**Electrical Characteristics**TC= 25°C unless otherwise noted
**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Device Marking**
**Device**
**Package**
**Reel Size**
**Tape Width**
**Quantity**
FDD13AN06A0
FDD13AN06A0
D-PAK
330 mm
16 mm
2500 units
BVDSS
Drain to Source Breakdown Voltage
ID= 250µA, VGS= 0V
60
-
-
V
IDSS
Zero Gate Voltage Drain Current
VDS= 50V
-
-
1
µA
VGS= 0V
-
TC= 150oC
-
250
IGSS
Gate to Source Leakage Current
VGS=±20V
-
-
±100
nA
VGS(TH)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250µA
2
-
4
V
rDS(ON)
Drain to Source On Resistance
ID= 50A, VGS= 10V
-
0.0115
0.0135
Ω
ID= 25A, VGS= 6V
-
0.022
0.034
ID= 50A, VGS= 10V,
TJ= 175oC
-
0.026
0.030
CISS
Input Capacitance
VDS= 25V, VGS= 0V,
f = 1MHz
-
1350
-
pF
COSS
Output Capacitance
-
260
-
pF
CRSS
Reverse Transfer Capacitance
-
90
-
pF
Qg(TOT)
Total Gate Charge at 10V
VGS= 0V to 10V
22
29
nC
~~SSS~~
~~i~~
~~oe~~|**Symbol**
**Parameter**
**Test Conditions**
**Min**
**Typ**
**Max**
**Unit**
**Electrical Characteristics**TC= 25°C unless otherwise noted
**Off Characteristics**
**On Characteristics**
**Dynamic Characteristics**
**Device Marking**
**Device**
**Package**
**Reel Size**
**Tape Width**
**Quantity**
FDD13AN06A0
FDD13AN06A0
D-PAK
330 mm
16 mm
2500 units
BVDSS
Drain to Source Breakdown Voltage
ID= 250µA, VGS= 0V
60
-
-
V
IDSS
Zero Gate Voltage Drain Current
VDS= 50V
-
-
1
µA
VGS= 0V
-
TC= 150oC
-
250
IGSS
Gate to Source Leakage Current
VGS=±20V
-
-
±100
nA
VGS(TH)
Gate to Source Threshold Voltage
VGS= VDS, ID= 250µA
2
-
4
V
rDS(ON)
Drain to Source On Resistance
ID= 50A, VGS= 10V
-
0.0115
0.0135
Ω
ID= 25A, VGS= 6V
-
0.022
0.034
ID= 50A, VGS= 10V,
TJ= 175oC
-
0.026
0.030
CISS
Input Capacitance
VDS= 25V, VGS= 0V,
f = 1MHz
-
1350
-
pF
COSS
Output Capacitance
-
260
-
pF
CRSS
Reverse Transfer Capacitance
-
90
-
pF
Qg(TOT)
Total Gate Charge at 10V
VGS= 0V to 10V
22
29
nC
~~SSS~~
~~i~~
~~oe~~| |---|---|---| |Qg(TH)
Threshold Gate Charge|VDD= 30V
VGS= 0V to 2V
-
2.6
3.4|nC| |Qgs
Gate to Source Gate Charge|ID= 50A
-
8.2
-|nC| |Qgs2
Gate Charge Threshold to Plateau|Ig= 1.0mA
-
5.6
-|nC| |Qgd
Gate to Drain “Miller” Charge|-
6.4
-|nC| |**Switching Characteristics**(VGS= 10V)||| |**Drain-Source Diode Characteristics**
tON
Turn-On Time
VDD= 30V, ID= 50A
VGS= 10V, RGS= 12Ω
-
-
130
ns
td(ON)
Turn-On Delay Time
-
9
-
ns
tr
Rise Time
-
77
-
ns
td(OFF)
Turn-Off Delay Time
-
26
-
ns
tf
Fall Time
-
25
-
ns
tOFF
Turn-Off Time
-
-
77
ns
VSD
Source to Drain Diode Voltage
ISD= 50A
-
-
1.25
V
ISD= 25A
-
-
1.0
V
trr
Reverse RecoveryTime
-
ISD= 50A, dISD/dt = 100A/µs
-
24
ns
QRR
Reverse Recovered Charge
-
ISD= 50A, dISD/dt = 100A/µs
-
15
nC
~~==~~
~~eae~~
~~ee~~||| |**Notes:**||| |**1:** Starting TJ= 25°C, L = 45µH, IAS= 50A.||| ©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 www.fairchildsemi.com **2** ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [429 x 553] intentionally omitted <==** **----- Start of picture text -----**
1.2
80
1.0
CURRENT LIMITED
BY PACKAGE
60
0.8 SSE bee 7
0.6 SUNG EEE) 40 OES _
w oo
0.4
20
0.2
0 ft | ttER 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
a 0.01 Sestiiieeeise aes Sess eesti ete ee
en eI PDM
0.1
eA
t 1
t 2
Se sie a ee nn ad NOTES: DUTY FACTOR: D = t 1 /t 2
Of SINGLE PULSE ete PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01 Zrlll
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
800
SS T C = 25 [o] C oon
Pe | TTT FOR TEMPERATURES |
rst LTT TRANSCONDUCTANCE rT TT oT ETT ABOVE 25 [o] C DERATE PEAK |
MAY LIMIT CURRENT CURRENT AS FOLLOWS:
IN THIS REGION
Cae Cen I = I25 175 - TC |
VGS = 10V 150
mance TAN LETTE = |
100 UISTa LETTE tut
EHH
YT SS te
YT ETLTTE EE ETT eeTT TTT ETT
30 Ee ce en
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJC θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
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Figure 4. Peak Current Capability
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**==> picture [137 x 14] intentionally omitted <==** **----- Start of picture text -----**
©2003 Fairchild Semiconductor Corporation
FDD13AN06A0 Rev. C2
**----- End of picture text -----**
www.fairchildsemi.com **3** ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [429 x 587] intentionally omitted <==** **----- Start of picture text -----**
1000 100 If R = 0
tAV = (L)(I AS )/(1.3*RATED BV DSS - V DD )
10 µ s If R ≠ 0
t AV = (L/R)ln[(I AS *R)/(1.3*RATED BV DSS - V DD ) +1]
100
100 µ s STARTING T J = 25 [o] C
10 OPERATION IN THIS 1ms 10
AREA MAY BE
LIMITED BY rDS(ON) STARTING T J = 150 [o] C
1
SINGLE PULSE 10ms
ee TJ = MAX RATED DC CSS
T C = 25 [o] C
0.1 FESS COME 1 CMAN SU
1 10 100 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
100 100
PULSE DURATION = 80 µ s TC = 25 [o] C VGS = 20V
DUTY CYCLE = 0.5% MAX
80 VDD = 15V 80
VGS = 10V
60 Yn 60 | fr
VGS = 6V
40 |] T J = 175 fo [o] C Jf| 40 |feYYET
TJ = 25 [o] C T J = -55 [o] C PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX
20 20
VGS = 5V
0 eS Gl 0 Zee
3 4 5 7 0 0.5 1.0 1.5 2.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
30 2.5
PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
25 2.0
VGS = 6V
20 1.5
15 —
1.0
VGS = 10V
10 eeee ee VGS = 10V, ID =50A
0 10 20 30 40 50 0.5
-80 -40 0 40 80 120 160 200
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Drain to Source On Resistance vs Drain Figure 10. Normalized Drain to Source On
Current Resistance vs Junction Temperature
, DRAIN CURRENT (A)
ID
, AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)ID , DRAIN CURRENT (A)ID
) Ω
ON RESISTANCE
NORMALIZED DRAIN TO SOURCE
DRAIN TO SOURCE ON RESISTANCE(m
**----- End of picture text -----**
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©2003 Fairchild Semiconductor Corporation
FDD13AN06A0 Rev. C2
**----- End of picture text -----**
**==> picture [5 x 6] intentionally omitted <==** **----- Start of picture text -----**
4
**----- End of picture text -----**
www.fairchildsemi.com **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [434 x 388] intentionally omitted <==** **----- Start of picture text -----**
1.4 1.2
VGS = VDS, ID = 250 µ A ID = 250 µ A
1.2
1.1
1.0
0.8
1.0
0.6
0.4
-80 -40 0 40 80 120 160 200 0.9
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
3000
10
VDD = 30V
EN
8
1000 CISS = CGS + CGD
=e C OSS ≅ C DS + C GD
ee [ |SA 6
es eee, ee
CRSS = CGD 4
WAVEFORMS IN
100 iTa PPAR TH 2 DESCENDING ORDER:
Se) ID = 50A
SS V GS = 0V, f = 1MHz ID = 25A
40 Bo SeP [Teri] tt Tt 0
0.1 1 10 60 0 5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Current
NORMALIZED GATE THRESHOLD VOLTAGE BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 www.fairchildsemi.com **5** ## **Test Circuits and Waveforms** **==> picture [414 x 138] intentionally omitted <==** **----- Start of picture text -----**
VDS
BVDSS
L tP
VDS
VARY tREQUIRED PEAK IP TO OBTAINAS RG + VDD IAS VDD
VGS -
DUT
tP
0V IAS
0.01 Ω 0
tAV
**----- End of picture text -----**
**Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms** **==> picture [420 x 358] intentionally omitted <==** **----- Start of picture text -----**
VDS
VDD Qg(TOT)
L VDS
VGS VGS = 10V
an
VGS +
VDD Qgs2
-
DUT
Ig(REF) VGS = 2V
0
Qg(TH)
Qgs Qgd
Ig(REF)
= 0 2
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
+
VGS
- VDD 0 10% 10%
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
**----- End of picture text -----**
©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 www.fairchildsemi.com **6** ## _**Thermal Resistance vs. Mounting Pad Area**_ The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance RθJA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. _PDM_ = ---------( _TJM_ ------------------– _TA_ - ) (EQ. 1) _R_ θ _JA_ In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. **==> picture [206 x 180] intentionally omitted <==** **----- Start of picture text -----**
125
R θ JA = 33.32+ 23.84/(0.268+Area) EQ.2
10075 —HHIN HEN R θ JA = 33.32+ 154/ i Ml (1.73+Area ii ) EQ.3 |
50
a aa
25 ELAINE LAE Tomint
0.01 0.1 1 10
(0.0645) (0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
Figure 21. Thermal Resistance vs Mounting
Pad Area
oC/W)(RJA θ
**----- End of picture text -----**
2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. **==> picture [197 x 69] intentionally omitted <==** www.fairchildsemi.com ©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 **7** ## _**PSPICE Electrical Model**_ **==> picture [430 x 514] intentionally omitted <==** **----- Start of picture text -----**
.SUBCKT FDD13AN06A0 2 1 3 ; rev August 2002
Ca 12 8 5.1e-10
Cb 15 14 5.8e-10 LDRAIN
Cin 6 8 1.3e-9 DPLCAP 5 DRAIN
2
10
Dbody 7 5 DbodyMOD RLDRAIN
Dbreak 5 11 DbreakMOD 51RSLC1 DBREAK
Dplcap 10 5 DplcapMOD RSLC2
Ebreak 11 7 17 18 65.40 515 ESLC 11
Eds 14 8 5 8 1Egs 13 8 6 8 1Esg 6 10 6 8 1Evthres 6 21 19 8 1Evtemp 20 6 18 22 1 LGATE EVTEMPESG +- 68 EVTHRES+ 198 - 21RDRAIN50 16 EBREAKMWEAK+-1718 DBODY
GATE RGATE + 18 [[] - 6 [ts]
It 8 17 1 1 9 20 22 MMED
RLGATE MSTRO
Lgate 1 9 5.2e-9Ldrain 2 5 1.0e-9 CIN 8 7 LSOURCE SOURCE3
Lsource 3 7 2.14e-9
RSOURCE
RLSOURCE
RLgate 1 9 52 S1A S2A
RLdrain 2 5 10 12 13 14 15 17 RBREAK 18
RLsource 3 7 21.4 8 13
S1B S2B RVTEMP
Mmed 16 6 8 8 MmedMODMstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD CA = EGS13+68 4 EDSCB+ 58 14 IT i +-19VBAT
Rbreak 17 18 RbreakMOD 1 - - 8
Rdrain 50 16 RdrainMOD 3.1e-3 22
Rgate 9 20 3.71 RVTHRES
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*160),6))}
.MODEL DbodyMOD D (IS=1.0E-11 N=1.08 RS=3.5e-3 TRS1=2.2e-3 TRS2=2.5e-9
+ CJO=.9e-9 M=5.1e-1 TT=1e-9 XTI=3.9)
.MODEL DbreakMOD D (RS=1.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=4.1e-10 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.5 KP=6 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.71)
.MODEL MstroMOD NMOS (VTO=4.3 KP=50 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=2.91 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.71e+1 RS=0.1)
.MODEL RbreakMOD RES (TC1=9e-4 TC2=-5e-7)
.MODEL RdrainMOD RES (TC1=1.3e-2 TC2=5.2e-5)
.MODEL RSLCMOD RES (TC1=1.8e-3 TC2=1.7e-5)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.0e-5)
.MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)
+
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.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=.5 VOFF=-1.5) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.fairchildsemi.com ©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 **8** ## _**SABER Electrical Model**_ rev August 2002 template FDD13AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=1.0e-11,nl=1.08,rs=3.5e-3,trs1=2.2e-3,trs2=2.5e-9,cjo=.9e-9,m=5.1e-1,tt=1e-9,xti=3.9) dp..model dbreakmod = (rs=1.5e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.1e-10,isl=10e-30,nl=10,m=0.45) m..model mmedmod = (type=_n,vto=3.5,kp=6,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.3,kp=50,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.91,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5,voff=-2) **DPLCAP 5 LDRAIN DRAIN** sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-5) **2** sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=.5) **10 RLDRAIN** sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=.5,voff=-1.5) **RSLC1** c.ca n12 n8 = 5.1e-10 **51** c.cb n15 n14 = 5.8e-10 **RSLC2** c.cin n6 n8 = 1.3e-9 **ISCL** dp.dbody n7 n5 = model=dbodymod **50 DBREAK** dp.dbreak n5 n11 = model=dbreakmoddp.dplcap n10 n5 = model=dplcapmod **ESG + 68 EVTHRES RDRAIN16 11 DBODY** spe.ebreak n11 n7 n17 n18 = 65.40spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 **GATE1 RLGATELGATE 9RGATE20EVTEMP+ 1822** ~~|~~ **6 + 198 CINMSTRO21 8 MMED MWEAKEBREAK+-1718** ~~[~~ **7 LSOURCE SOURCE3 RSOURCE** i.it n8 n17 = 1 **RLSOURCE S1A S2A** l.lgate n1 n9 = 5.2e-9 **12 138 1413 15 17 RBREAK 18** l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.14e-9 **S1B S2B RVTEMP CA 13 CB 19** res.rlgate n1 n9 = 52 ~~ea~~ **+ + 14** ~~l~~ **IT -** res.rldrain n2 n5 = 10res.rlsource n3 n7 = 21.4 **EGS -68 EDS - 58 8 + VBAT 22** m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u **RVTHRES** m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=-5e-7 res.rdrain n50 n16 = 3.1e-3, tc1=1.3e-2,tc2=5.2e-5 res.rgate n9 n20 = 3.71 res.rslc1 n5 n51 = 1e-6, tc1=1.8e-3,tc2=1.7e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 5.5e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.0e-5 res.rvtemp n18 n19 = 1, tc1=-2.5e-3,tc2=1e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/160))** 6)) }} www.fairchildsemi.com ©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 **9** ## _**SPICE Thermal Model**_ **th JUNCTION** REV 22 August 2002 FDD13AN06A0T CTHERM1 TH 6 9.7e-4 CTHERM2 6 5 6.2e-3 CTHERM3 5 4 4.6e-3 **RTHERM1 CTHERM1** CTHERM4 4 3 4.9e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 4.2e-2 **6** RTHERM1 TH 6 5.24e-2 RTHERM2 6 5 10.08e-2 RTHERM3 5 4 4.28e-1 **RTHERM2 CTHERM2** RTHERM4 4 3 1.8e-1 RTHERM5 3 2 1.9e-1 RTHERM6 2 TL 2.1e-1 **5** _**SABER Thermal Model**_ SABER thermal model FDD13AN06A0T template thermal_model th tl **RTHERM3 CTHERM3** thermal_c th, tl { ctherm.ctherm1 th 6 =9.7e-4 **4** ctherm.ctherm2 6 5 =6.2e-3 ctherm.ctherm3 5 4 =4.6e-3 ctherm.ctherm4 4 3 =4.9e-3 ctherm.ctherm5 3 2 =8e-3 **RTHERM4 CTHERM4** ctherm.ctherm6 2 tl =4.2e-2 rtherm.rtherm1 th 6 =5.24e-2 rtherm.rtherm2 6 5 =10.08e-2 **3** rtherm.rtherm3 5 4 =4.28e-1 rtherm.rtherm4 4 3 =1.8e-1 rtherm.rtherm5 3 2 =1.9e-1 **RTHERM5 CTHERM5** rtherm.rtherm6 2 tl =2.1e-1 } **2 RTHERM6 CTHERM6 tl CASE** ©2003 Fairchild Semiconductor Corporation FDD13AN06A0 Rev. C2 www.fairchildsemi.com **10** **==> picture [37 x 58] intentionally omitted <==** **==> picture [37 x 54] intentionally omitted <==** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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