# Power MOSFET, N Channel, 60 V, 50 A, 0.0094 ohm, TO-252AA, Surface Mount ![Product image](https://novapart.co/image/farnell:1471039RL/) **URL**: https://novapart.co/products/FDD10AN06A0/power-mosfet-n-channel-60-v-50-a-00094-ohm-to **SKU**: FDD10AN06A0 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.6080 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | Channel Type | N Channel | | Power Dissipation | 135W | | Drain Source On State Resistance | 0.0094ohm | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:1471039RL/) ## **Is Now Part of** **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. July 2016 ## **FDD10AN06A0** ## **N-Channel PowerTrench[®] MOSFET** ## **60V, 50A, 10.5m** Ω ## **Features** - RDS(on) = 9.4 mΩ (Typ.) @ VGS = 10 V, ID = 50 A - QG(tot) = 28 nC (Typ.) @ VGS = 10 V - Low Miller Charge - Low Qrr Body Diode - UIS Capability (Single Pulse and Repetitive Pulse) ## **Applications** - Consumer Applications ## **General Description** This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. These MOSFETs feature faster switching and lower gate charge than other MOSFETs with comparable RDS(ON) specifications. The result is a MOSFET that is easy and safer to drive (even at very high frequencies), and DC/DC power supply designs with higher reliability and system efficiency. - LED TV - Synchronous Rectification |**MOSFET Maximum Ratin**|**MOSFET Maximum Ratings **TC= 25°C unless otherwise noted||| |---|---|---|---| |**Symbol**|**Parameter**|**Rating**|**Unit**| |VDSS|Drain to Source Voltage|60|V| |VGS|Gate to Source Voltage|±20|V| |ID|Drain Current
Continuous (TC< 115oC, VGS= 10V)|50|A| ||Continuous (Tamb= 25oC, VGS= 10V, with RθJA= 52oC/W)|11|A| ||Pulsed|Figure 4|A| |EAS|Single Pulse Avalanche Energy (Note 1)|429|mJ| |PD|Power dissipation|135|W| ||Derate above 25oC|0.9|W/oC| |TJ, TSTG|Operating and Storage Temperature|-55 to 175|oC| 1 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **Package Marking and Ordering Information** |**Device Marking**|**Device Marking**|**Device**|**Package**|**Package**|**Reel Size**|**Reel Size**|**Tape Width**|**Tape Width**|**Tape Width**|**Quantity**|**Quantity**|**Quantity**| |---|---|---|---|---|---|---|---|---|---|---|---|---| |FDD10AN06A0||FDD10AN06A0|D-PAK||330mm|||16mm||2500 units||| |**Electrical Characteristics**TC= 25°C unless otherwise noted||||||||||||| |**Symbol**|**Parameter**|||**Test Conditions**||||**Min**|**Typ**||**Max**|**Unit**| |**Off Characteristics**||||||||||||| |BVDSS|Drain to Source Breakdown Voltage|||ID= 250μA, VGS=||0V||60|-||-|V| |IDSS|Zero Gate Voltage Drain Current|||VDS= 50V
VGS= 0V||||-|-||1|μA| |||||||TC= 150oC||-|-||250|| |IGSS|Gate to Source Leakage Current|||VGS= ±20V||||-|-||±100|nA| |**On Characteristics**||||||||||||| |VGS(TH)|Gate to Source Threshold Voltage|||VGS= VDS, ID= 250μA||||2|-||4|V| |rDS(ON)|Drain to Source On Resistance|||ID= 50A, VGS= 10V||||-|0.0094||0.0105|Ω| |||||ID= 25A, VGS= 6V||||-|0.015||0.027|| |||||ID= 50A, VGS= 10V,
TJ= 175oC||||-|0.020||0.023|| |**Dynamic Characteristics**||||||||||||| |CISS|Input Capacitance|||VDS= 25V, VGS= 0V,
f = 1MHz||||-|1840||-|pF| |COSS|Output Capacitance|||||||-|340||-|pF| |CRSS|Reverse Transfer Capacitance|||||||-|110||-|pF| |Qg(TOT)|Total Gate Charge at 10V|||VGS= 0V to 10V|||||28||37|nC| |Qg(TH)|Threshold Gate Charge|||VGS= 0V to 2V||||-|3.5||4.6|nC| |Qgs|Gate to Source Gate Charge|||||||-|9.8||-|nC| |Qgs2|Gate Charge Threshold to Plateau|||||||-|6.4||-|nC| |Qgd|Gate to Drain “Miller” Charge|||||||-|7.8||-|nC| |**Switching Characteristics**(VGS= 10V)||||||||||||| |tON|Turn-On Time|||VDD= 30V, ID= 50A
VGS= 10V, RGS= 10Ω||||-|-||131|ns| |td(ON)|Turn-On Delay Time|||||||-|8||-|ns| |tr|Rise Time|||||||-|79||-|ns| |td(OFF)|Turn-Off Delay Time|||||||-|32||-|ns| |tf|Fall Time|||||||-|32||-|ns| |tOFF|Turn-Off Time|||||||-|-||97|ns| |**Drain-Source Diode Characteristics**||||||||||||| |VSD|Source to Drain Diode Voltage|||ISD= 50A||||-|-||1.25|V| |||||ISD= 25A||||-|-||1.0|V| |trr|Reverse Recovery Time|||ISD= 50A, dISD/dt = 100A/μs||||-|36||72|ns| |QRR|Reverse Recovered Charge|||ISD= 50A, dISD/dt = 100A/μs||||-|-||23|nC| **Notes:** 1. Starting TJ = 25°C, L = 8.58mH, IAS = 10A. 2 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **Electrical Characteristics** TC = 25°C unless otherwise noted **Figure 1. Normalized Power Dissipation vs Ambient Figure 2. Maximum Continuous Drain Current vs Temperature Case Temperature** **Figure 3. Transfer Characteristics** - **Figure 4. Peak Current Capability** 3 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **Electrical Characteristics** TC = 25°C unless otherwise noted **Figure 5. Forward Bias Safe Operating Area** NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 **Figure 6. Unclamped Inductive Switching Capability** - **Figure 7. Transfer Characteristics** **Figure 8. Saturation Characteristics** - **Figure 9. Drain to Source On Resistance vs Drain Current** **Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature** 4 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **Electrical Characteristics** TC = 25°C unless otherwise noted ## **Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature** **Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature** **Figure 13. Capacitance vs Drain to Source Voltage** **Figure 14. Gate Charge Waveforms for Constant Gate Currents** 5 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **Test Circuits and Waveforms** **Figure 15. Unclamped Energy Test Circuit** **Figure 17. Gate Charge Test Circuit** **Figure 19. Switching Time Test Circuit** **Figure 16. Unclamped Energy Waveforms** **Figure 18. Gate Charge Waveforms** **==> picture [163 x 10] intentionally omitted <==** **----- Start of picture text -----**
Figure 20. Switching Time Waveforms
**----- End of picture text -----**
6 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **Thermal Resistance vs. Mounting Pad Area** The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance R θ JA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. **==> picture [194 x 22] intentionally omitted <==** In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. **==> picture [208 x 206] intentionally omitted <==** **----- Start of picture text -----**
RθJA = 33.32 + ------------------------------------(1.73154+ Area - ) (EQ. 3)
Area in Centimeters Squared
125
R θ JA = 33.32+ 23.84/(0.268+Area) EQ.2
100 R θ JA = 33.32+ 154/(1.73+Area) EQ.3
75
50
25
0.01 0.1 1 10
(0.0645) (0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
oC/W)(RJA θ
**----- End of picture text -----**
**Figure 21. Thermal Resistance vs Mounting Pad Area** 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the R θ JA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. **==> picture [197 x 32] intentionally omitted <==** 7 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **PSPICE Electrical Model** .SUBCKT FDD10AN06A0 2 1 3 ; rev July 2002 Ca 12 8 7e-10 Cb 15 14 7e-10 Cin 6 8 1.8e-9 **==> picture [318 x 257] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
5
51 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE RGATE + 18 - 6
1 9 20 22 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
6 5 VBAT
EGS 8 EDS 8 +
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 67.2 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 3.2e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.2e-9 RLgate 1 9 32 RLdrain 2 5 10 RLsource 3 7 12 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.35e-3 Rgate 9 20 3.6 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 6e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),7))} .MODEL DbodyMOD D (IS=2E-11 N=1.06 RS=3.3e-3 TRS1=2.4e-3 TRS2=1.1e-6 + CJO=1.25e-9 M=5.3e-1 TT=4.2e-8 XTI=3.9) .MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=4.7e-10 IS=1e-30 N=10 M=0.44) .MODEL MmedMOD NMOS (VTO=3.5 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.6) .MODEL MstroMOD NMOS (VTO=4.25 KP=80 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.92 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=36 RS=0.1) .MODEL RbreakMOD RES (TC1=9e-4 TC2=5e-7) .MODEL RdrainMOD RES (TC1=2.5e-2 TC2=7.8e-5) .MODEL RSLCMOD RES (TC1=1e-3 TC2=3.5e-5) .MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.3e-5) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=1.3e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-1.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 8 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## **SABER Electrical Model** REV July 2002 template FDD10AN06A0 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2e-11,nl=1.06,rs=3.3e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.25e-9,m=5.3e-1,tt=4.2e-8,xti=3.9) dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=4.7e-10,isl=10e-30,nl=10,m=0.44) m..model mmedmod = (type=_n,vto=3.5,kp=5.5,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=4.25,kp=80,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.92,kp=0.03,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5) **DPLCAP 5** sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8) **10** sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-1.5) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-2) **51RSLC1RSLC1** c.ca n12 n8 = 7e-10 **RSLC2** c.cb n15 n14 = 7e-10 **ISCL** c.cin n6 n8 = 1.8e-9 **==> picture [312 x 251] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
51RSLC1RSLC1
RSLC2
ISCL
- 50 DBREAK
ESG + 68 EVTHRES RDRAIN16 11 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE1 9RGATE20+ 1822 - 6 MMED EBREAK+
RLGATE MSTRO 17
CIN 8 -18 7 LSOURCE SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
**----- End of picture text -----**
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 67.2 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 3.2e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.2e-9 res.rlgate n1 n9 = 32 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 12 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=9e-4,tc2=5e-7 res.rdrain n50 n16 = 1.35e-3, tc1=2.5e-2,tc2=7.8e-5 res.rgate n9 n20 = 3.6 res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=3.5e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6e-3, tc1=1e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.3e-5 res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=1.3e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 7)) } 9 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com ## _**SPICE Thermal Model**_ REV 23 July 2002 **th JUNCTION** FDD10AN06A0T CTHERM1 TH 6 3.2e-3 CTHERM2 6 5 3.3e-3 CTHERM3 5 4 3.4e-3 CTHERM4 4 3 3.5e-3 **RTHERM1 CTHERM1** CTHERM5 3 2 6.4e-3 CTHERM6 2 TL 1.9e-2 **6** RTHERM1 TH 6 5.5e-4 RTHERM2 6 5 5.0e-3 RTHERM3 5 4 4.5e-2 **RTHERM2 CTHERM2** RTHERM4 4 3 1.5e-1 RTHERM5 3 2 3.37e-1 RTHERM6 2 TL 3.5e-1 **5** _**SABER Thermal Model**_ **RTHERM3 CTHERM3** SABER thermal model FDD10AN06A0T template thermal_model th tl **4** thermal_c th, tl { ctherm.ctherm1 th 6 =3.2e-3 ctherm.ctherm2 6 5 =3.3e-3 **RTHERM4 CTHERM4** ctherm.ctherm3 5 4 =3.4e-3 ctherm.ctherm4 4 3 =3.5e-3 ctherm.ctherm5 3 2 =6.4e-3 **3** ctherm.ctherm6 2 tl =1.9e-2 rtherm.rtherm1 th 6 =5.5e-4 **RTHERM5 CTHERM5** rtherm.rtherm2 6 5 =5.0e-3 rtherm.rtherm3 5 4 =4.5e-2 rtherm.rtherm4 4 3 =1.5e-1 **2** rtherm.rtherm5 3 2 =3.37e-1 rtherm.rtherm6 2 tl =3.5e-1 } **RTHERM6 CTHERM6 tl CASE** 10 ©2002 Fairchild Semiconductor Corporation FDD10AN06A0 Rev. 1.5 www.fairchildsemi.com **==> picture [37 x 58] intentionally omitted <==** **==> picture [37 x 54] intentionally omitted <==** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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