# MOSFET, N CHANNEL, 30V, 0.0207OHM, 6.1A, SUPERSOT-6

![Product image](https://novapart.co/image/farnell:2459564/)

**URL**: https://novapart.co/products/FDC855N/mosfet-n-channel-30v-00207ohm-61a-supersot-6
**SKU**: FDC855N
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.2720
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 6Pins |
| Channel Type | N Channel |
| Power Dissipation | 1.6W |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | N Channel |
| Power Dissipation Pd | 1.6W |
| Rds(On) Test Voltage | 10V |
| On Resistance Rds(On) | 0.0207ohm |
| Transistor Case Style | SuperSOT |
| Drain Source Voltage Vds | 30V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 6.1A |
| Drain Source On State Resistance | 0.0207ohm |
| Gate Source Threshold Voltage Max | 2V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2459564/)

tm 

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## 

## **Single N-Channel, Logic Level, PowerTrench[®] MOSFET 30V, 6.1A, 27m** Ω 

## **Features** 

Max rDS(on) = 27mΩ at VGS = 10V, ID = 6.1A 

Max rDS(on) = 36mΩ at VGS = 4.5V, ID = 5.3A 

SuperSOT[TM] -6 package: small footprint (72% smaller than standard SO-8; low profile (1mm thick). 

RoHS Compliant 

## **General Description** 

This N-Channel Logic Level MOSFET is an efficient solution for low voltage and battery powered applications. Utilizing Fairchild Semiconductor’s advanced PowerTrench[®] process, this device possesses minimized on-state resistance to optimize the power consumption. They are ideal for applications where in-line power loss is critical. 

## **Application** 

Power Management in Notebook, Hard Disk Drive 

|**S**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**SuperSOTTM-6**<br>**Pin 1**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**S**<br>ie<br>dl |<br>eo<br>/|**S**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**SuperSOTTM-6**<br>**Pin 1**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**S**<br>ie<br>dl |<br>eo<br>/|**S**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**SuperSOTTM-6**<br>**Pin 1**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**S**<br>ie<br>dl |<br>eo<br>/|**S**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**SuperSOTTM-6**<br>**Pin 1**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**S**<br>ie<br>dl |<br>eo<br>/|**S**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**SuperSOTTM-6**<br>**Pin 1**<br>**D**<br>**D**<br>**G**<br>**D**<br>**D**<br>**S**<br>ie<br>dl |<br>eo<br>/|||
|---|---|---|---|---|---|---|
|**MOSFET Maximum Ratings  **TA= 25°C unless otherwise noted|||||||
|**Symbol**<br>**Parameter**||||**Ratings**||**Units**|
|VDS<br>Drain to Source Voltage||||30||V|
|VGS<br>Gate to Source Voltage||||±20||V|
|ID<br>Drain Current  -Continuous                                        TA= 25°C<br>-Pulsed||= 25°C(Note 1a)||6.1<br>20||A|
|PD<br>Power Dissipation(SteadyState) <br>Power Dissipation(SteadyState)|<br>|(Note 1a)<br> (Note 1b)||1.6<br>0.8||W|
|TJ, TSTG<br>Operatingand Storage Junction Temperature Range||||-55 to +150||°C|
|**Thermal Characteristics**|||||||
|RθJC<br>Thermal Resistance, Junction to Case(Note 1)<br>30<br>°C/W<br>RθJA<br>Thermal Resistance, Junction to Ambient(Note 1a)<br>78<br>~~ee~~|||||||
|**Package Marking and Ordering Information**|||||||
|**Device Marking**<br>**Device**<br>**Package**<br>**Reel Size**<br>**Tape Width**<br>**Quantity**<br>.855<br>FDC855N<br>SuperSOT-6<br>7”<br>8 mm<br>3000 units<br>~~se~~<br>~~eeee~~|||||||



**1** 

©2008 Fairchild Semiconductor Corporation FDC855N Rev.C 

www.fairchildsemi.com 

**Electrical Characteristics** TJ = 25°C unless otherwise noted 

|**Electrical Characteristics**TJ = 25°C unless otherwise notedJ = 25°C unless otherwise noted= 25°C unless otherwise noted|**Electrical Characteristics**TJ = 25°C unless otherwise notedJ = 25°C unless otherwise noted= 25°C unless otherwise noted|**Electrical Characteristics**TJ = 25°C unless otherwise notedJ = 25°C unless otherwise noted= 25°C unless otherwise noted|**Electrical Characteristics**TJ = 25°C unless otherwise notedJ = 25°C unless otherwise noted= 25°C unless otherwise noted|
|---|---|---|---|
|**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>**Off Characteristics**<br>BVDSS<br>Drain to Source Breakdown Voltage<br>ID= 250µA, VGS= 0V<br>30<br>V<br>∆BVDSS<br>∆TJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250µA, referenced to 25°C<br>24<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VGS= 0V, VDS= 24V,<br>1<br>µA<br>TC = 125°C<br>250<br>IGSS<br>Gate to Source Leakage Current<br>VGS= ±20V, VDS = 0V<br>±100<br>nA<br>**On Characteristics**<br>VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS,  ID= 250µA<br>1.0<br>2.0<br>3.0<br>V<br>∆VGS(th)<br>∆TJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= 250µA, referenced to 25°C<br>-6<br>mV/°C<br>rDS(on)<br>Static Drain to Source On Resistance<br>VGS= 10V,  ID= 6.1A<br>20.7<br>27.0<br>mΩ<br>VGS= 4.5V, ID= 5.3A<br>28.2<br>36.0<br>VGS= 10V,  ID= 6.1A, TJ=125°C<br>30.1<br>39.3<br>gFS<br>Forward Transconductance<br>VDD= 10V,  ID= 6.1A<br>20<br>S<br>**Dynamic Characteristics**<br>Ciss<br>Input Capacitance<br>VDS= 15V, VGS= 0V,<br>f = 1MHz<br>493<br>655<br>pF<br>Coss<br>Output Capacitance<br>108<br>145<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>62<br>95<br>pF<br>Rg<br>Gate Resistance<br>f = 1MHz<br>1.0<br>Ω<br>**Switching Characteristics**<br>td(on)<br>Turn-On DelayTime<br>VDD= 15V, ID= 6.1A,<br>VGS= 10V, RGEN= 6Ω<br>6<br>12<br>ns<br>tr<br>Rise Time<br>2<br>10<br>ns<br>td(off)<br>Turn-Off DelayTime<br>14<br>23<br>ns<br>~~——— ae~~<br>~~—————~~||||
|tf<br>Fall Time||2<br>10<br>ns||
|Qg<br>Total Gate Charge at 10V<br>VGS= 0V to 10V<br>VDD= 15V,<br>ID= 6.1A<br>9.2<br>13<br>nC<br>Qg<br>Total Gate Charge at 5V<br>VGS= 0V to 5V<br>4.9<br>7.0<br>nC<br>Qgs<br>Gate to Source Charge<br>1.7<br>nC<br>Qgd<br>Gate to Drain “Miller” Charge<br>3.1<br>nC<br>~~——————~~||||
|**Drain-Source Diode Characteristics**||||
|VSD<br>Source to Drain Diode  Forward Voltage<br>VGS = 0V, IS = 1.3A(Note 2)<br>0.80<br>1.2<br>V<br>trr<br>Reverse RecoveryTime<br>IF= 6.1A, di/dt = 100A/µs<br>17<br>31<br>ns<br>Qrr<br>Reverse RecoveryCharge<br>6<br>12<br>nC<br>~~———————~~||||
|**Notes:**||||
|**1:**RθJAis the sum of the junction-to-case and case-to- ambient  thermal resistance where the case thermal reference is defined  as the solder mounting surface of the drain pins.||is the sum of the junction-to-case and case-to- ambient  thermal resistance where the case thermal reference is defined  as the solder mounting surface of the drain pins.||
|RθJCis guaranteed by design  while RθCAis determined by the user’s board design.||||
|a. 78°C/W when mounted  on a||b. 156°C/W when mounted on  a||
|1 in2pad of  2 oz  copper.||minimum pad of 2 oz copper.||
|**2:**Pulse Test: Pulse Width<300µs, Duty Cycle < 2.0%.||||



- ©2008 Fairchild Semiconductor Corporation FDC855N Rev.C 

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**2** 

## **Typical Characteristics** TJ = 25°C unless otherwise noted 

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20 4.0<br>VGS = 4.5V PULSE DURATION = 80 µ s<br>VGS = 4.0V 3.5 DUTY CYCLE = 0.5%MAX<br>16 VGS = 10V 3.0 VGS = 3.5V<br>12 VGS = 6V VGS = 4.0V<br>2.5<br>2.0<br>8<br>VGS = 3.5V VGS = 4.5V<br>1.5<br>4 PULSE DURATION = 80DUTY CYCLE = 0.5%MAX µ s 1.0<br>VGS =  6V VGS =  10V<br>0 0.5<br>0 1 2 3 4 0 4 8 12 16 20<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A)<br>Figure 1.  On-Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 60<br> ID = 6.1A PULSE DURATION = 300 µ s<br>1.4 VGS = 10V DUTY CYCLE = 2%MAX<br>50<br>ID = 6.1A<br>1.2<br>40<br>1.0 TJ = 125 [o] C<br>30<br>0.8<br>TJ = 25 [o] C<br>0.6 20<br>-75 -50 -25 0 25 50 75 100 125 150 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On- Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>20 20<br>PULSE DURATION = 80 µ s 10 VGS = 0V<br>DUTY CYCLE = 0.5%MAX<br>16<br>VDS = 10V 1<br>12<br>TJ = 150 [o] C<br>0.1 TJ = 25 [o] C<br>8<br>TJ = 150 [o] C TJ = 25 [o] C 0.01<br>4 TJ = -55 [o] C<br>TJ = -55 [o] C<br>0 0.001<br>1 2 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>DRAIN CURRENT (A)<br>,<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>m<br>(<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID , REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

©2008 Fairchild Semiconductor Corporation FDC855N Rev.C 

**3** 

## **Typical Characteristics** TJ = 25°C unless otherwise noted 

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10 1000<br>ID = 6.1A Ciss<br>8<br>VDD = 15V<br>6 Coss<br>VDD = 10V<br>VDD = 20V<br>4 100<br>2 f = 1MHz Crss<br>VGS = 0V<br>0 20<br>0 3 6 9 12 0.1 1 10 30<br>Qg, GATE CHARGE(nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>30 100<br>10 10 0µ s VGS = 10V SINGLE PULSE<br>R θ JA = 156 [o] C/W<br>1ms TA = 25 [o] C<br>1 10<br>10ms<br>THIS AREA IS<br>LIMITED BY r 100ms<br>DS(on)<br>0.1 SINGLE PULSE<br>TJ = MAX RATED 1s<br>R θ JA = 156 [o] C/W DC 1<br>TA = 25 [o] C<br>0.01 0.5<br>0.01 0.1 1 10 100 10-3 10-2 10-1 1 10 100 1000<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>Figure 9.  Forward Bias Safe                                      Figure 10.   Single  Pulse Maximum<br>Operating Area  Power  Dissipation<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05<br>      0.02 PDM<br>      0.01<br>0.1<br>t1<br>t2<br>NOTES:<br>SINGLE PULSE DUTY FACTOR: D = t1/t2<br>R θ JA = 156 [o] C/W PEAK TJ = PDM x Z θJA  x R θJA  + TA<br>0.01<br>10-3 10-2 10-1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE(V)<br>GS<br>V<br>, DRAIN CURRENT (A)<br>D<br> I<br>PEAK TRANSIENT POWER (W)<br>P)(PK,<br>ZJA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 11.  Transient Thermal Response Curve** 

www.fairchildsemi.com 

©2008 Fairchild Semiconductor Corporation FDC855N Rev.C 

**4** 

## **Dimensional Outline and Pad Layout** 

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©2008 Fairchild Semiconductor Corporation<br>FDC855N Rev.C<br>**----- End of picture text -----**<br>


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**5** 

## **TRADEMARKS** 

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. 

ACEx[®] 

ACEx FPS™ PDP-SPM™ SupreMOS™ Build it Now™ FRFET[®] Power220[®] SyncFET™ CorePLUS™ Global Power Resource[SM] POWEREDGE[®] ® _CROSSVOLT_ ™ Green FPS™ Power-SPM™ DS ceNerAL The Power Franchise[®] CTL™Current Transfer Logic™ Green FPS™ e-Series™GTO™ PowerTrenchProgrammable Active Droop™[®] Pavethe wer tm EcoSPARK[®] _i-Lo_ ™ QFET[®] TinyBoost™ EZSWITCH™ * IntelliMAX™ QS™ ™ ISOPLANAR™ QT Optoelectronics™ TinyBuck™ TinyLogic[®] ® MegaBuck™ Quiet Series™ TINYOPTO™ tm MICROCOUPLER™ RapidConfigure™ TinyPower™ Fairchild[®] MicroFET™ SMART START™ TinyPWM™ Fairchild Semiconductor[®] MicroPak™ SPM[®] TinyWire™ FACT Quiet Series™ MillerDrive™ STEALTH™ µSerDes™ FACT[®] Motion-SPM™ SuperFET™ UHC[®] FAST[®] OPTOLOGIC[®] SuperSOT™-3 Ultra FRFET™ FastvCore™FlashWriter[® ] * OPTOPLANARtm®[®] SuperSOT™-6SuperSOT™-8 UniFET™VCX™ 

* EZSWITCH™ and FlashWriter[®] are trademarks of System General Corporation, used under license by Fairchild Semiconductor. 

## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

As used herein: 

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 

2. A critical component in any component of a life support, device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 

## **PRODUCT STATUS DEFINITIONS** 

## **Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative or In Design|This datasheet contains the design specifications for product development.<br>Specifications may change in any manner without notice.|
|Preliminary|First Production|This datasheet contains preliminary data; supplementary data will be pub-<br>lished at a later date. Fairchild Semiconductor reserves the right to make<br>changes at any time without notice to improve design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild Semiconductor reserves<br>the right to make changes at any time without notice to improve design.|
|Obsolete|Not In Production|This datasheet contains specifications on a product that has been discontin-<br>ued by Fairchild Semiconductor. The datasheet is printed for reference infor-<br>mation only.|



Rev. I33 

©2008 Fairchild Semiconductor Corporation FDC855N Rev.C 

www.fairchildsemi.com 



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