# Dual MOSFET, Complementary N and P Channel, 25 V, 220 mA, 3.1 ohm, SOT-23, Surface Mount

![Product image](https://novapart.co/image/farnell:2453396/)

**URL**: https://novapart.co/products/FDC6320C/dual-mosfet-complementary-n-and-p-channel-25-v-220
**SKU**: FDC6320C
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Dual MOSFETs
**Price**: €0.1110
**Stock**: 10+

## Specifications

| Parameter | Value |
|---|---|
| No. Of Pins | 6Pins |
| Channel Type | Complementary N and P Channel |
| Transistor Mounting | Surface Mount |
| Transistor Polarity | Complementary N and P Channel |
| Power Dissipation Pd | 900mW |
| Rds(On) Test Voltage | 4.5V |
| On Resistance Rds(On) | 3.1ohm |
| Transistor Case Style | SOT-23 |
| Drain Source Voltage Vds | 25V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 220mA |
| Power Dissipation N Channel | 900mW |
| Power Dissipation P Channel | 900mW |
| Gate Source Threshold Voltage Max | 850mV |
| Drain Source Voltage Vds N Channel | 25V |
| Drain Source Voltage Vds P Channel | 25V |
| Continuous Drain Current Id N Channel | 220mA |
| Continuous Drain Current Id P Channel | 220mA |
| Drain Source On State Resistance N Channel | 3.1ohm |
| Drain Source On State Resistance P Channel | 3.1ohm |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2453396/)

FAIRCHILD 

October 1997 

SEMICONDUCTOR m 

## **FDC6320C Dual N & P Channel , Digital FET** 

## 

These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The  device is an improved  design especially for low voltage applications  as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors. 

## 

- N-Ch 25 V, 0.22 A,  RDS(ON) = 5 Ω @ VGS= 2.7 V. 

- P-Ch 25 V, -0.12 A, RDS(ON) = 13 Ω @ VGS= -2.7 V. 

- Very low level gate drive requirements allowing  direct operation in 3 V circuits. VGS(th) < 1.5 V. 

- Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace  NPN & PNP digital transistors. 

**==> picture [190 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT-23 SuperSOTTM-6 SuperSOTTM-8<br>**----- End of picture text -----**<br>


**==> picture [175 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SO-8 SOT-223 SOIC-16<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
4 3<br>5 2<br>6 1<br>**----- End of picture text -----**<br>


|**Absolute Maximum Ratings**TA= 25<br>oC unless  other wise noted|C unless  other wise noted||
|---|---|---|
|**Parameter**|**N-Channel**|**P-Channel**|
|Drain-Source Voltage, Power Supply Voltage|25|-25|
|Gate-Source Voltage,|8|-8|
|Drain/Output Current<br>- Continuous<br>- Pulsed|0.22|-0.12|
||0.5|-0.5|
|Maximum Power Dissipation(Note 1a)<br> (Note 1b)|0.9||
||0.7||
|Operating and Storage Tempature Ranger|-55 to 150||
|Electrostatic Discharge  Rating MIL-STD-883D<br>Human Body  Model (100pf / 1500 Ohm)|6||



© 1997 Fairchild Semiconductor Corporation 

FDC6320C.Rev C 

**DMOS Electrical Characteristics** (TA = 25 OC unless otherwise noted ) 

|**DMOS Ele**|**ctrical Characteristics**(TA= 25<br>OC unl|ess otherwise noted )|ess otherwise noted )||||||
|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**||**Type**|**Min**|**Typ**|**Max**|**Units**|
|**OFF CHARACTERISTICS**|||||||||
|BVDSS|Drain-Source Breakdown Voltage|VGS= 0 V,  ID= 250 µA||N-Ch|25|||V|
|||VGS= 0 V,  ID= -250 µA||P-Ch|-25||||
|∆BVDSS/∆TJ|Breakdown Voltage Temp. Coefficient|ID= 250 µA, Referenced to  25<br>oC||N-Ch||25||mV /<br>oC|
|||ID= -250 µA, Referenced to  25<br>oC||P-Ch||-20|||
|IDSS|Zero Gate Voltage  Drain Current|VDS= 20 V,  VGS= 0 V,||N-Ch|||1|µA|
||||TJ= 55°C||||10||
|IDSS|Zero Gate Voltage  Drain Current|VDS=-20 V,  VGS= 0 V,||P-Ch|||-1|µA|
||||TJ= 55°C||||-10||
|IGSS|Gate - Body Leakage Current|VGS= 8 V,  VDS= 0 V||N-Ch|||100|nA|
|||VGS= -8 V,  VDS= 0 V||P-Ch|||-100|nA|
|**ON CHARACTERISTICS**(Note 2)|||||||||
|∆VGS(th)/∆TJ|Gate Threshold Voltage Temp. Coefficient|ID= 250 µA, Referenced|to  25<br>oC|N-Ch||-2.1||mV /<br>oC|
|||ID= -250 µA, Referenced|to  25<br>oC|P-Ch||1.9|||
|VGS(th)|Gate Threshold Voltage|VDS= VGS,  ID= 250 µA||N-Ch|0.65|0.85|1.5|V|
|||VDS= VGS,  ID= -250 µA||P-Ch|-0.65|-1|-1.5||
|RDS(ON)|Static Drain-Source On-Resistance|VGS= 2.7 V,  ID= 0.2 A||N-Ch||3.8|5|Ω|
||||T**J**=125°C|||6.3|9||
|||VGS= 4.5 V,  ID= 0.4 A||||3.1|4||
|||VGS= -2.7 V,  ID= -0.05 A<br>T**J**=125°C||P-Ch||10.6|13||
||||T**J**=125°C|||15|21||
|||VGS= -4.5 V,  ID= -0.2 A||||7.9|10||
|ID(ON)|On-State Drain Current|VGS= 2.7 V,  VDS= 5 V||N-Ch|0.2|||A|
|||VGS= -2.7 V,  VDS= -5 V||P-Ch|-0.05||||
|gFS|Forward Transconductance|VDS= 5 V,  ID=  0.4 A||N-Ch||0.2||S|
|||VDS= -5 V,  ID= -0.2 A||P-Ch||0.135|||
|**DYNAMIC CHARACTERISTICS**|||||||||
|Ciss|Input Capacitance|N-Channel<br>V**DS**= 10 V,  V**GS**= 0 V,<br>f  = 1.0 MHz<br>P-Channel<br>V**DS**= -10 V,  V**GS**= 0 V,<br>f  = 1.0 MHz||N-Ch||9.5||pF|
|||||P-Ch||11|||
|Coss|Output Capacitance|||N-Ch||6||pF|
|||||P-Ch||7|||
|Crss|Reverse Transfer Capacitance|||N-Ch||1.3||pF|
|||||P-Ch||1.4|||



FDC6320C.Rev C 

**DMOS Electrical Characteristics** (TA = 25[O] C unless otherwise noted ) 

|**Symbol**|**Parameter**|**Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|---|
|**SWITCHING CHARACTERISTICS**(Note 2)||||||||
|tD(on)|Turn - On Delay Time|N-Channel|N-Ch||5|11|nS|
|||VDD= 6 V, ID= 0.5 A,|P-Ch||6|12||
|tr|Turn - On Rise Time|VGS= 4.5 V, RGEN= 50Ω|N-Ch||4.5|10|nS|
||||P-Ch||6|12||
|tD(off)|Turn - Off Delay Time|P-Channel|N-Ch||4|10|nS|
|||VDD= -6 V, ID= -0.5 A,|P-Ch||7.4|15||
|tf|Turn - Off Fall Time|VGEN= -4.5 V, RGEN= 50Ω|N-Ch||3.2|8|nS|
||||P-Ch||4|10||
|Qg|Total Gate Charge|N-Channel|N-Ch||0.29|0.4|nC|
|||VDS= 5 V,<br>ID=  0.2 A,  VGS= 4.5 V|P-Ch||0.23|0.32||
|Qgs|Gate-Source Charge||N-Ch||0.105||nC|
|||P-Channel|P-Ch||0.12|||
|Qgd|Gate-Drain Charge|VDS= -5 V,<br>ID=  -0.2A,  VGS= -4.5 V|N-Ch||0.045||nC|
||||P-Ch||0.03|||
|**DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**||||||||
|IS|Maximum Continuous Drain-Source Diode Forward Current||N-Ch|||0.5|A|
||||P-Ch|||-0.5||
|VSD|Drain-Source Diode Forward  Voltage|VGS= 0 V,  IS= 0.5 A (Note 2)|N-Ch||0.97|1.3|V|
|||VGS= 0 V,  IS= -0.5 A (Note 2)|P-Ch||-1|-1.3||



Notes: 

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. 

- θJA using the board layouts shown below on  FR-4 PCB in a still air environment: 

a. 140OC/W on a 0.125 in2 pad of b. 180OC/W on a 0.005 in2 of pad 2oz copper. of 2oz copper. 

- Scale 1 : 1 on letter size paper 

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. 

FDC6320C.Rev C 

## **Typical Electrical Characteristics:  N-Channel** 

**==> picture [222 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.5<br>V     = 4.5VGS    4.0<br> 3.5<br>0.4 3.0<br>2.7<br>0.3  2.5<br>0.2<br>2.0<br>0.1<br> 1.5<br>0<br>0 0.5 1 1.5 2 2.5 3<br>V     , DRAIN-SOURCE VOLTAGE (V)DS<br>I    , DRAIN-SOURCE CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure 1. On-Region Characteristics** . 

**==> picture [223 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.8<br>I   = 0.2AD<br>1.6 V     = 2.7 VGS<br>1.4<br>1.2<br>1<br>0.8<br>0.6<br>-50 -25 0 25 50 75 100 125 150<br>T  , JUNCTION TEMPERATURE (°C)J<br>DS(ON)<br>R            , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


## **Figure 3. On-Resistance Variation with Temperature** . 

**==> picture [226 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.2<br>V     = 5.0VDS T  = -55°CJ 25°C<br>125°C<br>0.15<br>0.1<br>0.05<br>0<br>0.5 1 1.5 2 2.5<br>V     , GATE TO SOURCE VOLTAGE (V)GS<br>I   , DRAIN CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure  5. Transfer Characteristics.** 

**==> picture [225 x 343] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.4<br>V    = 2.0VGS<br>1.2<br> 2.5<br>2.7<br>1<br> 3.0<br>3.5<br>0.8 4.0<br>4.5<br>0.6<br>0 0.1 0.2 0.3 0.4 0.5<br>I    , DRAIN CURRENT (A)D<br>Figure 2. On-Resistance Variation with<br>Drain Current and Gate Voltage .<br>15<br> I    = 0.2AD<br>12<br> 25°C  125°C<br>9<br>6<br>3<br>0<br>2 2.5 3 3.5 4<br>V      , GATE TO SOURCE VOLTAGE (V)GS<br> , NORMALIZEDDS(on)<br>R<br>DRAIN-SOURCE ON-RESISTANCE<br>DS(on)<br>R           , ON-RESISTANCE (OHM)<br>**----- End of picture text -----**<br>


**Figure 4. On Resistance Variation with Gate-To- Source Voltage.** 

**==> picture [206 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.5<br>V     = 0VGS<br>0.2<br>0.1 T   J = 125°C<br>25 ° C<br>0.01 -55°C<br>0.001<br>0.0001<br>0.2 0.4 0.6 0.8 1 1.2<br>V     , BODY DIODE FORWARD VOLTAGE (V)SD<br>I   , REVERSE DRAIN CURRENT (A)<br>S<br>**----- End of picture text -----**<br>


**Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.** 

FDC6320C.Rev C 

## **Typical Electrical Characteristics: N-Channel (continued)** 

**==> picture [465 x 349] intentionally omitted <==**

**----- Start of picture text -----**<br>
30 5<br>20 I   = 0.2AD V     = 5.0VDS<br>4<br>10 C  iss<br>3<br>C  oss<br>5<br>2<br>3<br>2 f = 1 MHz<br>V     = 0VGS C  rss 1<br>1<br>0.1 0.5 1 2 5 10 25 0<br>V     , DRAIN TO SOURCE VOLTAGE (V)DS 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35<br>Q    , GATE CHARGE (nC)g<br>Figure 7. Capacitance Characteristics . Figure 8. Gate Charge Characteristics .<br>0.8 5<br>0.5<br>SINGLE PULSE<br>4<br>R     =See note 1b  θ [JA]<br>0.2 T  = 25°CA<br>3<br>0.1<br>2<br>0.05<br>V     = 2.7VGS<br>SINGLE PULSE<br>1<br>0.02 R     =See note 1b       θ [JA]<br>T  = 25°CA<br>0.01 0<br>0.5 1 2 5 10 20 40 0.01 0.1 1 10 100 300<br> V     , DRAI N-SOURCE VOLTAGE (V)DS SINGLE PULSE TIME (SEC)<br>RDS(ON) LIMIT<br> 10ms<br>100ms<br> 1ms<br> 1s<br> DC<br>CAPACITANCE (pF)<br>GS<br>V     , GATE-SOURCE VOLTAGE (V)<br>POWER (W)<br>I   , DRAIN CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure 9. Maximum Safe Operating Area.** 

**Figure 10. Single Pulse Maximum Power Dissipation.** 

FDC6320C.Rev C 

## **Typical Electrical Characteristics:  P-Channel** 

**==> picture [220 x 133] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.2<br>V      = -5.0VGS -4.0<br>-4.5 -3.5<br>-3.0<br>0.15<br>-2.7<br>0.1  -2.5<br>0.05  -2.0<br>0<br>0 1 2 3 4<br>-V     , DRAIN-SOURCE VOLTAGE (V)DS<br>D<br>-I    , DRAIN-SOURCE CURRENT (A)<br>**----- End of picture text -----**<br>


**Figure 11. On-Region Characteristics** . 

**==> picture [223 x 139] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.6<br>I   = -0.05AD<br>1.4 V     = -2.7VGS<br>1.2<br>1<br>0.8<br>0.6<br>-50 -25 0 25 50 75 100 125 150<br>T  , JUNCTION TEMPERATURE (°C)J<br>DS(ON)<br>R              , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


## **Figure 13. On-Resistance Variation with Temperature** . 

**==> picture [199 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
2<br>V     = -2.0 VGS<br>1.5 -2.5<br>-2.7<br>-3.0<br>1 -4.0<br>-3.5<br>-4.5<br>0.5<br>0 0.05 0.1 0.15 0.2<br>-I    , DRAIN CURRENT (A)D<br>DS(ON)<br>R           , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 12. On-Resistance Variation with Drain Current and Gate Voltage** . 

**==> picture [227 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
25<br>T  = 25°CA I   = -0.05AD<br>20<br> 125 °C<br>15<br>10<br>5<br>0<br>0 1 2 3 4 5 6 7 8<br>-V       ,GATE TO SOURCE VOLTAGE (V)GS<br>   ,DRAIN-SOURCE ON-RESISTANCE<br>DS(ON)<br>R<br>**----- End of picture text -----**<br>


**Figure 14. On Resistance Variation with Gate-To- Source Voltage.** 

**==> picture [220 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
-1<br>V     = -5VDS T   = -55°CJ<br>25°C<br>-0.75<br>125°C<br>-0.5<br>-0.25<br>0<br>-0.5 -1 -1.5 -2 -2.5 -3<br>V     , GATE TO SOURCE VOLTAGE (V)GS<br>I   , DRAIN CURRENT (A)D<br>**----- End of picture text -----**<br>


**==> picture [195 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.5<br>V    = 0V GS T  = 125°CJ<br>0.1<br>25°C<br>0.01  -55°C<br>0.0001<br>0 0.2 0.4 0.6 0.8 1 1.2<br>-V     , BODY DIODE FORWARD VOLTAGE (V)SD<br>-I   , REVERSE DRAIN CURRENT (A)<br>S<br>**----- End of picture text -----**<br>


**Figure  15. Transfer Characteristics.** 

**Figure 16. Body Diode Forward Voltage Variation with Source Current and Temperature.** 

FDC6320C.Rev C 

## **Typical Electrical Characteristics:  P-Channel (continued)** 

**==> picture [459 x 342] intentionally omitted <==**

**----- Start of picture text -----**<br>
8 0.8<br>I    = -0.2AD V    = -5VDS 0.5<br>-10<br>6 -15<br>0.2<br>4 0.1<br>0.05<br>2 V     = -2.7VGS<br>SINGLE PULSE<br>0.02 R     =See Note 1b   θ [JA]<br>0 T  = 25°CA<br>0 0.1 0.2 0.3 0.4 0.5 0.01<br>Q    , GATE CHARGE (nC)g 1 2 5 10 20 40<br>- V     , DRAIN-SOURCE VOLTAGE (V)DS<br>Figure 17. Gate Charge Characteristics . Figure 18. Maximum Safe Operating Area.<br>25 5<br>15<br>4 SINGLE PULSE<br>C  iss<br>10 R     =See note 1b  θ [JA]<br>T  = 25°CA<br>C   oss 3<br>5<br>2<br>3<br>2 f = 1 MHz 1<br>V     = 0 VGS          C  rss<br>1 0<br>0.1 0.3 1 2 5 10 15 25 0.01 0.1 1 10 100 300<br>-V     , DRAIN TO SOURCE VOLTAGE (V)DS SINGLE PULSE TIME (SEC)<br>RDS(ON) LIMIT 100ms<br> 1s<br>1ms<br>10ms<br>DC<br>D<br>GS -I   , DRAIN CURRENT (A)<br>-V      , GATE-SOURCE VOLTAGE (V)<br>POWER (W)<br>CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 19. Capacitance Characteristics** . 

**Figure 20. Single Pulse Maximum Power Dissipation.** 

**==> picture [409 x 125] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>0.5  D = 0.5<br>R       (t) = r(t)  θ [JA] *   R         θ [JA]<br>0.2   0.2      R         θ [JA] = See Note 1b<br> 0.1<br>0.1 P(pk)<br> 0.05<br>0.05  t  1<br> 0.02   t   2<br> 0.01  T  - T    = P  * R       (t)J A θ [JA]<br>0.02  Single Pulse<br>Duty Cycle, D = t   / t1 2<br>0.01<br>0.0001 0.001 0.01 0.1 1 10 100 300<br>t  , TIME (sec)1<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 21. Transient Thermal Response Curve** . Note: Thermal characterization performed using the conditions described in note 1b.Transient thermal response will change depending on the circuit board design. 

FDC6320C.Rev C 

## **TRADEMARKS** 

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 

**==> picture [433 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||||
|---|---|---|---|---|---|---|
|ACEx™|FAST||OPTOLOGIC™|SMART START™|VCX™|
|Bottomless™|FASTr™|OPTOPLANAR™|STAR*POWER™|
|CoolFET™|FRFET™|PACMAN™|Stealth™|
|CROSSVOLT|™|GlobalOptoisolator™|POP™|SuperSOT™-3|
|DenseTrench™|GTO™|Power247™|SuperSOT™-6|
|DOME™|HiSeC™|PowerTrench||SuperSOT™-8|
|EcoSPARK™|ISOPLANAR™|QFET™|SyncFET™|
|E|[2]|CMOS|[TM]|LittleFET™|QS™|TinyLogic™|
|EnSigna|[TM]|MicroFET™|QT Optoelectronics™|TruTranslation™|
|FACT™|MicroPak™|Quiet Series™|UHC™|
|FACT Quiet Series™|MICROWIRE™|SILENT SWITCHER||UltraFET||

**----- End of picture text -----**<br>


STAR*POWER is used under license 

## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. 

## **PRODUCT STATUS DEFINITIONS** 

## **Definition of Terms** 

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**----- Start of picture text -----**<br>
Datasheet Identification Product Status Definition<br>Advance Information Formative or This datasheet contains the design specifications for<br>In Design product development. Specifications may change in<br>any manner without notice.<br>Preliminary First Production This datasheet contains preliminary data, and<br>supplementary data will be published at a later date.<br>Fairchild Semiconductor reserves the right to make<br>changes at any time without notice in order to improve<br>design.<br>No Identification Needed Full Production This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at<br>any time without notice in order to improve design.<br>Obsolete Not In Production This datasheet contains specifications on a product<br>that has been discontinued by Fairchild semiconductor.<br>The datasheet is printed for reference information only.<br>**----- End of picture text -----**<br>


Rev. H4 



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