# Power MOSFET, N Channel, 80 V, 220 A, 0.003 ohm, H-PSOF, Surface Mount

![Product image](https://novapart.co/image/farnell:3003990/)

**URL**: https://novapart.co/products/FDBL86366-F085/power-mosfet-n-channel-80-v-220-a-0003-ohm-h-psof
**SKU**: FDBL86366-F085
**Manufacturer**: ONSEMI
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.0800
**Stock**: 1000+
**Lead Time**: 120 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:220A; Drain Source Voltage Vds:80V; On Resistance Rds(on):0.0024ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vg

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | Lead (25-Jun-2025) |
| No. Of Pins | 8Pins |
| Channel Type | N Channel |
| Product Range | PowerTrench |
| Qualification | AEC-Q101 |
| Power Dissipation | 300W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 10V |
| Transistor Case Style | H-PSOF |
| Drain Source Voltage Vds | 80V |
| Operating Temperature Max | 175°C |
| Continuous Drain Current Id | 220A |
| Drain Source On State Resistance | 0.003ohm |
| Gate Source Threshold Voltage Max | 3V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3003990/)

## MOSFET – POWERTRENCH N-Channel **80 V, 220 A, 3.0 m** ~~-~~ 

## FDBL86366-F085 

## **Features** 

- Typical RDS(on) = 2.4 m . at VGS = 10 V, ID = 80 A 

- Typical Qg(tot) = 86 nC at VGS = 10 V, ID = 80 A 

- UIS Capability 

- AEC−Q101 Qualified and PPAP Capable 

- These Devices are Pb−Free and are RoHS Compliant 

## **Applications** 

- Automotive Engine Control 

- PowerTrain Management 

- Solenoid and Motor Drivers 

- Integrated Starter/Alternator 

- Primary Switch for 12 V Systems 

**www.onsemi.com** ~~ee~~ 

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D<br>G<br>S<br>N−Channel<br>**----- End of picture text -----**<br>


**MOSFET MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 

|**MOSFET MAXIMUM RATINGS**|**MOSFET MAXIMUM RATINGS**(TJ = 25J = 25= 25°C unless otherwise noted)|C unless otherwise noted)|C unless otherwise noted)|
|---|---|---|---|
|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|VDSS|Drain−to−Source Voltage|80|V|
|VGS<br>~~i a~~|Gate−to−Source Voltage<br>~~a~~|±20<br>~~a~~|V<br>~~a~~|
|ID<br>~~ee~~|Drain Current − Continuous<br>(VGS= 10), TC= 25°C (Note 1)|220|A<br>~~ee~~|
||Pulsed Drain Current, TC= 25°C<br>~~ee~~|See Figure 4<br>~~ee~~||
|EAS<br>~~ee~~<br>~~es~~|Single Pulse Avalanche Energy<br>(Note 2)<br>~~ee~~<br>~~es~~|205<br>~~ee~~|mJ<br>~~ee~~|
|PD<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~i~~|Power Dissipation<br>~~ee~~<br>~~es~~<br>~~ee~~<br>|300<br>~~ee~~|W<br>~~ee~~|
||Derate Above 25°C<br>~~es~~<br>~~ee~~<br>|2.0|W/°C|
|TJ, TSTG<br>~~es~~<br>~~ee~~<br>~~i ~~|Operating and Storage Temperature<br>~~es~~<br>~~ee~~<br> ~~a~~|−55 to +175|°C|
|R JC<br>|Thermal Resistance, Junction to Case<br> ~~a~~|0.5|°C/W|
|R JA|Maximum Thermal Resistance,<br>Junction to Ambient (Note 3)|43|°C/W|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Current is limited by silicon. 

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H−PSOF8L<br>CASE 100CU<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAM** 

$Y&Z&3&K FDBL 86366 

$Y = ON Semiconductor Logo &Z = Assembly Plant Code &3 = Numeric Date Code &K = Lot Code FDBL86366 = Specific Device Code 

2. Starting TJ = 25 ° C, L = 0.1 mH, IAS = 64 A, VDD = 80 V during inductor charging and VDD = 0 V during time in avalanche. 

3. R 8 JA is the sum of the junction−to−case and case−to−ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain pins. R Q JC is guaranteed by design, while R es JA is determined by the board design. The maximum rating presented here is based on mounting on a 1 in[2] pad of 2oz copper. 

## **ORDERING INFORMATION** 

|**Device**<br>a|**Top Mark**|**Package**|**Shipping**|
|---|---|---|---|
|FDBL86366<br>−F085|FDBL86366|H−PSOF8L <br>FDBL86366|2000 Units/<br>Tape&Reel|



- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2015 **January, 2020 − Rev. 3** 

**FDBL86366−F085/D** 

**FDBL86366−F085** 

**ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL**|**CHARACTERISTICS**(TJ= 25°C un|less otherwise noted)|less otherwise noted)|||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**||**Min.**|**Typ.**|**Max.**|**Unit**|
|**OFF CHARACTERISTICS**||||||||
|BVDSS|Drain−to−Source Breakdown Voltage|ID= 250�A, VGS= 0 V||80|−|−|V|
|IDSS|Drain−to−Source Leakage Current|VDS= 80 V,<br>VGS= 0 V|TJ= 25°C|−|−|1|�A|
||||TJ= 175°C (Note 4)|−|−|1|mA|
|IGSS|Gate−to−Source Leakage Current|VGS=±20 V||−|−|±100|nA|
|**ON CHARACTERISTICS**||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS, ID=|250�A|2.0|3.0|4.0|V|
|RDS(on)|Drain to Source on Resistance|ID= 80 A,<br>VGS= 10 V|TJ= 25°C|−|2.4|3.0|m�|
||||TJ= 175°C (Note 4)|−|4.9|6.1|m�|
|**DYNAMIC CHARACTERISTICS**||||||||
|Ciss|Input Capacitance|VDS= 40 V, VGS= 0 V, f = 1 MHz||−|6320|−|pF|
|Coss|Output Capacitance|||−|1030|−|pF|
|Crss|Reverse Transfer Capacitance|||−|32|−|pF|
|Rg|Gate Resistance|f = 1 MHz||−|2.1|−|�|
|Qg(ToT)|Total Gate Charge at 10 V|VGS= 0 to 10 V|VDD= 64 V,<br>ID= 80 A|−|86|112|nC|
|Qg(th)|Threshold Gate Charge|VGS= 0 to 2 V||−|12|18|nC|
|Qgs|Gate−to−Source Gate Charge|VDD= 64 V, ID= 80 A||−|30|−|nC|
|Qgd|Gate−to−Drain “Miller” Charge|||−|18|−|nC|
|**SWITCHING CHARACTERISTICS**||||||||
|ton|Turn−On Time|VDD= 40 V, ID= 80 A,<br>VGS= 10 V, RGEN= 6�||−|−|98|ns|
|td(on)|Turn−On Delay|||−|30|−|ns|
|tr|Rise Time|||−|34|−|ns|
|td(off)|Turn−Off Delay|||−|40|−|ns|
|tf|Fall Time|||−|17|−|ns|
|toff|Turn−Off Time|||−|−|86|ns|
|**DRAIN−SOURCE DIODE CHARACTERISTIC**||||||||
|VSD|Source−to−Drain Diode Voltage|ISD= 80 A, VGS= 0 V||−|−|1.25|V|
|||ISD= 40 A, VGS= 0 V||−|−|1.2|V|
|trr|Reverse−Recovery Time|IF= 80 A, dISD/dt = 100 A/�s,<br>VDD= 64 V||−|80|120|ns|
|Qrr|Reverse−Recovery Charge|||−|95|140|nC|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

4. The maximum value is specified by design at TJ = 175 ° C. Product is not tested to this condition in production. 

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**2** 

**FDBL86366−F085** 

## **TYPICAL CHARACTERISTICS** 

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1.2 250<br>Current limited VGS = 10 V<br>1.0 by silicon<br>200<br>0.8<br>150<br>0.6<br>100<br>0.4<br>0.2 50<br>0.0 0<br>0 25 50 75 100 125 150 175 25 50 75 100 125 150 175 200<br>TC, Case Temperature [ ° C] TC, Case Temperature [ ° C]<br>Figure 1. Normalized Power Dissipation  Figure 2. Maximum Continuous Drain Current<br>vs. Case Temperature vs. Case Temperature<br>2<br>DUTY CYCLE − DESCENDING ORDER<br>1<br>D = 0.50<br>0.20<br>0.10<br>0.05<br>0.02 PDM<br>0.1 0.01<br>t1<br>t 2<br>NOTES:<br>SINGLE PULSE Duty factor: D = t1 / t2<br>Peak TJ = PDM ×  Z � JA  ×  R � JA + TC<br>0.01<br>10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]<br>t, Rectangular Pulse Duration (s)<br>Figure 3. Normalized Maximum Transient Thermal Impedance<br>10000<br>VGS = 10 V TC = 25 ° C<br>For temperatures<br>above 25 ° C derate peak<br>current as follows:<br>1000 I � I2 �� 175150 � TC �<br>100<br>SINGLE PULSE<br>10<br>10 [−5] 10 [−4] 10 [−3] 10 [−2] 10 [−1] 10 [0] 10 [1]<br>t, Rectangular Pulse Duration (s)<br>, Drain Current [A]<br>ID<br>Power Dissipation Multiplier<br>, Normalized Thermal Impedance<br>JC<br>�<br>Z<br>, Peak Current [A]<br>IDM<br>**----- End of picture text -----**<br>


**Figure 4. Peak Current Capability** 

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**3** 

**FDBL86366−F085** 

## **TYPICAL CHARACTERISTICS** (continued) 

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1000<br>100<br>100  � s<br>10 Operation in this<br>area may be<br>limited by rDS(on)<br>1 1 ms<br>SINGLE PULSE<br>TJ = max rated 10 ms<br>T C  = 25 ° C 100 ms<br>0.1<br>0.1 1 10 100 500<br>VDS, Drain to Source Voltage [V]<br>Figure 5. Forward Bias Safe Operating Area<br>300<br>Pulse duration = 80  � s<br>Duty cycle = 0.5% MAX<br>250 V DD  = 5 V<br>200<br>150<br>TJ = 25 ° C<br>100<br>TJ = 175 ° C TJ = −55 ° C<br>50<br>0<br>2 3 4 5 6 7 8<br>VGS, Gate to Source Voltage [V]<br>Figure 7. Transfer Characteristics<br>300<br>VGS<br>15 V Top<br>250 10 V<br>8 V<br>7 V<br>200<br>80  � s Pulse Width 6 V<br>TJ = 25 ° C 5.5 V<br>150 5 V Bottom<br>100<br>50<br>0<br>0 1 2 3 4 5<br>VDS, Drain to Source Voltage [V]<br>, Drain Current [A]<br>ID<br>, Drain Current [A]<br>ID<br>, Drain Current [A]<br>ID<br>**----- End of picture text -----**<br>


**Figure 9. Saturation Characteristics** 

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1000 If R = 0<br>tAV = (L)(IAS) / (1.3  ×  Rated BVDSS − VDD)<br>If R  ≠ 0<br>tAV = (L/R)ln[(IAS ×  R) / (1.3 ×  Rated BVDSS − VDD) + 1]<br>100<br>Starting TJ =  25 ° C<br>10<br>Starting TJ =  150 ° C<br>1<br>0.001 0.01 0.1 1 10 100 1000<br>tAV, Time in Avalanche [ms]<br>NOTE: Refer to ON Semiconductor Application Notes AN7514 and and AN7515.<br>Figure 6. Unclamped Inductive Switching Capability<br>300<br>VGS = 0 V<br>100<br>TJ = 175 ° C<br>10<br>TJ = 25 ° C<br>1<br>0.1<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VSD, Body Diode Forward Voltage [V]<br>Figure 8. Forward Diode Characteristics<br>300<br>VGS<br>15 V Top<br>250 10 V<br>8 V<br>7 V<br>200<br>6 V<br>5.5 V<br>150 5 V Bottom<br>100<br>50<br>80  � s Pulse Width<br>TJ = 175 ° C<br>0<br>0 1 2 3 4 5<br>VDS, Drain to Source Voltage [V]<br>, Avalanche Current [A]<br>IAS<br>, Reverse Drain Current [A]<br>IS<br>, Drain Current [A]<br>ID<br>**----- End of picture text -----**<br>


NOTE: Refer to ON Semiconductor Application Notes AN7514 and and AN7515. 

**Figure 6. Unclamped Inductive Switching Capability** 

**Figure 10. Saturation Characteristics** 

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**4** 

**FDBL86366−F085** 

## **TYPICAL CHARACTERISTICS** (continued) 

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50<br>ID = 80 A Pulse duration = 80  � s<br>Duty cycle = 0.5% MAX<br>40<br>30<br>TJ = 25 ° C<br>20<br>TJ = 175 ° C<br>10<br>0<br>4 6 8 10<br>VGS, Gate to Source Voltage [V]<br>Figure 11. RDSON vs. Gate Voltage<br>1.5<br>VGS = VDS<br>ID = 250  � A<br>1.2<br>0.9<br>0.6<br>0.3<br>0.0<br>−80 −40 0 40 80 120 160 200<br>TJ, Junction Temperature [ ° C]<br>Figure 13. Normalized Gate Threshold Voltage<br>vs. Temperature<br>10000<br>Ciss<br>1000<br>Coss<br>100<br>Crss<br>f = 1 MHz<br>VGS = 0 V<br>10<br>0.1 1 10 100<br>VDS, Drain to Source Voltage [V]<br>] �<br>, Drain to Source<br>rDS(on) On−Resistance [m<br>Normalized Gate Threshold Voltage<br>Capacitance [pF]<br>**----- End of picture text -----**<br>


**Figure 15. Capacitance vs. Drain to Source Voltage** 

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2.4<br>Pulse duration = 80  � s<br>Duty cycle = 0.5% MAX<br>2.0<br>1.6<br>1.2<br>0.8<br>ID = 80 A<br>VGS = 10 V<br>0.4<br>−80 −40 0 40 80 120 160 200<br>TJ, Junction Temperature [ ° C]<br>On−Resistance<br>Normalized Drain to Source<br>**----- End of picture text -----**<br>


**Figure 12. Normalized RDSON vs. Junction Temperature** 

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1.10<br>ID = 5 mA<br>1.05<br>1.00<br>0.95<br>0.90<br>−80 −40 0 40 80 120 160 200<br>TJ, Junction Temperature [ ° C]<br>Figure 14. Normalized Drain to Source<br>Breakdown Voltage vs. Junction Temperature<br>10<br>ID = 80 A<br>VDD = 40 V<br>8<br>VDD = 32 V VDD = 48 V<br>6<br>4<br>2<br>0<br>0 20 40 60 80 100<br>Qg, Gate Charge [nC]<br>Breakdown Voltage<br>Normalized Drain to Source<br>, Gate to Source Voltage [V]<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 16. Gate Charge vs. Gate to Source Voltage** 

POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. 

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**5** 

## MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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H−PSOF8L 11.68x9.80<br>CASE 100CU<br>ISSUE B<br>DATE 20 MAY 2022<br>**----- End of picture text -----**<br>


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GENERIC<br>MARKING DIAGRAM*<br>AYWWZZ<br>XXXXXXXX<br>XXXXXXXX<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>ZZ = Assembly Lot Code<br>XXXX = Specific Device Code<br>**----- End of picture text -----**<br>


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*This information is generic. Please refer to<br>device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ = ”, may<br>or may not be present. Some products may<br>not follow the Generic Marking.<br>**----- End of picture text -----**<br>


Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **DOCUMENT NUMBER: 98AON13813G** 

## **H−PSOF8L 11.68x9.80** 

## **PAGE 1 OF 1** 

## **DESCRIPTION:** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba onsemi **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

**onsemi** , , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. **onsemi** owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of **onsemi** ’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. **onsemi** reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and **onsemi** makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using **onsemi** products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by **onsemi** . “Typical” parameters which may be provided in **onsemi** data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. **onsemi** does not convey any license under any of its intellectual property rights nor the rights of others. **onsemi** products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use **onsemi** products for any such unintended or unauthorized application, Buyer shall indemnify and hold **onsemi** and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that **onsemi** was negligent regarding the design or manufacture of the part. **onsemi** is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

## **PUBLICATION ORDERING INFORMATION** 

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◊ 

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