# Power MOSFET, N Channel, 30 V, 93 A, 0.0049 ohm, TO-263AB, Surface Mount ![Product image](https://novapart.co/image/farnell:2322578/) **URL**: https://novapart.co/products/FDB8896/power-mosfet-n-channel-30-v-93-a-00049-ohm-to **SKU**: FDB8896 **Manufacturer**: ONSEMI **Category**: Semiconductors - Discretes || FETs || Single MOSFETs **Price**: €0.4470 **Stock**: 10+ ## Specifications | Parameter | Value | |---|---| | No. Of Pins | 3Pins | | Channel Type | N Channel | | Power Dissipation | 80W | | Transistor Mounting | Surface Mount | | Transistor Polarity | N Channel | | Power Dissipation Pd | 80W | | Rds(On) Test Voltage | 10V | | On Resistance Rds(On) | 0.0049ohm | | Transistor Case Style | TO-263AB | | Drain Source Voltage Vds | 30V | | Operating Temperature Max | 175°C | | Continuous Drain Current Id | 93A | | Drain Source On State Resistance | 0.0049ohm | | Gate Source Threshold Voltage Max | 2.5V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:2322578/) ## **Is Now Part of** **To learn more about ON Semiconductor, please visit our website at www.onsemi.com** ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **FDB8896** **==> picture [56 x 39] intentionally omitted <==** **----- Start of picture text -----**
May 2008
tm
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**N-Channel PowerTrench[®] MOSFET 30V, 93A, 5.7m** Ω ## **General Description** This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(ON) and fast switching speed. ## **Features** - rDS(ON) = 5.7mΩ, VGS = 10V, ID = 35A - rDS(ON) = 6.8mΩ, VGS = 4.5V, ID = 35A - High performance trench technology for extremely low rDS(ON) - Low gate charge ## **Applications** - High power and current handling capability - DC/DC converters ||**TO-263AB**
**GATE**
**SOURCE**
**DRAIN**
**(FLANGE)**
\
>
a~~n~~||**G**|||**D**
**S**|||||| |---|---|---|---|---|---|---|---|---|---|---|---| ||FDB SERIES||||||||||| |**MOSFET Maximum Ratings **TC= 25°C unless otherwise noted|||||||||||| |**Symbol**|**Parameter**|||||||**Ratings**|||**Units**| |VDSS|Drain to Source Voltage||||||||30||V| |VGS|Gate to Source Voltage|||||||±20|||V| ||Drain Current||||||||||| ||Continuous (TC= 25oC, VGS= 10V) (Note 1)||||||||93||A| |ID|Continuous (TC= 25oC, VGS= 4.5V) (Note 1)||||||||85||A| ||Continuous (Tamb= 25oC, VGS= 10V, with RθJA= 43oC/W)||||||||19||A| ||Pulsed|||||||Figure 4|||A| |EAS|Single Pulse Avalanche Energy (Note 2)||||||||74||mJ| |PD|Power dissipation
Derate above 25oC|||||||80
0.53|||W
W/oC| |TJ, TSTG|Operating and Storage Temperature|||||||-55 to 175|-55 to 175||oC| |**Thermal Characteristics**|**Thermal Characteristics**||||||||||| |RθJC|Thermal Resistance Junction to Case TO-263|||||||1.88|||oC/W| |RθJA|Thermal Resistance Junction to Ambient TO-263 ( Note 3)||||||||62||oC/W| |RθJA|Thermal Resistance Junction to Ambient TO-263, 1in2copper pad area||||||||43||oC/W| |**Package Marking and Ordering Information**|**Package Marking and Ordering Information**||||||||||| |**Device Marking**
**Device**
**Package**|||**Reel Size**|||**Tape Width**||||**Quantity**|| |FDB8896
FDB8896
TO-263AB|||330mm|||24mm||||800 units|| ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 |**Electrical Characteristics**TC= 25°C unless otherwise noted|**Electrical Characteristics**TC= 25°C unless otherwise noted|**Electrical Characteristics**TC= 25°C unless otherwise noted|**Electrical Characteristics**TC= 25°C unless otherwise noted||||| |---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**||**Min**|**Typ**|**Max**|**Units**| |**Off Characteristics**|||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250µA, VGS|= 0V|30|-|-|V| |IDSS|Zero Gate Voltage Drain Current|VDS= 24V
VGS= 0V||-|-|1|µA| ||||TC= 150oC|-|-|250|| |IGSS|Gate to Source Leakage Current|VGS=±20V||-|-|±100|nA| |**On Characteristics**|||||||| |VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID=|250µA|1.2|-|2.5|V| |rDS(ON)|Drain to Source On Resistance|ID= 35A, VGS= 10V||-|0.0049|0.0057|Ω| |||ID= 35A, VGS= 4.5V||-|0.0059|0.0068|| |||ID= 35A, VGS= 10V,
TJ= 175oC||-|0.0078|0.0094|| |**Dynamic Characteristics**|||||||| |CISS|Input Capacitance|VDS= 15V, VGS= 0V,
f = 1MHz||-|2525|-|pF| |COSS|Output Capacitance|||-|490|-|pF| |CRSS|Reverse Transfer Capacitance|||-|300|-|pF| |RG|Gate Resistance|VGS= 0.5V, f = 1MHz||-|2.3|-|Ω| |Qg(TOT)|Total Gate Charge at 10V|VGS= 0V to 10V||-|48|67|nC| |Qg(5)|Total Gate Charge at 5V|VGS= 0V to 5V||-|25|36|nC| |Qg(TH)|Threshold Gate Charge|VGS= 0V to 1V||-|2.3|3.0|nC| |Qgs|Gate to Source Gate Charge|||-|8|-|nC| |Qgs2|Gate Charge Threshold to Plateau|||-|5.7|-|nC| |Qgd|Gate to Drain “Miller” Charge|||-|9.5|-|nC| |**Switching Characteristics**(VGS= 10V)|||||||| |tON|Turn-On Time|VDD= 15V, ID= 35A
VGS= 4.5V, RGS= 6.2Ω||-|-|167|ns| |td(ON)|Turn-On Delay Time|||-|9|-|ns| |tr|Rise Time|||-|102|-|ns| |td(OFF)|Turn-Off Delay Time|||-|58|-|ns| |tf|Fall Time|||-|44|-|ns| |tOFF|Turn-Off Time|||-|-|153|ns| |**Drain-Source Diode Characteristics**|||||||| |VSD|Source to Drain Diode Voltage|ISD= 35A||-|-|1.25|V| |||ISD= 20A||-|-|1.0|V| |trr|Reverse RecoveryTime|ISD= 35A, dISD/dt = 100A/µs||-|-|27|ns| |QRR|Reverse Recovered Charge|ISD= 35A, dISD/dt = 100A/µs||-|-|12|nC| **Notes:** - **1:** Package current limitation is 80A. - **2:** Starting TJ = 25°C, L = 36µH, IAS = 64A, VDD = 27V, VGS = 10V. **3:** Pulse width = 100s. **4** ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [426 x 572] intentionally omitted <==** **----- Start of picture text -----**
1.2
100
CURRENT LIMITED
1.0 BY PACKAGE
80
0.8 VGS = 10V
60
0.6 VGS = 4.5V
40
0.4
0.2 20
0
0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC, CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)
Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs
Temperature Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t 1
t 2
NOTES:
DUTY FACTOR: D = t 1 /t 2
SINGLE PULSE PEAK TJ = PDM x Z θ JC x R θ JC + TC
0.01
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25 [o] C
FOR TEMPERATURES
TRANSCONDUCTANCE
MAY LIMIT CURRENT ABOVE 25 [o] C DERATE PEAK
IN THIS REGION CURRENT AS FOLLOWS:
I = I25 175 - T C
VGS = 4.5V 150
100
50
10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
, DRAIN CURRENT (A)
ID
POWER DISSIPATION MULTIPLIER
, NORMALIZED
ZJC θ
THERMAL IMPEDANCE
, PEAK CURRENT (A)
IDM
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**Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs Temperature Case Temperature** ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 **==> picture [256 x 12] intentionally omitted <==** **----- Start of picture text -----**
Typical Characteristics TC = 25°C unless otherwise noted
**----- End of picture text -----**
**==> picture [430 x 589] intentionally omitted <==** **----- Start of picture text -----**
1000 500
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
10 µ s If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100 100
100 µ s
STARTING TJ = 25 [o] C
10
OPERATION IN THIS
AREA MAY BE 10
LIMITED BY r DS(ON) 1ms
1
10ms
SINGLE PULSE
TTJC = MAX RATED = 25 [o] C DC STARTING T J = 150 [o] C
0.1 1
1 10 60 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)
Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
160 160
DUTY CYCLE = 0.5% MAXPULSE DURATION = 80 µ s VGS = 10V
VDD = 15V VGS = 5V
120 120
VGS = 4V
TJ = 25 [o] C
80 80
VGS = 3V
40 40
T C = 25 [o] C
TJ = 175 [o] C T J = -55 [o] C DUTY CYCLE = 0.5% MAXPULSE DURATION = 80 µ s
0 0
1.5 2.0 2.5 3.0 3.5 4 0 0.25 0.5 0.75 1.0 1.25 1.5
VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics
14 1.6
PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s
ID = 35A DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
12 1.4
10 1.2
8 1.0
6 0.8
ID = 1A
VGS = 10V, ID = 35A
4 0.6
2 4 6 8 10 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 9. Drain to Source On Resistance vs Gate Figure 10. Normalized Drain to Source On
Voltage and Drain Current Resistance vs Junction Temperature
, DRAIN CURRENT (A)
ID , AVALANCHE CURRENT (A)
IAS
, DRAIN CURRENT (A)ID , DRAIN CURRENT (A)ID
) Ω
, DRAIN TO SOURCE
ON RESISTANCE
ON RESISTANCE (m
rDS(ON)
NORMALIZED DRAIN TO SOURCE
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©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 ## **Typical Characteristics** TC = 25°C unless otherwise noted **==> picture [426 x 360] intentionally omitted <==** **----- Start of picture text -----**
1.2 1.2
VGS = VDS, ID = 250 µ A ID = 250 µ A
1.0
1.1
0.8
1.0
0.6
0.4 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)
Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature
5000 10
CISS = CGS + CGD VDD = 15V
8
1000 COSS ≅ CDS + CGD 6
C RSS = C GD
4
WAVEFORMS IN
2 DESCENDING ORDER:
ID = 35A
VGS = 0V, f = 1MHz ID = 16A
100 0
0 10 20 30 40 50
0.1 1 10 30
VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)
NORMALIZED GATE THRESHOLD VOLTAGE BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
, GATE TO SOURCE VOLTAGE (V)
GS
V
**----- End of picture text -----**
**Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature** **Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant Voltage Gate Current** ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 **==> picture [427 x 204] intentionally omitted <==** **----- Start of picture text -----**
Test Circuits and Waveforms
VDS
BVDSS
L tP
VDS
REQUIRED PEAK IVARY tP TO OBTAINAS RG + VDD IAS VDD
VGS -
DUT
tP
0V IAS
0.01 Ω 0
tAV
Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms
**----- End of picture text -----**
**==> picture [413 x 166] intentionally omitted <==** **----- Start of picture text -----**
VDS
VDD Qg(TOT)
L VDS VGS
VGS = 10V
VGS + Qg(5)
VDD Qgs2 VGS = 5V
-
DUT
Ig(REF) VGS = 1V
0
Qg(TH)
Qgs Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
**----- End of picture text -----**
**==> picture [421 x 160] intentionally omitted <==** **----- Start of picture text -----**
VDS tON tOFF
td(ON) td(OFF)
RL tr tf
VDS
90% 90%
VGS +
- VDD 0 10% 10%
DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0
Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms
**----- End of picture text -----**
©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 ## _**Thermal Resistance vs. Mounting Pad Area**_ The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA ([o] C), and thermal resistance RθJA ([o] C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. **==> picture [194 x 22] intentionally omitted <==** In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. **==> picture [208 x 183] intentionally omitted <==** **----- Start of picture text -----**
80
R θ JA = 26.51+ 19.84/(0.262+Area) EQ.2
R θ JA = 26.51+ 128/(1.69+Area) EQ.3
60
40
20
0.1 1 10
(0.645) (6.45) (64.5)
AREA, TOP COPPER AREA in [2] (cm [2] )
Figure 21. Thermal Resistance vs Mounting
Pad Area
oC/W)(RJA θ
**----- End of picture text -----**
2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RθJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. **==> picture [197 x 70] intentionally omitted <==** ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 ## _**PSPICE Electrical Model**_ .SUBCKT FDB8896 2 1 3 ; rev December 2003 Ca 12 8 2.3e-9 Cb 15 14 2.3e-9 Cin 6 8 2.3e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 33 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.5e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.7e-9 RLgate 1 9 55 RLdrain 2 5 10 RLsource 3 7 27 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.1e-3 Rgate 9 20 2.3 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD **==> picture [319 x 257] intentionally omitted <==** **----- Start of picture text -----**
LDRAIN
DPLCAP 5 DRAIN
2
10
RLDRAIN
RSLC1
51 DBREAK
RSLC2
515 ESLC 11
ESG +- 68 EVTHRES RDRAIN50 16 EBREAK +-1718 DBODY
LGATE EVTEMP + 198 - 21 MWEAK
GATE RGATE + 18 - 6
1 9 20 22 MMED
RLGATE MSTRO
LSOURCE
CIN 8 7 SOURCE3
RSOURCE
RLSOURCE
S1A S2A
12 13 14 15 17 RBREAK 18
8 13
S1B S2B RVTEMP
CA 13+ CB+ 14 IT -19
EGS 68 EDS 58 + VBAT
- - 8
22
RVTHRES
+
-
**----- End of picture text -----**
Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))} .MODEL DbodyMOD D (IS=4E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7 + CJO=8.8e-10 M=0.57 TT=1e-16 XTI=2.2) .MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4) .MODEL MmedMOD NMOS (VTO=1.98 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.3 T_ABS=25) .MODEL MstroMOD NMOS (VTO=2.4 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25) .MODEL MweakMOD NMOS (VTO=1.68 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=23 RS=0.1 T_ABS=25) .MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7) .MODEL RdrainMOD RES (TC1=1.2e-3 TC2=8e-6) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-2.4e-3 TC2=-8.8e-6) .MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2) .ENDS Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 ## _**SABER Electrical Model**_ rev December 2003 template FDB8896 n2,n1,n3 =m_temp electrical n2,n1,n3 number m_temp=25 { var i iscl dp..model dbodymod = (isl=4e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=2.2) dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6) **==> picture [439 x 288] intentionally omitted <==** **----- Start of picture text -----**
dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=1.98,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.4,kp=350,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.68,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) DPLCAP 5 DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) 2
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5) 10 RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2) RSLC1
c.ca n12 n8 = 2.3e-9 51
RSLC2
c.cb n15 n14 = 2.3e-9
c.cin n6 n8 = 2.3e-9 ISCL
dp.dbody n7 n5 = model=dbodymoddp.dbreak n5 n11 = model=dbreakmoddp.dplcap n10 n5 = model=dplcapmod ESG +- 68 EVTHRES RDRAIN50 16 DBREAK11 DBODY
spe.ebreak n11 n7 n17 n18 = 33spe.eds n14 n8 n5 n8 = 1spe.egs n13 n8 n6 n8 = 1 GATE1 RLGATELGATE 9RGATE20EVTEMP+ 1822 - 6 + 198 - MSTRO21 MMED MWEAKEBREAK+17
spe.esg n6 n10 n6 n8 = 1spe.evthres n6 n21 n19 n8 = 1spe.evtemp n20 n6 n18 n22 = 1 CIN 8 -18 7 LSOURCE SOURCE3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A S2A
l.lgate n1 n9 = 5.5e-9 12 138 1413 15 17 RBREAK 18
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.7e-9 S1B S2B RVTEMP
res.rlgate n1 n9 = 55res.rldrain n2 n5 = 10 CA EGS13+68 EDSCB+ 58 14 IT +-19VBAT
res.rlsource n3 n7 = 27 - - 8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp RVTHRES
**----- End of picture text -----**
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7 res.rdrain n50 n16 = 2.1e-3, tc1=1.2e-3,tc2=8e-6 res.rgate n9 n20 = 2.3 res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-2.4e-3,tc2=-8.8e-6 res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10)) } } ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 _**PSPICE Thermal Model**_ **th JUNCTION** REV 23 December 2003 FDB8896T CTHERM1 TH 6 9e-4 CTHERM2 6 5 1e-3 CTHERM3 5 4 2e-3 **RTHERM1 CTHERM1** CTHERM4 4 3 3e-3 CTHERM5 3 2 7e-3 CTHERM6 2 TL 8e-2 **6** RTHERM1 TH 6 3.0e-2 RTHERM2 6 5 1.0e-1 RTHERM3 5 4 1.8e-1 **RTHERM2 CTHERM2** RTHERM4 4 3 2.8e-1 RTHERM5 3 2 4.5e-1 RTHERM6 2 TL 4.6e-1 **5** _**SABER Thermal Model**_ SABER thermal model FDB8896T template thermal_model th tl **RTHERM3 CTHERM3** thermal_c th, tl { ctherm.ctherm1 th 6 =9e-4 ctherm.ctherm2 6 5 =1e-3 **4** ctherm.ctherm3 5 4 =2e-3 ctherm.ctherm4 4 3 =3e-3 ctherm.ctherm5 3 2 =7e-3 **RTHERM4 CTHERM4** ctherm.ctherm6 2 tl =8e-2 rtherm.rtherm1 th 6 =3.0e-2 rtherm.rtherm2 6 5 =1.0e-1 **3** rtherm.rtherm3 5 4 =1.8e-1 rtherm.rtherm4 4 3 =2.8e-1 rtherm.rtherm5 3 2 =4.5e-1 **RTHERM5 CTHERM5** rtherm.rtherm6 2 tl =4.6e-1 } **2 RTHERM6 CTHERM6 tl CASE** ©2008 Fairchild Semiconductor Corporation FDB8896 Rev. B2 ## **TRADEMARKS** The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. ACEx[®] FPS™ PDP-SPM™ The Power Franchise[®] Build it Now™ F-PFS™ Power-SPM™ the wer CorePLUS™ FRFET[®] PowerTrench[®] Paw tm CorePOWER™ Global Power Resource[SM] Programmable Active Droop™ TinyBoost™ _CROSSVOLT_ ™ Green FPS™ QFET[®] TinyBuck™ CTL™ Green FPS™ e-Series™ QS™ TinyLogic[®] Current Transfer Logic™ GTO™ Quiet Series™ TINYOPTO™ EcoSPARK[®] IntelliMAX™ RapidConfigure™ TinyPower™ EfficentMax™ ISOPLANAR™ Saving our world 1mW at a time™ TinyPWM™ EZSWITCH™ * MegaBuck™ SmartMax™ TinyWire™ ™ MICROCOUPLER™ SMART START™ µSerDes™ MicroFET™ SPM[®] ® MicroPak™ STEALTH™ ~~-~~ "ZZ... Fairchild[®] MillerDrive™ SuperFET™ UHC[®] Fairchild Semiconductor[®] MotionMax™ SuperSOT™-3 Ultra FRFET™ FACT Quiet Series™ Motion-SPM™ SuperSOT™-6 UniFET™ FACT[®] OPTOLOGIC[®] SuperSOT™-8 VCX™ FAST[®] OPTOPLANAR[®] SuperMOS™ VisualMax™ FastvCore™ ® ® FlashWriter[® ] * tm Te ceNeRAL * EZSWITCH™ and FlashWriter[®] are trademarks of System General Corporation, used under license by Fairchild Semiconductor. ## **DISCLAIMER** FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. **LIFE SUPPORT POLICY** FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, 2. A critical component in any component of a life support, (a) are intended for surgical implant into the body or (b) device, or system whose failure to perform can be reasonably support or sustain life, and (c) whose failure to perform when expected to cause the failure of the life support device or properly used in accordance with instructions for use provided system, or to affect its safety or effectiveness. in the labeling, can be reasonably expected to result in a significant injury of the user. ## **PRODUCT STATUS DEFINITIONS Definition of Terms** |**Definition of Terms**||| |---|---|---| |**Datasheet Identification**|**Product Status**|**Definition**| |Advance Information|Formative or In Design|This datasheet contains the design specifications for product development.
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