# TVS Diode, ESDA1, 10 V, 16.5 V, SOD-523, 2 Pins

![Product image](https://novapart.co/image/farnell:1889332/)

**URL**: https://novapart.co/products/ESDA12-1K/tvs-diode-esda1-10-v-165-sod-523-2-pins
**SKU**: ESDA12-1K
**Manufacturer**: STMICROELECTRONICS
**Category**: Circuit Protection || TVS - Transient Voltage Suppressors || TVS Diodes
**Price**: €0.0570
**Stock**: 1000+
**Lead Time**: 120 days (indicative)

## Description

Product Range:ESDA1 Series; TVS Polarity:-; Reverse Stand-Off Voltage Vrwm:10V; Clamping Voltage Vc Max:16.5V; Diode Case Style:SOD-523; No. of Pins:2Pins; Breakdown Voltage Min:-; Bre

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 2Pins |
| Tvs Polarity | - |
| Product Range | ESDA1 |
| Diode Case Style | SOD-523 |
| Clamping Voltage Max | 16.5V |
| Reverse Standoff Voltage | 10V |
| Maximum Breakdown Voltage | - |
| Minimum Breakdown Voltage | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:1889332/)

## **ESDA-1K** 

## EOS and ESD Transil™ protection for charger and battery port 

## **Features** 

- Breakdown voltage: 12 V, 18 V 

- Unidirectional device 

- High peak power dissipation: 450 W (8/20 µs waveform) 

- ESD protection level better than IEC 61000-4-2 level 4: 30 kV contact discharge. 

- Low leakage current < 0.5 µA at 5 V 

- PCB area: 1.3 mm[2] 

## **Benefits** 

- High EOS and ESD protection level 

- High integration 

- Suitable for high density board 

- Small package 

## **Complies with the following standards** 

**==> picture [38 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOD-523<br>**----- End of picture text -----**<br>


## **Figure 1. Functional diagram** 

**==> picture [56 x 130] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin 1<br>Pin 2<br>**----- End of picture text -----**<br>


- IEC 61000-4-2 level 4 

   - 15 kV (air discharge) 

   - 8 kV (contact discharge) 

- MIL STD 883G - Method 3015-7 Class 3B – HBM (Human Body Model): ≥ 8 kV 

## **Applications** 

## **Description** 

The ESDA-1K is a single line Transil diode designed specifically for the protection of integrated circuits in portable equipment and miniaturized electronics devices subject to ESD and EOS transient overvoltages. 

Where transient overvoltage protection in ESD sensitive equipment is required, such as: 

- Computers 

- Printers 

- Communication systems 

- Cellular phone handsets and accessories 

- Video equipment 

**TM** : Transil is a trademark of STMicroelectronics. 

September 2010 

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Doc ID 17883 Rev 1 

_www.st.com_ 

**Characteristics** 

**ESDA-1K** 

## **1 Characteristics** 

## **Table 1. Absolute maximum ratings (Tamb = 25 °C)** 

|**Symbol**|**Parameter**|**Parameter**|**Value**|**Unit**<br>kV<br>°C<br>°C<br>°C|
|---|---|---|---|---|
|VPP|Peak pulse voltage<br>I<br>I|EC 61000-4-2 air discharge<br>EC 61000-4-2 contact discharge|30<br>30||
|Tj|Operating Junction temperature rage||-40 to +150||
|Tstg|Storage temperature range||-65 to +150||
|TL|Maximum lead temperature for soldering during 10 s||260||



0 **Table 2. Absolute maximum ratings (tamb = 25 °C) - product specific parameters** 

|**Order code**|**IPP(A) peak pulse current (8/20 µs) **|**PPP(W) peak pulse power (8/20 µs)**|
|---|---|---|
|ESDA12-1K|16|450|
|ESDA18-1K|12|400|



## **Figure 2. Electrical characteristics (definitions)** 

**Symbol                Parameter** 

**==> picture [88 x 116] intentionally omitted <==**

**==> picture [65 x 108] intentionally omitted <==**

## **Table 3. Electrical characteristics (values, Tamb = 25 °C)** 

|**Order code**|**VBR @ IR**<br>**Min.**<br>**Typ.**<br>**V**<br>**V**<br>**mA**|**VBR @ IR**<br>**Min.**<br>**Typ.**<br>**V**<br>**V**<br>**mA**|**VBR @ IR**<br>**Min.**<br>**Typ.**<br>**V**<br>**V**<br>**mA**|**IRM @ VRM**|**IRM @ VRM**|**VCL@ IPP (8/20 µs)**|**VCL@ IPP (8/20 µs)**|**VCL@ IPP (8/20 µs)**|**VCL@ IPP (8/20 µs)**|**Cline**<br>**(1)**|
|---|---|---|---|---|---|---|---|---|---|---|
|||**Typ.**||**Max.**||**Max.**||**Max.**||**Max.**|
|||**V**|**mA**|**µA**|**V**|**V**|**A**|**V**|**A**|**pF**|
|ESDA12-1K|12|13|1|0.5|10|16.5|1|28|16|150|
|ESDA18-1K|18|19|1|0.5|15|24|1|34|12|105|



1. VR = 0 V, Fosc = 1 MHz, Vosc = 30 mV 

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**ESDA-1K** 

**Characteristics** 

## **Figure 3. Peak pulse power dissipation versus exponential pulse duration (typical values)** 

**Figure 4. Peak pulse power dissipation versus initial junction temperature (typical values)** 

**==> picture [442 x 319] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000 PPP(W) 1000 PPP(W)<br>8/20 µs<br>SS a  S ESDA12-1K ee Tj=25 °C 900 ee ee<br>800<br>ESDA18-1K<br>700<br>100 = ieAS = nna a ESDA12-1K e e<br>600<br>500 ESDA18-1K<br>SSS Se 400 =<br>10<br>eee 300 ee<br>200<br>po L 100 es ee ee ee<br>1 PC et tP(µs) 0 a Tj (°C)<br>10 100 1000 25 50 75 100 125 150 175<br>Clamping voltage versus peak  Figure 6. Leakage current versus junction<br>pulse current (typical values)ulse current (typical values)(typical values)typical values)ypical values)ical values)) temperature (typical values)<br>100.0 IPP (A) 100.00 IR (nA)<br>8/20 µs VR = VRM = 10 V for ESDA12-1K<br>SSS T initial = 25 °Cj VR = VRM =1 5V for  ESDA18-1K<br>ee ee SSee — eee —<br>[| a ee<br>10.0 ESDA12-1K<br>e e _ ESDA12-1K<br>1.00<br>ee ny Aan Aa a<br>a | ee ee ————————————<br>1.0 ESDA18-1K ESDA18-1K<br>[iLs ——— a<br>0.1 | VCL (V) 0.01 Po Tj (°C)<br>0 10 20 30 25 35 45 55 65 75 85<br>**----- End of picture text -----**<br>


## **Figure 5. Clamping voltage versus peak pulse current (typical values)ulse current (typical values)(typical values)typical values)ypical values)ical values))** 

**Figure 7. ESD response to IEC 61000-4-2 (+15 kV air discharge) ESDA12-1K** 

**Figure 8. ESD response to IEC 61000-4-2 (-15 kV air discharge) ESDA12-1K** 

**==> picture [440 x 128] intentionally omitted <==**

**----- Start of picture text -----**<br>
5 V / div 5 V / div<br>C2<br>/<br>C2<br>100 ns / div 100 ns / div<br>**----- End of picture text -----**<br>


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**Ordering information scheme** 

**ESDA-1K** 

## **2 Ordering information scheme** 

**==> picture [198 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 9. Ordering information scheme<br>**----- End of picture text -----**<br>


**==> picture [267 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
ESDA      XX    -    1K<br>ESD array<br>Breakdown voltage<br>XX = 12: 12 V min.<br>XX = 18: 18 V min.<br>Package<br>1 = 1 line<br>K = SOD-523<br>**----- End of picture text -----**<br>


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**ESDA-1K** 

**Package information** 

## **3 Package information** 

- Epoxy meets UL94,V0 

- Lead-free package 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK[®] is an ST trademark. 

|**Table 4.**|**Table 4.**|**Table 4.**|**Table 4.**|**SOD-523 dimensions**|**SOD-523 dimensions**|**SOD-523 dimensions**|**SOD-523 dimensions**|**SOD-523 dimensions**|**SOD-523 dimensions**||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**SEATING PLAN**|||||||||**R0.1**<br>**c**<br>**8°**<br>**7°**<br>**D**<br><br>**B**<br>**A**<br>**L1**|**Ref.**|**Dimensions**||||||
||||||||||||**Millimeters**|||**Inches**|||
||<br>**A**|**2xb**||||**E1**<br>**E**<br>**0.15**<br>**C**<br>**A**<br>**B**<br>**M**|**015**<br>**M**|**C**<br>**A**<br>**B**|||||||||
||||||||||||||||||
||||||||||||**Min.**|**Typ.**|**Max.**|**Min.**|**Typ.**|**Max.**|
|||||||||||A|0.50|0.60|0.70|0.020|0.024|0.028|
||||||||||||||||||
|||||||||||E|1.50|1.60|1.70|0.059|0.063|0.067|
||||||**0.20**|**C**<br>**A**<br>**B**<br>**M**||||E1|1.10|1.20|1.30|0.043|0.047|0.051|
||||||||||||||||||
|||||||||||D|0.70|0.80|0.90|0.028|0.031|0.035|
||<br>|**C**||||**L**||||b|0.25||0.35|0.010||0.014|
|||||||||||c|0.07||0.20|0.003||0.008|
||||||||||||||||||
|||||||||||L|0.15|0.20|0.25|0.006|0.008|0.010|
||||||||||||||||||
|||||||||||L1|0.05||0.20|0.002||0.008|



**Figure 10. Footprint (dimensions in mm) Figure 11. Marking** 

**==> picture [462 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.7<br>0.3<br>1X<br>Pin 1 Pin 2<br>2<br>**----- End of picture text -----**<br>


_Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose._ 

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**ESDA-1K** 

**Package information** 

**==> picture [461 x 239] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 12. Tape and reel specification<br>Ø 1.50<br>2.0 4.10<br>0.22<br>0.50 0.90 4.0<br>0.73<br>All dimensions are typical values in mm User direction of unreeling<br>1.75<br>1.35 3.5<br>8.0<br>**----- End of picture text -----**<br>


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**ESDA-1K** 

**Recommendation on PCB assembly** 

## **4 Recommendation on PCB assembly** 

## **4.1 Solder paste** 

1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 

2. “No clean” solder paste recommended. 

3. Offers a high tack force to resist component displacement during PCB movement. 

4. Use solder paste with fine particles: powder particle size 20-45 µm. 

## **4.2 Placement** 

1. Manual positioning is not recommended. 

2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 

3. Standard tolerance of ± 0.05 mm is recommended. 

4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 

5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 

## **4.3 PCB design preference** 

1. To control the solder paste amount, the closed via is recommended instead of open vias. 

2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 

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**Recommendation on PCB assembly** 

**ESDA-1K** 

## **4.4 Reflow profile** 

**Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting** 

**==> picture [342 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
Temperature (°C)<br>260°C max<br>255°C<br>220°C<br>180°C<br>125 °C 2°C/s recommended2°C/s recommended<br>3°C/s max 6°C/s max<br>6°C/s max<br>3°C/s max<br>0<br>0 1 2 3 4 5 6 7<br>10-30 sec Time (min)<br>90 to 150 sec 90 sec max<br>**----- End of picture text -----**<br>


_Note: Minimize air convection currents in the reflow oven to avoid component movement._ 

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**ESDA-1K** 

**Ordering information** 

## **5 Ordering information** 

**Table 5. Ordering information** 

|**Order code**|**Marking**|**Package**|**Weight**|**Base qty**|**Delivery mode**|
|---|---|---|---|---|---|
|ESDA12-1K|12|SOD-523|1.46|3000|Tape and reel|
|ESDA18-1K|18|||||



_Note:_ 

_The marking can be rotated by multiples of 90° to differentiate assembly location._ 

## **6 Revision history** 

|**Table 6.**<br>**Document revision history**|**Table 6.**<br>**Document revision history**|**Table 6.**<br>**Document revision history**|
|---|---|---|
|**Date**|**Revision**|**Changes**|
|02-Sep-2010|1|First issue.|



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