# EMI Filter, 8-Channel, ESD Protection, 400 MHz, µQFN-16

![Product image](https://novapart.co/image/farnell:3130035RL/)

**URL**: https://novapart.co/products/EMIF08-LCD04M16/emi-filter-8-channel-esd-protection-400-mhz-qfn-16
**SKU**: EMIF08-LCD04M16
**Manufacturer**: STMICROELECTRONICS
**Price**: €0.2890
**Stock**: 1000+
**Lead Time**: 106 days (indicative)

## Description

EMI Filter Type:EMI Filter with ESD Protection; No. of Data Lines:8 Data Lines; Filter Circuit:C-L-C Pi Filter; Filter Case Style:µQFN; No. of Pins:16Pins; Product Range:-; SVHC:No

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 16Pins |
| Product Range | EMIF Series |
| Filter Circuit | C-L-C Pi Filter |
| Emi Filter Type | EMI Filter with ESD Protection |
| No. Of Data Lines | 8 Data Lines |
| Filter Case / Package | µQFN |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3130035RL/)

**EMIF08-LCD04M16** 

**==> picture [61 x 39] intentionally omitted <==**

## 8-line L-C IPAD™, EMI filter and ESD protection in  Micro QFN 

## **Features** 

- High cut off frequency  low-pass filter: FC = 400 MHz at -6 dB 

- High efficiency in EMI filtering: better than -35 dB from 900 MHz to 2 GHz 

- Very low PCB space consuming with plastic micro-package 3.3 x 1.35 mm 

**==> picture [84 x 50] intentionally omitted <==**

**Micro QFN 3.3 x 1.35 16L** 

- Very thin package: 0.55 mm 

- High efficiency in ESD (IEC 61000-4-2 level 4) 

## **Figure 1. Device configuration** 

- High reliability offered by monolithic integration 

- High reducing of parasitic elements through integration 

- ECOPACK[®] 2 compliant component 

## **Complies with the following standards** 

- IEC 61000-4-2 level 4: 

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**----- Start of picture text -----**<br>
Low-pass Filter<br>0 0 0 0<br>Input Output<br>GND GND GND<br>**----- End of picture text -----**<br>


- 15 kV (air discharge) 

- 8 kV (contact discharge) 

## **Applications** 

Where EMI filtering in ESD sensitive equipment is required: 

- 

## **Description** 

The EMIF08-LCD04M16 is a 8-line inductorcapacitor (LC) EMI filter designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences requiring a large bandwidth. 

- 

- 

- MCU boards 

This filter includes an ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up 15 kV contact discharge. 

**TM** : IPAD is a trademark of STMicroelectronics. 

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Doc ID 15673 Rev 2 

_www.st.com_ 

**EMIF08-LCD04M16** 

**Electrical characteristics** 

## **1 Electrical characteristics** 

## **Table 1. Absolute maximum ratings (Tamb = 25 °C)** 

|**Table 1.**|**Absolute maximum ratings (Tamb= 25 °C)**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Value**|**Unit**|
|VPP|ESD discharge IEC 61000-4-2, contact discharge|± 15|kV|
|Top|Operating temperature  range|-40 to 85|°C|
|Tj|Maximum junction temperature|125|°C|
|Tstg|Storage temperature range|-55 to 150|°C|



## **Figure 2. Electrical characteristics (definitions)** 

||**Symbol**<br>**Parameter**<br>V<br>=<br>Breakdown voltage<br>I<br>=<br>Leakage current @ V<br>V<br>=<br>Stand-off voltage<br>V<br>=<br>Clamping voltage<br>R<br>=<br>Dynamic impedance<br>I<br>=<br>Peak pulse current<br>I<br>=<br>Breakdown current<br>T<br>=<br>Voltage temperature coefficient<br>V<br>=<br>Forward voltage drop<br>BR<br>RM<br>RM<br>RM<br>CL<br>d<br>PP<br>R<br>F<br>α|**VCLVBR VRM**<br>**IRM**<br>**IR**<br>**IPP**<br>**I**<br>**IF**<br>**V**|**VCLVBR VRM**<br>**IRM**<br>**IR**<br>**IPP**<br>**I**<br>**IF**<br>**V**||
|---|---|---|---|---|
||||||



## **Table 2. Electrical characteristics (Tamb = 25 °C)** 

|**Table 2.**|**Electrical characteristics(Tamb= 25 °C)**|||||
|---|---|---|---|---|---|
|**Symbol**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|VBR|IR= 1 mA|6|-|-|V|
|IRM|VRM= 3 V per line|-|-|100|nA|
|L|Inductance|-|12|-|nH|
|Cline|VR= 3 V DC, F = 1 MHz, Vosc= 30 mV|17|18|19|pF|
|R|Parasitic resistance of the inductance|9|12.5|20|Ω|
|FC|50Ωsource  and 50Ωload termination at -6 dB|-|400|-|MHz|



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**EMIF08-LCD04M16** 

**Electrical characteristics** 

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**----- Start of picture text -----**<br>
Figure 3. S21 attenuation measurements  Figure 4. Analog crosstalk measurements<br>0 [dB] —— dB<br>-5 Co Te ATT) |) 2° gq ooo otooon<br>-10<br>-15 PEATPT TTTTTI TTII TITIE PNTNIT)TT | 3S q8 HisSIS 0283 ——re FC Te<br>-20<br>-25 Se ee ee seat ee e e E at<br>-30 PIN] a ee/\ N ae<br>-35 Pr | 3 0<br>CCCINIE CTI TTICOTO | 2 0 eeMH<br>-40 pei I2 [-] O2 #1<br>-45 al I3 - O3 #1 LIENTIL LIM LT | 82 0° EETea eea ee<br>-50 || I5I4 -- O5 #1O4 #1 NI | 4 00 UE a a<br>-55 ll I6 [-] O6 #1 TNIE [TT] 1 10, eile tial IMME ITE<br>-60-65-70 Fo||Tm I7I8 - [-] O7 #1O8 #1 LL LITE} F/Hz TW)|} | 2as oLLily30aod0 LET) TearHH TUTTITEATTT PyITIneTET F/Hz TTT]<br>100k 1M 10M 100M 1G 100k 1M 10M 100M 1G<br>Figure 5. ESD response to IEC 61000-4-2  Figure 6. ESD response to IEC 61000-4-2<br>(+15 kV air discharge)+15 kV air discharge)ge)e)) (-15 kV air discharge)-15 kV air discharge)ge)e))<br>5V/Div 5V/Div<br>C2<br>{ I, a IN<br>IN<br>| *<br>C2 eae } “-<br>C3 OUT<br>aes a ee OUT  ROR EE SE CONE<br>C3 errenes! 2V/Div 2V/Div<br>**----- End of picture text -----**<br>


**Figure 5. ESD response to IEC 61000-4-2 Figure 6. ESD response to IEC 61000-4-2 (+15 kV air discharge)+15 kV air discharge)ge)e)) (-15 kV air discharge)-15 kV air discharge)ge)e))** 

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Figure 7. Line capacitance versus applied voltage<br>C(pF)<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>VR(V)<br>0<br>0 1 2 3 4 5<br>FF<br>ky Doc ID 15673 Rev 2 3/10<br>**----- End of picture text -----**<br>


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**Ordering information scheme** 

**EMIF08-LCD04M16** 

## **2 Ordering information scheme** 

## **Figure 8. Ordering information scheme** 

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**----- Start of picture text -----**<br>
EMIF     yy     -     xxxzz     Mxx<br>EMI Filter<br>Number of lines<br>Information<br>xxx = application<br>zz = version<br>Package<br>Mxx = Micro QFN - xx leads<br>**----- End of picture text -----**<br>


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**EMIF08-LCD04M16** 

**Package information** 

## **3 Package information** 

- Epoxy meets UL94, V0 

- Lead-free package 

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: www.st.com. ECOPACK[®] is an ST trademark. 

## **Table 3. Micro QFN 3.3x1.35 16L dimensions** 

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**----- Start of picture text -----**<br>
Dimensions<br>TOP VIEW<br>D<br>Ref. Millimeters Inches<br>INDEX AREA<br>(D/2 x E/2) E Min. Typ. Max. Min. Typ. Max.<br>A 0.45 0.50 0.55 0.018 0.020 0.022<br>A1 0.00 0.02 0.05 0.00 0.0008 0.002<br>SIDE VIEW<br>A A1 b 0.15 0.20 0.25 0.006 0.008 0.010<br>D - 3.30 - - 0.13 -<br>BOTTOM VIEW<br>e b D2 2.65 2.80 2.90 0.104 0.110 0.114<br>INDEX AREA<br>(D/2 x E/2) 1 8 EXPOSED PAD E - 1.35 - - 0.053 -<br>PIN # 1 ID E2 0.25 0.40 0.50 0.010 0.016 0.020<br>E2<br>e - 0.40 - - 0.016 -<br>16 D2 9 K k 0.20 - - 0.008 - -<br>L<br>L 0.15 0.25 0.35 0.006 0.010 0.014<br>Figure 9. Footprint Figure 10. Marking<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
0.40<br>0.20<br>0.45<br>Dot: Pin 1<br>0.40 0.85 1.75 XX XX: Marking<br>WW WW: Assembly week<br>Y: Assembly year<br>Y P<br>2.80 P: Assembly plant<br>3.00<br>**----- End of picture text -----**<br>


_Note: Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose._ 

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**Recommendation on PCB assembly** 

**EMIF08-LCD04M16** 

## **4 Recommendation on PCB assembly** 

## **4.1 Stencil opening design** 

1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). 

## **Figure 11. Stencil opening dimensions** 

**==> picture [99 x 65] intentionally omitted <==**

**----- Start of picture text -----**<br>
L<br>T<br>W<br>**----- End of picture text -----**<br>


- b) General design rule 

Stencil thickness (T) = 75 ~ 125 µm 

W Aspect Ratio = ≥ 1.5[-----] T Aspect Area = --------------------------L × W **-** ≥ 0.66 2T(L + W) 

2. Reference design 

   - a) Stencil opening thickness: 100 µm 

   - b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%. 

   - c) Stencil opening for leads: Opening to footprint ratio is 90%. 

## **Figure 12. Recommended stencil window position** 

**==> picture [331 x 240] intentionally omitted <==**

**----- Start of picture text -----**<br>
4 µm 4 µm<br>14 µm<br>T=100 µm<br>192 µm<br>14<br>200 µm<br>µm<br>2800 µm<br>60 µm<br>400 µm<br>2000 µm Footprint<br>60 µm Stencil window<br>400 µm 400 µm Footprint<br>450 µm 422 µm<br>280 µm<br>**----- End of picture text -----**<br>


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**EMIF08-LCD04M16** 

**Recommendation on PCB assembly** 

## **4.2 Solder paste** 

1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 

2. “No clean” solder paste is recommended. 

3. Offers a high tack force to resist component movement during high speed. 

4. Solder paste with fine particles: powder particle size is 20-45 µm. 

## **4.3 Placement** 

1. Manual positioning is not recommended. 

2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 

3. Standard tolerance of ± 0.05 mm is recommended. 

4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 

5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 

## **4.4 PCB design preference** 

1. To control the solder paste amount, the closed via is recommended instead of open vias. 

2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 

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**Recommendation on PCB assembly** 

**EMIF08-LCD04M16** 

## **4.5 Reflow profile** 

**Figure 13. ST ECOPACK[®] recommended soldering reflow profile for PCB mounting** 

**==> picture [342 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
Temperature (°C)<br>260°C max<br>255°C<br>220°C<br>180°C<br>125 °C 2°C/s recommended2°C/s recommended<br>3°C/s max 6°C/s max<br>6°C/s max<br>3°C/s max<br>0<br>0 1 2 3 4 5 6 7<br>10-30 sec Time (min)<br>90 to 150 sec 90 sec max<br>**----- End of picture text -----**<br>


_Note: Minimize air convection currents in the reflow oven to avoid component movement._ 

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**EMIF08-LCD04M16** 

**Ordering information** 

## **5 Ordering information** 

**Table 4. Ordering information** 

|**Table 4.**<br>**Ordering **|**information**|||||
|---|---|---|---|---|---|
|**Order code**|**Marking**|**Package**|**Weight**|**Base qty**|**Delivery mode**|
|EMIF08-LCD04M16|JA(1)|µQFN|6.74 mg|3000|Tape and reel|



1. The marking can be rotated by 90° to differentiate assembly location 

## **6 Revision history** 

## **Table 5. Document revision history** 

|**Date**|**Revision**|**Changes**|
|---|---|---|
|20-May-2009|1|Initial release.|
|10-Nov-2009|2|Updated_Features on page 1_. Added_Figure 2 on page 2_.|



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