# EMI Filter, 7 V, 100 Ω, 50 pF, SOT323-5

![Product image](https://novapart.co/image/farnell:2629722RL/)

**URL**: https://novapart.co/products/EMIF01-10005W5/emi-filter-7-v-100-50-pf-sot323-5
**SKU**: EMIF01-10005W5
**Manufacturer**: STMICROELECTRONICS
**Category**: Passive Components || Filters || Integrated Passive Filters
**Price**: €0.1580
**Stock**: 10+
**Lead Time**: 127 days (indicative)

## Description

EMI Filter Type:EMI Filter with ESD Protection; No. of Data Lines:2 Data Lines; Filter Circuit:RC Pi Filter; Filter Case Style:SOT323; No. of Pins:5Pins; Product Range:-; SVHC:No SVHC

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 5Pins |
| Product Range | EMIF Series |
| Filter Circuit | RC Pi Filter |
| Emi Filter Type | EMI Filter with ESD Protection |
| No. Of Data Lines | 2 Data Lines |
| Filter Case / Package | SOT323 |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2629722RL/)

## Ky/ Application Specific Discretes A.S.D.™ 

## EMIFO1-10005W5 EMI FILTER INCLUDING ESD PROTECTION 

## MAIN APPLICATIONS 

Where EMI filtering in ESD sensitive equipment is required : 

- a Computers and printers 

- a Communication systems 

- a Mobile phones mg MCU Boards 

## DESCRIPTION 

> ThedesignedEMIF01-10005W5to suppress EMIi ; RELhighly noiseint in alltedsystems subjected to electromagnetic interferences. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. 

BENEFITS a EMI bi-directional low-pass filter a Cost-effectiveness compared to discrete solution 

- a High efficiency in ESD suppression. 

- a High flexibility in the design of high density boards m Very low PCB space consuming : 4.2 mm? typically m High reliability offered by monolithic integration 

COMPLIES WITH THE FOLLOWING STANDARD: IEC 1000-4-2. 15kV_—_ (air discharge) 8kV (contact discharge) 

## ESD response to IEC1000-4-2 (16 kV air discharge) 

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SOT323-5L<br>**----- End of picture text -----**<br>


## FUNCTIONAL DIAGRAM 

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## Filtering response 

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EMIF01-10005W5 

## ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C) 

Parameterandteatconaiions [Symiot | ‘| vee ——~[ ‘Unk ESD discharge IEC1000-4-2, contact discharge 9 

## ELECTRICAL CHARACTERISTICS (Tamb = 25 °C) 

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ew | eakagecoren@ vin<br>and Output<br>**----- End of picture text -----**<br>


[Symiot[_Testeondtons———*] [ Cve win Tym | won | Unt SS™~—SsSSC‘YSCédT owa **[** mimve SSSC=~—s CT Tl+} J a Fs [Apoaeemey —~«| —t t |i) a 0 Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5 

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EMIFO1-10005W5 

## TECHNICAL INFORMATION 

## FREQUENCY BEHAVIOR 

The EMIF01-10005W5is firstly designed as an EMI/RFI parameters: 

filter. This low-pass filter is characterized by the following 

- Cut-off frequency 

- Insertion loss 

- High frequency rejection 

Fig A1: EMIF01-10005W5 frequency response curve. 

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dB<br>‘TTT<br>PaSC<br>A<br>oo} INTE ETI ENTIT<br>PUTIN TAIN WalTEN<br>-30 1INE10 comes100 TT1000 2000|<br>**----- End of picture text -----**<br>


Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about -24dB at 900MHz, 

Fig A2: Measurement conditions 

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TRACKING GENERATOR SPECTRUM ANALYSER<br>TEST BOARD<br>500 woh oe<br>Vo . 500<br>**----- End of picture text -----**<br>


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## EMIF0O1-10005W5 

## ESD PROTECTION 

In addition to its filtering function, the EMIFO1-10005W5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at : 

## Ve = Ver + Ra.|PpP 

This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. 

## Fig A3 : ESD clamping behavior 

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Rg Re<br>|__| OF LO<br>Sur Vg C ) Vin |je ele ey | Vout | Rload<br>EMIFO1-10005W5 Device to be protected<br>**----- End of picture text -----**<br>


To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical resistance value Rd. By taking into account these following hypothesis : R>>Rd, Ra>>Rd and Rload>>Rd, it gives these formulas: 

Vin=.[Oe] Ag.2 Vbr+Rad.brvRa! VivgVg Rg Vout[=][———.——_] R.Vbr+Ra. Vin R 

The results of the calculation done for Vqg=8kV, Rq=330Q (IEC 1000-4-2 standard) and VBR=7V (typ.) give: 

## Vin =31.2V 

## Vout = 7.3 V 

This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R. 

Fig A4 : Measurement conditions 

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EMIFO1-10005W5 

The measurements shown here after illustrate very clearly (Fig. A5a) the high efficiency of the ESD protection : - no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to Vgr 

## Fig A5 : Remaining voltage at both stages $1 (Vin) and S2 (Vout) during ESD surge 

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1 1<br>10.0 , V 310.0 a il !<br>erme |eGR aGaee el eT aoe |<br>eo | fed |imu]| | 2 se- |ilope tt | 4 ituel fn||<br>_ eee Peer<br> fe ro—j |ga|feureree ren oe ree|meres | wee<br>a) Positive surge b) Negative surge<br>note that the EMIF01-10005W5 is not only acting Fig A6 : Rd measurement current wave<br>positive ESD surges but also for negative ones. For<br>kind of disturbances it clamps close to ground I<br>as shown in Fig. ASb.<br>DYNAMIC RESISTANCE MEASUREMENT RESISTANCE MEASUREMENT MEASUREMENT rePim<br> value of the dynamic the dynamic dynamic resistance remains stable for Yon t<br>duration lower than 20us, the 2.5us rectangular 2us<br>is well adapted. In addition both rise and fall times j____2.5us|<br>optimized to avoid any parasitic phenomenon during<br>measurement of Rd. 2.5us duration measurement wave<br>**----- End of picture text -----**<br>


Please note that the EMIF01-10005W5 is not only acting for positive ESD surges but also for negative ones. For these kind of disturbances it clamps close to ground voltage as shown in Fig. ASb. 

NOTE: DYNAMIC RESISTANCE MEASUREMENT RESISTANCE MEASUREMENT MEASUREMENT As the value of the dynamic the dynamic dynamic resistance remains stable for a surge duration lower than 20us, the 2.5us rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. 

ky 

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EMIF01-10005W5 

## CROSSTALK BEHAVIOR 

## 1- Crosstalk phenomena 

Fig A7 : Crosstalk phenomena 

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| Ret line  12 Ru 011Ve1 +B2Ve2<br>Ver<br>- | Ri2 | | 05Vg2 + Bo<br>"DRIVERS "RECEIVERS-<br>**----- End of picture text -----**<br>


## 2- Digital Crosstalk 

Fig A8 : Digital crosstalk measurement 

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+5V +5V<br>| aoe LOG<br>**----- End of picture text -----**<br>


Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure AQ shows that in such a condition signal from 0 to 5V and rise time of 3 ns, the impact on the disturbed line is less than 100mV peak to peak. No data disturbance was noted on the concerned line. The same results were obtained with falling edges. 

Fig A9 : Digital crosstalk results 

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EMIFO1-10005W5 

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3- Analog Crosstalk<br>**----- End of picture text -----**<br>


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Fig A10: Analog crosstalk measurement<br>TRACKING GENERATOR SPECTRUM ANALYSER<br>TEST BOARD<br>302 rs our \ ee \ REIN<br>Vg — 500.<br>**----- End of picture text -----**<br>


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Fig A11: Typical analog crosstalk result<br>**----- End of picture text -----**<br>


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A11: Typical analog crosstalk result Figure A10 gives the measurement circuit for the analog<br>application. In figure A11, the curve shows the effect of cell<br>dB /O1 on cell 1/02. In usual frequency range of analog<br>0 signals (up to 100MHz) the effect on disturbed line is less<br>| than -43 dB.<br>cotET<br>a<br>ao LLUEETATT<br>PL<br>eo PTTELUTEATT ETT<br>At<br>ee ae<br>PP TETT<br>yoo LLU<br>1 10 100 1,000<br>F(MHz)<br>**----- End of picture text -----**<br>


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## EMIFO1-10005W5 

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4 - PSpice model<br>**----- End of picture text -----**<br>


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Fig A12: PSpice model of one EMIFO01 cell<br>**----- End of picture text -----**<br>


Fig A13: PSpice parameters 

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ft<br>IN o — o OUT 1000 1000<br>Dee OF pf<br>D ‘ | [KF] | 1000 1000 1000<br>|fis| = 10E-15 | 1.016E-15 | 106-15<br>0.45nH Pp|M___|__0.3333oNIsR_ h])CUt| 1400pSCT| 10090.3333torss |[os0.3333100p<br>|Poors] ow | ClostTCT ttos |tmrs<br>GND<br>Note This model is available for an ambient temperature<br>of 27°C<br>Fig. A14: PSpice simulation : IEC 1000-4-2 Contact Discharge response<br>a) Positive surge b) Negative surge<br>(V) (V)<br>In<br>LLL 2) ose<br>50 al Pe<br>eetSee pe) PIRees<br>LLL LT 2<br>ee PLT TTT<br>wLttttttttte awtLL EET T EETT<br>0 ETTT TTT eo<br>20 40 60 80 100 0) 20 40 60 80 100<br>t(ns) t(ns)<br>Fig A15: Comparison between PSpice<br>simulation and measured frequency response<br>dB<br>0 a<br>pice<br>pastptabiaanac TT Till PSpic<br>so} TM TTT | Spie<br>.CoA<br>woe 1LLM10 TTI100 LU1,000<br>F(MHz)<br>8/10 ky<br>**----- End of picture text -----**<br>


Note This model is available for an ambient temperature 

Fig. A14: PSpice simulation : IEC 1000-4-2 Contact Discharge response 

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EMIFO1-10005W5 

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ORDER CODE<br>EMIF 1 - 100 W5<br>EMI |LTER SOT323-5L package<br>TYPE Input capacitance value /10<br>Series resistance value<br>EMIFO1-10005W5 SOT323.6L 3000 | Tap& r el e<br>**----- End of picture text -----**<br>


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## EMIF01-10005W5 

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PACKAGE MECHANICAL DATA<br>**----- End of picture text -----**<br>


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S$OT323-5L<br>mM | A | os | 11 | 0.031 | 0.043<br>| | par {| o | ot | o | 0.004<br>H| D | a2 | os | 1+ | 0031 | 0.039<br>Joa a a“ mo Lo | te | 22 | oor | 0.086<br>RECOMMENDED FOOTPRINT<br>0.3mm<br>Mechanical specifications<br>Lead plating<br>Lead plating thickness | 5um min.<br>25 um max.<br>>omm Lead material Sn/ Pb<br>(70% to 90% Sn)<br>Lead coplanarity 100um max.<br>Body material Molded epoxy<br>Flammability UL94V-0<br>0.35mm<br>**----- End of picture text -----**<br>


Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 

The ST logo is a registered trademark of ST Microelectronics 

© 1999 STMicroelectronics - Printed in Italy - All rights reserved. 

## STMicroelectronics GROUP OF COMPANIES 

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http:/Awww.st.com 

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- [Supplier page](https://es.farnell.com/stmicroelectronics/emif01-10005w5/emi-filter-esd-protection-sot/dp/2629722RL)
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