EMI4182MTTAG

## EMI4182 

## Common Mode Filter with ESD Protection 

## **Functional Description** 

The EMI4182 is an integrated common mode filter providing both ESD protection and EMI filtering for high speed digital serial interfaces such as HDMI or  MIPI D-PHY. 

The EMI4182 provides protection for two differential data line pairs in a small RoHS-compliant WDFN10 package. 

## **Features** 

- Highly Integrated Common Mode Filter (CMF) with ESD Protection provides protection and EMI reduction for systems using High Speed Serial Data Lines with cost and space savings over discrete solutions 

- Large Differential Mode Bandwidth with Cutoff Frequency > 2 GHz 

- High Common Mode Stop Band Attenuation: >25 dB at 700 MHz, >30 dB at 800 MHz 

- Provides ESD Protection to IEC61000-4-2 Level 4, ±15 kV Contact Discharge 

- Low Channel Input Capacitance Provides Superior Impedance Matching Performance 

- Low Profile Package with Small Footprint in WDFN10 2 x 2.5 mm Pb−Free Package 

- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 

## **Applications** 

- HDMI/DVI Display in Mobile Phones 

- MIPI D-PHY (CSI-2, DSI, etc) in Mobile Phones and Digital Still Cameras 

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1 10<br>2 er vvy > 9<br>External Internal<br>(Connector) 4 7 (ASIC)<br>5 6<br>3, 8<br>**----- End of picture text -----**<br>


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MARKING<br>DIAGRAMS<br>42M<br>WDFN10<br>CASE 511BM<br>42 = Specific Device Code<br>M = Date Code<br>= Pb−Free Package<br>**----- End of picture text -----**<br>


(Note: Microdot may be in either location) 

**PIN CONNECTIONS** In_1+ 1 10 Out_1+ In_1− 2 9 Out_1− ~~—~~ GND OO 3 8 GND 4 7 Out_2+ In_2+ In_2− 5 6 Out_2− ~~———~~ 

(Top View) 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**†|
|---|---|---|
|EMI4182MTTAG|WDFN10<br>(Pb−Free)|3000/Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

**Figure 1. EMI4182 Electrical Schematic** 

Publication Order Number: **EMI4182/D** 

**1** 

© Semiconductor Components Industries, LLC, 2011 **October, 2011 − Rev. 1** 

**EMI4182** 

## **PIN FUNCTION DESCRIPTION** 

|**Pin Name**|**Pin No.**|**Type**|**Description**|
|---|---|---|---|
|In_1+|1|I/O|CMF Channel 1+ to Connector (External)|
|In_1−|2|I/O|CMF Channel 1− to Connector (External)|
|Out_1+|10|I/O|CMF Channel 1+ to ASIC (Internal)|
|Out_1−|9|I/O|CMF Channel 1− to ASIC (Internal)|
|In_2+|4|I/O|CMF Channel 2+ to Connector (External)|
|In_2−|5|I/O|CMF Channel 2− to Connector (External)|
|Out_2+|7|I/O|CMF Channel 2+ to ASIC (Internal)|
|Out_2−|6|I/O|CMF Channel 2− to ASIC (Internal)|
|VN|3, 8|GND|Ground|



## **ABSOLUTE MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) 

|**ABSOLUTE MAXIMUM RATINGS**(TA= 25°C unless otherwise noted)||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Value**|**Unit**|
|Operating Temperature Range|TOP|−40 to +85|°C|
|Storage Temperature Range|TSTG|−65 to +150|°C|
|Maximum Lead Temperature for Soldering Purposes<br>(1/8” from Case for 10 seconds)|TL|260|°C|
|DC Current per Line|ILINE|100|mA|



Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise noted) 

|**ELECTRIC**|**AL CHARACTERISTICS**(TA= 25°C unle|ss otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|ILEAK|Channel Leakage Current|TA= 25°C, VIN= 5 V, GND = 0 V|||1.0|�A|
|VF|Channel Negative Voltage|TA= 25°C, IF= 10 mA|0.1||1.5|V|
|CIN|Channel Input Capacitance to Ground<br>(Pins 1, 2, 4, 5 to Pins 3, 8)|TA= 25°C, At 1 MHz, GND = 0 V,<br>VIN= 1.65 V||0.8|1.3|pF|
|RCH|Channel Resistance<br>(Pins 1−10, 2−9, 4−7 and 5−6)|||8.0||�|
|f3dB|Differential Mode Cut−off Frequency|50�Source and Load Termination||2.0||GHz|
|Fatten|Common Mode Stop Band Attenuation|@ 800 MHz||30||dB|
|VESD|In−system ESD Withstand Voltage<br>a) Contact discharge per IEC 61000−4−2<br>standard, Level 4**(External Pins)**<br>b) Contact discharge per IEC 61000−4−2<br>standard, Level 1**(Internal Pins)**|(Notes 1 and 2)|±15<br>±2|||kV|
|VCL|TLP Clamping Voltage<br>(See Figure 12)|Forward IPP= 8 A<br>Forward IPP= 16 A<br>Forward IPP= −8 A<br>Forward IPP= −16 A||12<br>18<br>−6<br>−12||V<br>V<br>V<br>V|
|RDYN|Dynamic Resistance<br>Positive Transients<br>Negative Transients|TA= 25°C, IPP= 1 A, tP= 8/20�s<br>Any I/O pin to Ground;<br>Notes 1 and 3||1.36<br>0.6|||
|VRWM|Reverse Working Voltage|(Note 3)|||5.0|V|
|VBR|Breakdown Voltage|IT= 1 mA; (Note 4)|5.6||9.0|V|



1. Standard IEC61000−4−2 with CDischarge = 150 pF, RDischarge = 330, GND grounded. 

2. These measurements performed with no external capacitor. 

3. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal to or greater than the DC or continuous peak operating voltage level. 

4. VBR is measured at pulse test current IT. 

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**EMI4182** 

## **TYPICAL CHARACTERISTICS** 

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0<br>−1<br>−2<br>−3<br>−4<br>−5<br>−6<br>−7<br>−8<br>−9<br>1E5 1E6 1E7 1E8 1E9 6E9<br>Frequency, Hz<br>Figure 2. Differential Mode Attenuation vs.<br>Frequency (Zdiff = 100 ) Q<br>0<br>−5<br>−10<br>|<br>−15<br>y|<br>−20<br>−25<br>−30 !<br>−35<br>−40<br>1E5 1E6 1E7 1E8 1E9 6E9<br>Frequency, Hz<br>dB (SCC21)<br>dB(SDD22)dB(SDD11)<br>**----- End of picture text -----**<br>


**Figure 4. Differential Return Loss vs. Frequency (Zdiff=100 )** Q 

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0<br>−5<br>−10<br>−15<br>−20<br>−25<br>−30<br>−35<br>−40<br>1E5 1E6 1E7 1E8 1E9 6E9<br>Frequency, Hz<br>dB (SCC21)<br>**----- End of picture text -----**<br>


**Figure 3. Common Mode Attenuation vs. Frequency (Zcomm = 50 )** Q 

**Figure 5. Differential Inter−Lane Cross−Coupling** 

**Figure 6. Common Mode Inter−Lane Cross−Coupling** 

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**EMI4182** 

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MIPI DSI (D−PHY) MIPI DSI (D−PHY)<br>Host Client<br>EMI4182<br>Evaluation<br>Board<br>**----- End of picture text -----**<br>


**Figure 7. MIPI D−PHY LP Mode Test Setup** 

**Figure 8. EMI4182 MIPI D−PHY LP Mode Measured Results** 

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**EMI4182** 

**Figure 9. EMI4182 Eye Diagram Test Setup** 

**Figure 10. EMI4182 Measured Eye Diagram @ 3.4Gbps (EVB through on left, EVB with EMI4182 on right)** 

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**EMI4182** 

## **Transmission Line Pulse (TLP) Measurements** 

Transmission Line Pulse (TLP) provides current versus voltage (I-V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 11. TLP I-V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10 s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 12 where an 8 kV IEC61000-4-2 current waveform is compared with TLP current pulses at 8 and 16 A. A TLP curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. Typical TLP I-V curves for the EMI4182 are shown in Figure 13. 

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Attenuator<br>k—— L  ——> | 50  Coax Cable 9<br>SW<br>÷ 7,<br>SS 50  Coax v r [_P]<br>Cable IM VM<br>10 M<br>Q 3<br>VC DUT<br>Oscilloscope<br>**----- End of picture text -----**<br>


**Figure 11. Simplified Schematic of a Typical TLP System** 

**Figure 12. Comparison Between 8 kV IEC61000−4−2 and 8 A and 16 A TLP Waveforms** 

**Figure 13. Positive and Negative TLP Waveforms** 

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**EMI4182** 

## **ESD Voltage Clamping** 

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor Application Notes AND8307/D and AND8308/D. 

|**IEC61000−4−2 Spec.**|**IEC61000−4−2 Spec.**|**IEC61000−4−2 Spec.**|||
|---|---|---|---|---|
|**Level**|**Test**<br>**Voltage**<br>**(kV)**|**First Peak**<br>**Current**<br>**(A)**|**Current at**<br>**30 ns (A)**|**Current at**<br>**60 ns (A)**|
|1|2|7.5|4|2|
|2|4|15|8|4|
|3|6|22.5|12|6|
|4|8|30|16|8|



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IEC61000−4−2 Waveform<br>Ipeak<br>100%<br>90%<br>I @ 30 ns<br>I @ 60 ns<br>10%<br>tP = 0.7 ns to 1 ns<br>**----- End of picture text -----**<br>


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ESD Gun Oscilloscope<br>TVS<br>50  �<br>Cable 50  �<br>**----- End of picture text -----**<br>


**Figure 14. Diagram of ESD Test Setup** 

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100<br>tr PEAK VALUE IRSM @ 8 �s<br>90<br>80 PULSE WIDTH (tP) IS DEFINED<br>AS THAT POINT WHERE THE<br>70 PEAK CURRENT DECAY = 8 �s<br>60<br>HALF VALUE IRSM/2 @ 20 �s<br>50<br>40<br>30<br>tP<br>20<br>10<br>0<br>0 20 40 60 80<br>t, TIME ( � s)<br>% OF PEAK PULSE CURRENT<br>**----- End of picture text -----**<br>


**Figure 15. 8 x 20 � s Pulse Waveform** 

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**EMI4182** 

**Figure 16. ESD Clamping Voltage +8 kV per IEC6100−4−2 (external to internal pin)** 

**Figure 17. ESD Clamping Voltage −8 kV per IEC6100−4−2 (external to internal pin)** 

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HDMI Type−A<br>Connector<br>EMI4182<br>TMDS Data 2+ D2+<br>TMDS Data 2− GND<br>D2−<br>TMDS Data 1+ D1+<br>TMDS Data 1− GND<br>D1−<br>EMI4182<br>TMDS Data 0+ D0+<br>TMDS Data 0− GND<br>D0−<br>TMDS Clock+ CLK+<br>TMDS Clock− GND<br>CEC CLK−<br>CEC<br>SCL<br>HEC DATA<br>SDA<br>SCL<br>Hot Plug Detect SDA<br>NUP4114 +5V Power GND<br>(Bottom View) 5V<br>HTP _D<br>Black = Top layer<br>Red = other layer<br>**----- End of picture text -----**<br>


**Figure 18. EMI4182 HDMI Type – A Connector Application Diagram** 

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HDMI Type −D<br>EMI4182 Connector<br>TMDS Data 2+<br>TMDS Data 2− PINHTP_D1<br>Util<br>D2+<br>GND<br>TMDS Data 1+ D2− D1+<br>GND<br>TMDS Data 1− D1−<br>D0+<br>GND<br>TMDS Data 0+ D0−<br>CLK +<br>TMDS Data 0− GND CLK −<br>CEC<br>GND<br>SCL<br>TMDS Clock + 5V SDA<br>TMDS Clock − Black = Top layer<br>Red = other layer<br>EMI4182<br>CEC<br>SCL<br>+5V Power<br>SDA<br>NUP4114<br>(Bottom View)<br>**----- End of picture text -----**<br>


**Figure 19. EMI4182 HDMI Type − D Connector Application Diagram** 

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## **PACKAGE DIMENSIONS** 

**WDFN10 2.5x2, 0.5P** CASE 511BM−01 ISSUE O 

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D A B L L NOTES:<br>1. DIMENSIONING AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>2X 0.10 C L1 2.3. CONTROLLING DIMENSION: MILLIMETERS.DIMENSIONS b APPLIES TO PLATED<br>oof} TERMINAL AND IS MEASURED BETWEEN<br>PIN 1 ÇÇÇ + E f o f DETAIL A u t 4. COPLANARITY APPLIES TO THE EXPOSED0.15 AND 0.30 MM FROM TERMINAL TIP.<br>REFERENCE ALTERNATE TERMINAL PAD AS WELL AS THE TERMINALS.<br>CONSTRUCTIONS<br>ÇÇÇ MILLIMETERS<br>A3 DIM MIN MAX<br>2X 0.10 C EXPOSED Cu MOLD CMPD A 0.70 0.80<br>“ E TOP VIEW T A1 0.00 0.05<br>ÉÉ ÉÉÇÇ A3 0.20 REF<br>0.05 C DETAIL B (A3) ÇÇ ÇÇ Db 0.152.50 BSC0.25<br>A1<br>E 2.00 BSC<br>A DETAIL B e 0.50 BSC<br>0.05 C ALTERNATE L 0.70 0.90<br>CONSTRUCTIONS L1 0.05 0.15<br>NOTE 4<br>SIDE VIEW A1 C SEATINGPLANE<br>DETAIL A RECOMMENDED<br>MOUNTING FOOTPRINT<br>1 Ne 5<br>8X L 1.078X 0.308X PACKAGEOUTLINE<br>O TTO,<br>0.10<br>MIN<br>10 6 2.30<br>e 9X b 1<br>0.10 M C A B<br>ait my<br>BOTTOM VIEW eee 0.05 M C NOTE 3 0.45 HI 0.50 PITCH<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

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**EMI4182/D** 

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