# Power MOSFET, N Channel, 650 V, 300 mA, 8 ohm, TO-252AA, Surface Mount

![Product image](https://novapart.co/image/farnell:2450519RL/)

**URL**: https://novapart.co/products/DN3765K4-G/power-mosfet-n-channel-650-v-300-ma-8-ohm-to-252aa
**SKU**: DN3765K4-G
**Manufacturer**: MICROCHIP
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €1.7700
**Stock**: 10+
**Lead Time**: 36 days (indicative)

## Description

Transistor Polarity:N Channel; Continuous Drain Current Id:300mA; Drain Source Voltage Vds:650V; On Resistance Rds(on):8ohm; Rds(on) Test Voltage Vgs:0V; Threshold Voltage Vgs:-; Pow

## Specifications

| Parameter | Value |
|---|---|
| Msl | MSL 1 - Unlimited |
| Svhc | No SVHC (04-Feb-2026) |
| No. Of Pins | 3Pins |
| Channel Type | N Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 2.5W |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 0V |
| Transistor Case Style | TO-252AA |
| Drain Source Voltage Vds | 650V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 300mA |
| Drain Source On State Resistance | 8ohm |
| Gate Source Threshold Voltage Max | - |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:2450519RL/)

_**Su ertex inc. p**_ 

**DN3765** 

## **N-Channel Depletion-Mode Vertical DMOS FET** 

## **Features** 

- High input  impedance 

- Low input capacitance 

- Fast switching speeds 

- Low on-resistance 

- Free from secondary breakdown 

- Low input and output leakage 

## **Applications** 

- Normally-on switches 

- Solid state relays 

- Converters 

- Linear amplifiers 

- Constant current sources 

## **General Description** 

This depletion-mode (normally-on) transistor utilizes an advanced vertical DMOS structure and Supertex’s wellproven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. 

Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. 

- Telecom 

**Ordering Information Product Summary Part Number Package Option Packing BVDSX/BVDGX RDS(ON) (max) IDSS (min)** ~~ee~~ DN3765K4-G TO-252 (D-PAK) 2000/Reel 650V 8.0Ω 200mA _-G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant._ 

## **Pin Configuration** 

## **Absolute Maximum Ratings** 

**==> picture [104 x 78] intentionally omitted <==**

**----- Start of picture text -----**<br>
DRAIN<br>SOURCE<br>GATE<br>**----- End of picture text -----**<br>


|**Parameter**|**Value**|
|---|---|
|Drain-to-source voltage|BVDSX|
|Drain-to-gate voltage|BVDGX|
|Gate-to-source voltage|±20V|
|Operatingand storage temperature|-55OC to +150OC|
|Maximumjunction temperature|150OC|



**==> picture [76 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
TO-252 (D-PAK)<br>**----- End of picture text -----**<br>


_Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground._ 

## **Product Marking** 

|**Si YYWW**|YY = Year Sealed<br>WW = Week Sealed|
|---|---|
|**DN3765**<br>**LLLLLLL**|L = Lot Number<br>~~=~~“Green” Packaging|



## **Typical Thermal Resistance** 

|**Package**<br>TO-252(D-PAK)|**_θja_**<br>81OC/W|
|---|---|



_Package may or may not include the following marks: Si or_ 

**TO-252 (D-PAK)** 

_**Supertex inc.**_ 

_Doc.# DSFP-DN3765 A070113_ 

_**www.supertex.com**_ 

**DN3765** 

## **Thermal Characteristics** 

**==> picture [542 x 45] intentionally omitted <==**

**----- Start of picture text -----**<br>
Package (continuous)ID [†] (pulsed)ID Power Dissipation@TA = 25 [O] C [ ‡] IDR † IDRM<br>TO-252 (D-PAK) 300mA 500mA 2.5W 300mA 500mA<br>**----- End of picture text -----**<br>


## _**Notes:**_ 

- _ID (continuous) is limited by max rated Tj of 150[O] C._ 

- _Mounted on FR4 board, 25mm x 25mm x 1.57mm._ 

## **Electrical Characteristics** _(TA = 25[O] C unless otherwise specified)_ 

**==> picture [542 x 331] intentionally omitted <==**

**----- Start of picture text -----**<br>
Sym Parameter Min Typ Max Units Conditions<br>BVDSX Drain-to-source breakdown voltage 650 - - V VGS = -5.0V, ID = 100µA<br>VGS(OFF) Gate-to-source off voltage -1.5 - -3.5 V VDS = 25V, ID= 10µA<br>ΔVGS(OFF) Change in VGS(OFF) with temperature - - -4.5 mV/ [O] C VDS = 25V, ID= 10µA<br>IGSS Gate body leakage current - - 100 nA VGS = ± 20V, VDS = 0V<br>- - 10 µA VGS = -10V, VDS = Max Rating<br>ID(OFF) Drain-to-source leakage current - - 1.0 mA VGS = -10V, VDS = 0.8 Max Rating,<br>T  = 125°C<br>A<br>IDSS Saturated drain-to-source current 200 - - mA VGS = 0V, VDS = 25V<br>RDS(ON) Static drain-to-source on-state resistance - - 8.0 Ω VGS = 0V, ID = 150mA<br>ΔRDS(ON) Change in RDS(ON) with temperature - - 1.1 %/ [O] C VGS = 0V, ID = 150mA<br>GFS Forward transductance 100 - - mmho  ID = 100mA, VDS = 10V<br>CISS Input capacitance - - 825 VGS = -10V,<br>COSS Common source output capacitance - - 190 pF VDS = 25V,<br>CRSS Reverse transfer capacitance - - 110 f = 1.0MHz<br>td(ON) Turn-on delay time  - - 50<br>t Rise time - - 75 VDD = 25V,<br>r ns ID = 150mA,<br>td(OFF) Turn-off delay time - - 75 R  = 25Ω<br>GEN<br>t Fall time - - 100<br>f<br>VSD Diode forward voltage drop - - 1.8 V VGS = -5.0V, ISD = 200mA<br>trr Reverse recovery time - 800 - ns VGS = -5.0V, ISD = 200mA<br>**----- End of picture text -----**<br>


_**Notes:**_ 

_1. All D.C. parameters 100% tested at 25[O] C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)_ 

_2. All A.C. parameters sample tested._ 

## **Switching Waveforms and Test Circuit** 

**==> picture [534 x 141] intentionally omitted <==**

**----- Start of picture text -----**<br>
0V 90% VDD<br>INPUT Pulse R<br>10% Generator L<br>-10V OUTPUT<br>t t<br>(ON) (OFF) R<br>GEN<br>td(ON) tr td(OFF) tf<br>VDD INPUT D.U.T.<br>10% 10%<br>OUTPUT<br>0V 90% 90%<br>**----- End of picture text -----**<br>


_**Supertex inc.**_ 

_Doc.# DSFP-DN3765 A070113_ 

_**www.supertex.com**_ 

2 

**DN3765** 

## **3-Lead TO-252 (D-PAK) Package Outline (K4)** 

**==> picture [471 x 394] intentionally omitted <==**

**----- Start of picture text -----**<br>
b3  A<br>E E1 c2<br>4 L3<br>θ1<br>D1  H<br>D<br>1 2 3 L4<br>L5<br>Note 1<br>View B<br>b2<br>b<br>e<br>Front View Rear View  Side View<br>Gauge<br>Plane A1 Seating<br>Plane<br>L2<br>θ<br>L<br>L1<br>View B<br>**----- End of picture text -----**<br>


## _**Note:**_ 

_1. Although 4 terminal locations are shown, only 3 are functional. Lead number 2 was removed._ 

**==> picture [543 x 64] intentionally omitted <==**

**----- Start of picture text -----**<br>
Symbol A A1 b b2 b3 c2 D D1 E E1 e H L L1 L2 L3 L4 L5 θ θ 1<br>MIN .086 .000* .025 .030 .195 .018 .235 .205 .250 .170 .370 .055 .035 .025* .035 [†] 0 [O] 0 [O]<br>Dimen-<br>sion NOM - - - - - - .240 - - - .090 - .060 .108 .020 - - - - -<br>BSC REF BSC<br>(inches)<br>MAX .094 .005 .035 .045 .215 .035 .245 .217* .265 .200* .410 .070 .050 .040 .060 10 [O] 15 [O]<br>**----- End of picture text -----**<br>


- _JEDEC Registration TO-252, Variation AA, Issue E, June 2004. * This dimension is not specified in the JEDEC drawing._ 

- _This dimension differs from the JEDEC drawing._ 

_**Drawings not to scale.**_ 

_**Supertex Doc. #:** DSPD-3TO252K4, Version F040910._ 

_(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)_ 

_**Supertex inc.**_ does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” _**Supertex inc.**_ does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the _**Supertex inc.**_ (website: http//www.supertex.com) 

©2013 _**Supertex inc.**_ All rights reserved. Unauthorized use or reproduction is prohibited. 

_**Supertex inc.**_ 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 _**www.supertex.com**_ 

_Doc.# DSFP-DN3765 A070113_ 

3 



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