# Power MOSFET, P Channel, 12 V, 2 A, 0.07 ohm, X2-DFN1010, Surface Mount

![Product image](https://novapart.co/image/farnell:3943697/)

**URL**: https://novapart.co/products/DMP1200UFR4-7/power-mosfet-p-channel-12-v-2-a-007-ohm-x2-dfn1010
**SKU**: DMP1200UFR4-7
**Manufacturer**: DIODES INC.
**Category**: Semiconductors - Discretes || FETs || Single MOSFETs
**Price**: €0.1330
**Stock**: 10+
**Lead Time**: 78 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | No SVHC (25-Jun-2025) |
| No. Of Pins | 3Pins |
| Channel Type | P Channel |
| Product Range | - |
| Qualification | - |
| Power Dissipation | 480mW |
| Transistor Mounting | Surface Mount |
| Rds(On) Test Voltage | 4.5V |
| Transistor Case Style | X2-DFN1010 |
| Drain Source Voltage Vds | 12V |
| Operating Temperature Max | 150°C |
| Continuous Drain Current Id | 2A |
| Drain Source On State Resistance | 0.07ohm |
| Gate Source Threshold Voltage Max | 1V |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:3943697/)

**DMP1200UFR4 P-CHANNEL ENHANCEMENT MODE MOSFET Product Summary Features and Benefits V(BR)DSS RDS(ON) TA = +25°C ID**  Low On-Resistance ESD Protected Gate 100mΩ @ VGS = -4.5 V -2A  Low Input/Output Leakage  Fast Switching Speed 160mΩ @ VGS = -2.5V -1A  **Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)** -12V  **Halogen and Antimony Free. “Green” Device (Note 3)** 200mΩ @ VGS = -1.8V -0.5A 380mΩ @ VGS = -1.5V -0.2A **Description and Applications Mechanical Data** This new generation MOSFET is designed to minimize the on-state  Case: X2-DFN1010-3 resistance (RDS(on)) and yet maintain superior switching  Case Material: Molded Plastic, “Green” Molding Compound. performance, making it ideal for high efficiency power management UL Flammability Classification Rating 94V-0 applications.  Moisture Sensitivity:  Level 1 per J-STD-020 |  Power Management Functions  Terminal Connections: See Diagram  Backlighting  Terminals: Finish - NiPdAu Annealed over Copper Leadframe.  Load Switch Solderable per MIL-STD-202, Method 208  Weight: 0.0015 grams (Approximate) X2-DFN1010-3 : ESD PROTECTED Bottom View Gate Proton Pin-out Top view Equivalent Circuit **Ordering Information** (Note 4) **Part Number Case Packaging** DMP1200UFR4-7 X2-DFN1010-3 3000/Tape & Reel Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds. 4. For packaging details, go to our website at http”//www.diodes.com/products/packages.html. **Marking Information** 12 = Product Type Marking Code **12** YM = Date Code Marking Y = Year (ex: Y = 2011) **YM** M = Month (ex: 9 = September) Date Code Key **Year 2011 2012 2013 2014 2015 2016 2017 Code** Y Z A B C D E **Month Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec** ~~—~~ **Code** 1 2 3 4 5 6 7 8 9 O N D DMP1200UFR4 1 of 6 October 2014 Document number: DS36557 Rev. 2 - 2 **www.diodes.com** © Diodes Incorporated 

||||**DMP1200UFR4**|
|---|---|---|---|
|NEW PRODUCT<br>**Maximum Ratings** (@TA= +25°C unless otherwise specified.)<br>**Characteristic**<br>**Symbol**<br>**Value**<br>**Units**<br>Drain-Source Voltage<br>VDSS<br>-12<br>V<br>Gate-Source Voltage<br>VGSS<br>±8<br>V<br>Drain Current(Note 6)<br>Steady<br>TA= +25C<br>ID<br>2<br>A<br>**Thermal Characteristics**<br>**Characteristic**<br>**Symbol**<br>**Value**<br>**Units**<br>Total Power Dissipation(Note 5)<br>PD<br>0.48<br>W<br>Thermal Resistance,Junction to Ambient@TA= +25°C(Note 5)<br>RJA<br>266<br>°C/W<br>Total Power Dissipation(Note 6)<br>PD<br>1.26<br>W<br>Thermal Resistance,Junction to Ambient@TA= +25°C(Note 6)<br>RJA<br>102<br>°C/W<br>Operatingand Storage Temperature Range<br>TJ,TSTG<br>-55 to +150<br>°C<br>**Electrical Characteristics** (@TA= +25°C unless otherwise specified.)<br>**Characteristic**<br>**Symbol**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Test Condition**<br>**OFF CHARACTERISTICS(Note 7)**<br>Drain-Source Breakdown Voltage<br>BVDSS<br>-12<br><br><br>V<br>VGS= 0V,ID= -250µA<br>Zero Gate Voltage Drain Current<br>IDSS<br><br><br>-1<br>µA<br>VDS= -9.6V,VGS= 0V<br>Gate-Source Leakage<br>IGSS<br><br><br>10<br>µA<br>VGS=6V,VDS= 0V<br>|~~——SSeeeSS~~||||
||**ON CHARACTERISTICS(Note 7)**|||
||Gate Threshold Voltage<br>VGS(th)<br>-0.35<br><br>-1.0<br>V<br>VDS= VGS,ID= -250µA<br>Static Drain-Source On-Resistance<br>RDS (ON)<br><br>70<br>90<br>115<br>145<br>100<br>160<br>200<br>380<br>mΩ<br>VGS= -4.5V, ID= -2A<br>VGS= -2.5V, ID= -1A<br>VGS= -1.8V, ID= -0.5A<br>VGS= -1.5V,ID= -0.2A<br>Forward Transfer Admittance<br>|Yfs|<br>40<br><br><br>mS<br>VDS= -5V,ID= -0.5A<br>Diode Forward Voltage<br>VSD<br><br><br>-1.2<br>V<br>VGS= 0V,IS= -0.2A<br>**DYNAMIC CHARACTERISTICS(Note 8)**<br>~~ft}~~<br>~~|~~|||
||Input Capacitance<br>Ciss<br><br>514<br>Output Capacitance<br>Coss<br><br>131<br>Reverse Transfer Capacitance<br>Crss<br><br>60|<br><br>|pF<br>VDS= -5V, VGS= 0V, f =<br>1.0MHz<br>pF<br>pF|
||Total Gate Charge<br>Qg<br><br>5.8<br>Gate-Source Charge<br>Qgs<br><br>0.8<br>Gate-Drain Charge<br>Qgd<br><br>1.2<br>Turn-On DelayTime<br>tD(on)<br><br>15<br>Turn-On Rise Time<br>tr<br><br>62<br>Turn-Off DelayTime<br>tD(off)<br><br>332<br>Turn-Off Fall Time<br>tf<br><br>166<br>Notes:<br>5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout.<br>~~a~~<br>~~OO~~<br>~~—_—————~~|<br><br><br><br><br><br><br>5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout.|nC<br>VGS= -4.5V, VDS= -5V,<br>ID= -2A<br>nC<br>nC<br>nS<br>VDD= -5V, VGEN= -4.5V,<br>RGEN= 6Ω<br>nS<br>nS<br>nS<br>~~eee~~|



Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout. 

6. Device mounted on 1” x 1” FR-4 PCB with high coverage 2oz. Copper, single sided. 

7. Short duration pulse test used to minimize self-heating effect. 

8. Guaranteed by design. Not subject to production testing. 

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**----- Start of picture text -----**<br>
15.0 10<br>VGS = -3.0V<br>VGS = -4.0V 9 V DS  = -5.0V<br>12.0 8<br>VGS = -4.5V<br>7<br>VGS  = -8.0V<br>9.0 6<br>Jf VGS  = -1.8V 5<br>6.0 4<br>foes 3 Frye<br>VGS = -1.5V<br>3.0 2<br>0.0 VVGSGS = -1.0V = -1.2V 10 TA = 150°C TA = 125°C TA T = -55°CAT = 25°CA = 85°C<br>0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5<br>VDS [,]  DRAIN -SOURCE VOLTAGE (V) V GS [,]  GATE-SOURCE VOLTAGE (V)<br>Figure 1 Typical Output Characteristics Figure 2 Typical Transfer Characteristics<br>0.3 0.5<br>0.25 VGS  = -1.5V 0.4<br>0.2 To Aa ID = -2.0A<br>pee VGS = -1.8V 0.3 Te<br>0.15<br>VGS = -2.5V 0.2 ID = -1.0A<br>0.1 Ay V GS  = -4.5V<br>an ST<br>0.05 0.1 ID = -500mA<br>rt KA<br>0<br>0 Tr 3 6 9 12 15 0 hanna<br>I D, DRAIN SOURCE CURRENT (A) 0 1 2 3 4 5 6 7 8<br>Figure 3 Typical On-Resistance vs.  V GS, GATE-SOURCE VOLTAGE (V)<br>Drain Current and Gate Voltage  Figure 4 Typical Transfer Characteristic<br>0.14 2<br>VGS = -4.5V<br>1.8<br>0.12 TA = 150°C<br>TA = 125°C 1.6 V GS  = -2.5V<br>0.1 ID = -2.0A<br>Coe eee 1.4 EEE<br>T A = 85°C<br>0.08 Srrrrer T A = 25°C tt 1.2 -CEL es<br>0.06 T A = -55°C $$ 1 Teer V GS  = -1.8V<br>0.8 ID = -1.0A<br>0.04 PTT FTL ll 0.6 PEELE<br>0.4<br>0.02 TELL ELL EL PT<br>0.2<br>0<br>0 TELL 1 2 3 4 5 ELLLL 6 7 8 9 10 0 ee<br>IFigure 5 Typical On-Resistance vs. D [,]  DRAIN SOURCE CURRENT (A) -50 -25TJ [,]  JUNCTION TEMPERATURE ( C)0 25 50 75 100 125 150<br>Drain Current and Temperature  Figure 6 On-Resistance Variation with Temperature<br>⁭<br>⁭<br> DRAIN-SOURCE<br>,<br>DS(ON)<br>R<br>ON-RESISTANCE (NORMALIZED)<br>, DRAIN CURRENT (A)<br>ID<br>)Ω<br> DRAIN-SOURCE ON-RESISTANCE (<br>,<br>DS(ON)<br>R<br>, DRAIN CURRENT (A)<br>ID<br>,<br>DS(ON)<br>)Ω<br> DRAIN-SOURCE ON-RESISTANCE (<br>R<br>)Ω<br> DRAIN-SOURCE ON-RESISTANCE (,<br>DS(ON)<br>R<br>**----- End of picture text -----**<br>


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0.2 1<br>VGS  = -1.8V<br>ID = -1.0A 0.8<br>0.15 ID = -1mA<br>EE eo<br>0.6<br>0.1 ppee seen > —SS<br>Pate VGS = -2.5V 0.4 SR<br>ID = -2.0A ID = -250µA<br>0.05<br>TT) oa<br>0.2<br>0 0<br>-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150<br>TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (C)<br>Figure 7 On-Resistance Variation with Temperature Figure 8 Gate Threshold Variation vs. Ambient Temperature<br>10 1000<br>f = 1MHz<br>9 Ciss<br>8 een a =====—<br>7 TA = 150°C<br>6 ae |i SSEA<br>5 100 Coss<br>ey | \<br>4 TA= 125°C<br>C rss<br>3 OPK ES<br>TA= 85°C<br>2<br>TA= 25°C<br>1 ame)— aeo ES<br>TA= -55°C<br>0 Yy 10 EL,<br>0 0.3 0.6 0.9 1.2 1.5 0 2 4 6 8 10 12<br>VSD, SOURCE-DRAIN VOLTAGE (V) VDS, DRAIN-SOURCE VOLTAGE (V)<br>Figure 9 Diode Forward Voltage vs. Current Figure 10 Typical Junction Capacitance<br>8 100<br>R DS(on)<br>Limited<br>6 10<br>VDS = -5V<br>ID = -2.0A<br>DC<br>4 1<br>PW = 10s<br>P W  = 1s<br>P W = 100ms<br>2 ) 0.1 T J(m ax )  = 150°C PW = 10ms<br>TA = 25°C PW = 1ms<br>V Single PulseGS  = 4.5V P W  = 100µs<br>0 ATI yd 0.01 DUT on 1 * MRP Board UNLeeeeeNsll<br>0 1 2 3 4 5 6 7 8 9 10 0.1 1 10 100<br>Q g [,]  TOTAL GATE CHARGE (nC) V DS, DRAIN-SOURCE VOLTAGE (V)<br>Figure 11 Gate-Charge Characteristics Figure 12 SOA, Safe Operation Area<br>,<br>gs(th)<br> Gate Threshold Voltage (V)<br>V<br>)Ω<br>, DRAIN-SOURCE<br>DS(ON)ON-RESISTANCE (<br>R<br>D<br>, DRAIN CURRENT (A)<br>I<br>, JUNCTION CAPACITANCE (pF)<br>T<br>C<br>, SOURCE CURRENT (A)<br>IS<br>GS<br>, GATE-SOURCE VOLTAGE (V)<br>V<br>**----- End of picture text -----**<br>


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1<br>D = 0.9<br>SS D = 0.7 Se<br>Ey D = 0.5 PHT<br>RUAN D = 0.3 CTE GMM TAIT  AAAI PEOGL S20 GM MOTIIIMMMOVIIION TTT TTAGLI MOOIETH<br>0.1 AT NM CLIN TAIT UII UU<br>ee D = 0.1<br>a a OO Oc”, Oe OO 0 |<br>eTCO<br>D = 0.05<br>ETHIE TTT<br>A<br>M77<br>D = 0.02<br>RAAT LTTE TTT<br>TINTaEAU EEE EET TM LUI<br>0.01 ee D = 0.01 ad A ee ee<br>ery Se ane<br>D = 0.005 Rthja(t)=r(t) * Rthja<br>Fy TCC TH TTT<br>Miia Rthja=262C/W au<br>Single Pulse Duty Cycle, D=t1 /  t2<br>0.001<br>0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, PULSE DURATION TIMES (sec)<br>Figure 13  Transient Thermal Resistance<br>r(t), TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


## **Package Outline Dimensions** 

Please see AP02002 at http://www.diodes.com/datasheets/ap02002.pdf for the latest version. 

**==> picture [346 x 375] intentionally omitted <==**

**----- Start of picture text -----**<br>
A3<br>A A1<br>X2-DFN1010-3<br>Seating Plane Dim  Min  Max  Typ<br>jlo oi ————— e A  e -  eoe 0.40 0.39<br>— | D ! : aa A1  A3   0.- 00 0.- 05 00..102 3<br>ee b  0.18 0.28 0.23<br>(Pin #1 ID) a D  0.95 1.05 1.00<br>E2 ee D2  0.70 0.90 0.80<br>E  0.95 1.05 1.00<br>E<br>a E2  0.36 0.56 0.46<br>D2 K ee e  -  -  0.50<br>a K  -  -  0.20<br>L L  0.195 0.295 0.245<br>All Dimensions in mm<br>b<br>J e bP _—<br>yout out<br>ae X<br>Y2 X2-DFN1010-3<br>Dimensions Value<br>C 0.500<br>X1 Y1 G  0.150<br>X  0.330<br>X1  0.900<br>G X Y  0.445<br>eo _<br>Y1  0.505<br>Y2  0.200<br>Y All Dimensions in mm<br>| !<br>Lu C<br>**----- End of picture text -----**<br>


## **Suggested Pad Layout out** 

Please see AP02001 at http://www.diodes.com/datasheets/ap02001.pdf for the latest version. 

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DMP1200UFR4 Document number: DS36557 Rev. 2 - 2 

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**DMP1200UFR4** a 

## **IMPORTANT NOTICE** 

DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 

Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others.  Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated website, harmless against all damages. 

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This document is written in English but may be translated into multiple languages for reference.  Only the English version of this document is the final and determinative format released by Diodes Incorporated. 

## **LIFE SUPPORT** 

Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein: 

- A.   Life support devices or systems are devices or systems which: 

   1. are intended to implant into the body, or 

   2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user. 

B.   A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or to affect its safety or effectiveness. 

Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated.  Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. 

Copyright © 2014, Diodes Incorporated 

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DMP1200UFR4 Document number: DS36557 Rev. 2 - 2 

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