Image not available
Illustrative purposes only
CYBLE-014008-00
PSoC® Module, Bluetooth® v4.1 Low Energy Module, 2.4GHz, Single Mode
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: INFINEON
- Product type: Bluetooth Modules & Adaptors
- Bluetooth Version:Bluetooth 4.1; Supply Voltage Min:1.71V; Supply Voltage Max:5.5V; Signal Range Max:-; Data Rate:1Mbps; Bluetooth Class:-; Re; Available until stocks are exhausted
- SVHC: No SVHC (23-Jan-2024)
- Interfaces: I2C, SPI, UART
- Product Range: -
- Certifications: CE, FCC, IC, KC, MIC
- Bluetooth Class: -
- Bluetooth Version: Bluetooth 4.1
- Supply Voltage Range: 1.71 V to 5.5 V
- Receiver Sensitivity Rx: -87 dBm
- Operating Temperature Range: -40 °C to 85 °C
| Delivery and price | |
|---|---|
| Units per pack | 10 |
| Price | 11.28 € |
| Current stock | 25+ |
| Lead time | 30 days |
Datasheet
**CYBLE-014008-00** EZ-BLE™ PSoC[®] Module
**==> picture [171 x 68] intentionally omitted <==**
## **General Description**
The Cypress CYBLE-014008-00 is a fully certified and qualified module supporting Bluetooth[] Low Energy (BLE) wireless communication. The CYBLE-014008-00 is a turnkey solution and includes onboard crystal oscillators, trace antenna, passive components, and the Cypress PSoC[®] 4 BLE. Refer to the PSoC[®] 4 BLE datasheet for additional details on the capabilities of the PSoC 4 BLE device used on this module.
The EZ-BLE PSoC[®] module is a scalable and reconfigurable platform architecture. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The CYBLE-014008-00 also includes digital programmable logic, high-performance analog-to-digital conversion (ADC), opamps with comparator mode, and standard communication and timing peripherals.
The CYBLE-014008-00 includes a royalty-free BLE stack compatible with Bluetooth 4.1 and provides up to 25 GPIOs in a small 11 × 11 × 1.80 mm package.
The CYBLE-014008-00 is a complete solution and an ideal fit for applications seeking a highly integrated BLE wireless solution.
## **Module Description**
- Module size: 11.0 mm × 11.0 mm × 1.80 mm (with shield)
- 128-KB flash memory, 16-KB SRAM memory
- Up to 25 GPIOs configurable as open drain high/low, pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output
- Bluetooth 4.1 qualified single-mode module
- ❐ QDID: 79697
- ❐ Declaration ID: D029647
- Certified to FCC, CE, MIC, KC, and IC regulations
- Industrial temperature range: –40 °C to +85 °C
- 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit multiply, operating at up to 48 MHz
- Watchdog timer with dedicated internal low-speed oscillator (ILO)
- Two-pin SWD for programming
## **Power Consumption**
- TX output power: –18 dbm to +3 dbm
- Received signal strength indicator (RSSI) with 1-dB resolution
## ■ Low power mode support
- ❐ Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on ❐ Hibernate: 150 nA with SRAM retention
- ❐ Stop: 60 nA with GPIO (P2.2) or XRES wakeup
## **Programmable Analog**
- Four opamps with reconfigurable high-drive external and high-bandwidth internal drive, comparator modes, and ADC input buffering capability; can operate in Deep-Sleep mode
- 12-bit, 1-Msps SAR ADC with differential and single-ended modes; channel sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- One low-power comparator that operate in Deep-Sleep mode
## **Programmable Digital**
- Four programmable logic blocks called universal digital blocks, (UDBs), each with eight macrocells and datapath
- Cypress-provided peripheral Component library, user-defined state machines, and Verilog input
## **Capacitive Sensing**
- Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (> 5:1) and liquid tolerance
- Cypress-supplied software component makes capacitive-sensing design easy
- Automatic hardware-tuning algorithm (SmartSense™)
## **Segment LCD Drive**
- LCD drive supported on all GPIOs (common or segment)
- Operates in Deep-Sleep mode with four bits per pin memory
## **Serial Communication**
- Two independent runtime reconfigurable serial communication blocks (SCBs) with I[2] C, SPI, or UART functionality
## **Timing and Pulse-Width Modulation**
- Four 16-bit timer, counter, pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
## **Up to 25 Programmable GPIOs**
- Any GPIO pin can be CapSense, LCD, analog, or digital
- TX current consumption of 15.6 mA (radio only, 0 dbm)
- RX current consumption of 16.4 mA (radio only)
**Cypress Semiconductor Corporation** Document Number: 002-00023 Rev. *G
• 198 Champion Court
San Jose, CA 95134-1709 • 408-943-2600 Revised September 2, 2016
•
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **More Information**
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.
- Overview: EZ-BLE Module Portfolio, Module Roadmap
- EZ-BLE PSoC Product Overview
- PSoC 4 BLE Silicon Datasheet
- Application notes: Cypress offers a number of BLE application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with EZ-BLE modules are:
- ❐ AN96841 - Getting Started with EZ-BLE Module
- ❐ AN94020 - Getting Started with PSoC[®] 4 BLE
- ❐ AN97060 - PSoC[®] 4 BLE and PRoC™ BLE - Over-The-Air (OTA) Device Firmware Upgrade (DFU) Guide
- ❐ AN91162 - Creating a BLE Custom Profile
- ❐ AN91184 - PSoC 4 BLE - Designing BLE Applications
- ❐ AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications
- ❐ AN85951 - PSoC[®] 4 CapSense[®] Design Guide
- ❐ AN95089 - PSoC[®] 4/PRoC™ BLE Crystal Oscillator Selection and Tuning Techniques
- ❐ AN91445 - Antenna Design and RF Layout Guidelines
## ■ Knowledge Base Articles
- ❐ KBA210574 - RF Regulatory Certifications for CYBLE-014008-00 and CYBLE-214009-00 EZ-BLE™ PSoC[®] Modules - KBA210574
- ❐ KBA97095 - EZ-BLE™ Module Placement
- ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules
- ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes
- Technical Reference Manual (TRM):
- ❐ PSoC[®] 4 BLE Technical Reference Manual
- ❐ PSOC[®] 4 BLE Registers Technical Reference Manual (TRM)
- Development Kits:
- ❐ CYBLE-014008-EVAL, CYBLE-014008-00 Evaluation Board
- ❐ CY8CKIT-042-BLE, Bluetooth[®] Low Energy (BLE) Pioneer Kit
- ❐ CY8CKIT-002, PSoC[®] MiniProg3 Program and Debug Kit
- Test and Debug Tools:
- ❐ CYSmart, Bluetooth[®] LE Test and Debug Tool (Windows)
- ❐ CYSmart Mobile, Bluetooth[®] LE Test and Debug Tool (Android/iOS Mobile App)
- ❐ KBA97279 - Pin Mapping Differences Between the EZ-BLE™ PRoC™ Evaluation Board
- (CYBLE-014008-EVAL) and the BLE Pioneer Kit (CY8CKIT-042-BLE)
## **PSoC[®] Creator™ Integrated Design Environment (IDE)**
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified, production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements.
## **Bluetooth Low Energy Component**
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS) hardware via the stack.
## **Technical Support**
- Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.
- Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.
- Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-00023 Rev. *G
Page 2 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Contents**
**Overview ............................................................................4** Module Description ......................................................4 **Pad Connection Interface ................................................6 Recommended Host PCB Layout ...................................7 Power Supply Connections and Recommended External Components ..................11** Connection Options ...................................................11 External Component Recommendation ....................11 Critical Components List ...........................................14 Antenna Design .........................................................14 **Electrical Specification ..................................................15** GPIO .........................................................................17 XRES .........................................................................18 Analog Peripherals ....................................................18 Digital Peripherals .....................................................22 Serial Communication ...............................................24 Memory .....................................................................25 System Resources ....................................................26 **Environmental Specifications .......................................31** Environmental Compliance .......................................31 RF Certification ..........................................................31 Environmental Conditions .........................................31
ESD and EMI Protection ...........................................31 **Regulatory Information ..................................................32** FCC ...........................................................................32 Industry Canada (IC) Certification .............................33 European R&TTE Declaration of Conformity ............33 MIC Japan .................................................................34 KC Korea ...................................................................34 **Packaging ........................................................................35 Ordering Information ......................................................37** Part Numbering Convention ......................................38 **Acronyms ........................................................................39 Document Conventions .................................................41** Units of Measure .......................................................41 **Document History Page .................................................42 Sales, Solutions, and Legal Information ......................44** Worldwide Sales and Design Support .......................44 Products ....................................................................44 PSoC®Solutions .......................................................44 Cypress Developer Community .................................44 Technical Support .....................................................44
Document Number: 002-00023 Rev. *G
Page 3 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Overview**
## **Module Description**
The CYBLE-014008-00 module is a complete module designed to be soldered to the main host board.
## _Module Dimensions and Drawing_
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
## **Table 1. Module Design Dimensions**
|**Dimension Item**||**Specification**|
|---|---|---|
|Module dimensions|Length (X)|11.00 ± 0.15 mm|
||Width (Y)|11.00 ± 0.15 mm|
|Antenna location dimensions|Length (X)|11.00 ± 0.15 mm|
||Width (Y)|4.62 ± 0.15 mm|
|PCB thickness|Height (H)|0.80 ± 0.10 mm|
|Shield height|Height (H)|1.00 ± 0.10 mm|
|Maximum component height|Height (H)|1.00 mm typical (shield)|
|Total module thickness (bottom of module to highest component)|Height (H)|1.80 mm typical|
See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-014008-00.
Document Number: 002-00023 Rev. *G
Page 4 of 44
**CYBLE-014008-00**
**Figure 1. Module Mechanical Drawing**
## **Top View**
## **Side View**
**==> picture [61 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Bottom View<br>**----- End of picture text -----**<br>
## **Note**
1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Figure 3 on page 6, Figure 4 and Figure 5 on page 7, and Figure 6 and Table 3 on page 8.
Document Number: 002-00023 Rev. *G
Page 5 of 44
**CYBLE-014008-00**
## **Pad Connection Interface**
As shown in the bottom view of Figure 1 on page 5, the CYBLE-014008-00 connects to the host board via solder pads on the back of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-014008-00 module.
**Table 2. Solder Pad Connection Description**
|**Name**|**Connections**|**Connection Type**|**Pad Length Dimension**|**Pad Width Dimension**|**Pad Pitch**|
|---|---|---|---|---|---|
|SP|32|Solder Pads|Pad9/Pad24: 0.74 mm<br>All Others: 0.79 mm|0.41 mm|0.66 mm|
**Figure 2. Solder Pad Dimensions (Seen from Bottom)**
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host board. This placement minimizes the additional recommended keep-out area stated in item 2. Please refer to AN96841 for module placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm).
## **Figure 3. Recommended Host PCB Keep-Out Area Around the CYBLE-014008-00 Trace Antenna**
Document Number: 002-00023 Rev. *G
Page 6 of 44
**CYBLE-014008-00**
## **Recommended Host PCB Layout**
Figure 4 through Figure 6 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBLE-014008-00. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
**Figure 4. Host Layout Pattern for CYBLE-014008-00**
**Figure 5. Module Pad Location from Origin**
Document Number: 002-00023 Rev. *G
Page 7 of 44
**CYBLE-014008-00**
Table 3 provides the center location for each solder pad on the CYBLE-014008-00. All dimensions reference the center of the solder pad. Refer to Figure 6 for the location of each module solder pad.
**Table 3. Module Solder Pad Location**
**Figure 6. Solder Pad Reference Location**
|**Solder Pad**<br>**(Center of Pad)**|**Location (X,Y) from**<br>**Orign (mm)**|**Dimension from**<br>**Orign (mils)**|
|---|---|---|
|1|(0.30, 4.83)|(11.81, 190.16)|
|2|(0.30, 5.49)|(11.81, 216.14)|
|3|(0.30, 6.15)|(11.81, 242.13)|
|4<br>~~es~~|(0.30, 6.81)<br>~~es~~|(11.81, 268.11)|
|5<br>~~es~~|(0.30, 7.47)<br>~~es~~|(11.81, 294.09)|
|6<br>~~es~~<br>~~ee~~|(0.30, 8.13)<br>~~es~~|(11.81, 320.08)|
|7<br>~~ee~~<br>~~po~~|(0.30, 8.79)<br>~~po~~|(11.81, 346.06)<br>~~po~~|
|8<br>~~ee~~<br>~~po~~|(0.30, 9.45)<br>~~po~~|(11.81, 372.05)<br>~~po~~|
|9<br>~~a~~|(0.27, 10.11)<br>~~a~~|(10.63, 398.03)<br>~~a~~|
|10|(1.21, 10.70)|(47.64, 421.26)|
|11|(1.87, 10.70)|(73.62, 421.26)|
|12|(2.53, 10.70)|(99.61, 421.26)|
|13|(3.19, 10.70)|(125.59, 421.26)|
|14|(3.85, 10.70)|(151.57, 421.26)|
|15|(4.51, 10.70)|(177.56, 421.26)|
|16|(5.17, 10.70)|(203.54, 421.26)|
|17|(5.84, 10.70)|(229.92, 421.26)|
|18|(6.50, 10.70)|(255.91, 421.26)|
|19|(7.16, 10.70)|(281.89, 421.26)|
|20|(7.82, 10.70)|(307.87, 421.26)|
|21|(8.48, 10.70)|(333.86, 421.26)|
|22|(9.14, 10.70)|(359.84, 421.26)|
|23|(9.80, 10.70)|(385.83, 421.26)|
|24|(10.73, 10.11)|(422.44, 398.03)|
|25|(10.70, 9.45)|(421.26, 372.05)|
|26|(10.70, 8.79)|(421.26, 346.06)|
|27|(10.70, 8.13)|(421.26, 320.08)|
|28|(10.70, 7.47)|(421.26, 294.09)|
|29|(10.70, 6.81)|(421.26, 268.11)|
|30|(10.70, 6.15)|(421.26, 242.13)|
|31|(10.70, 5.49)|(421.26, 216.14)|
|32|(10.70, 4.83)|(421.26, 190.16)|
Document Number: 002-00023 Rev. *G
Page 8 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on CYBLE-014008-00, the BLE device port-pin, and denotes whether the digital function shown is available for each solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for a single option shown with a ✓ .
## **Table 4. Digital Peripheral Capabilities**
|**Pad**<br>**Number**|**Device**<br>**Port Pin**|**UART**|**SPI**|**I2C**|**TCPWM**[2]|**Cap**<br>**Sense**|**WCO**<br>**Out**|**ECO**<br>**OUT**|**LCD**|**SWD**|**GPIO**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|1|GND[3]|Ground Connection<br><br><br><br><br>||||||||||
|2|P1.1||✓(SCB1_SS1)||✓(TCPWM0_N)<br>|✓<br>|||✓<br>||✓<br>|
|3|P1.0||||✓(TCPWM0_P)<br>|✓<br>|||✓<br>||✓<br>|
|4|P1.5|✓(SCB0_TX) <br>|✓(SCB0_MISO) <br>|✓(SCB0_SCL) <br>|✓(TCPWM2_N)<br>|✓<br>|||✓<br>||✓<br>|
|5|P0.1|✓(SCB1_TX) <br>|✓(SCB1_MISO) <br>|✓(SCB1_SCL)|✓(TCPWM0_N)<br>|✓<br>|||✓<br>||✓<br>|
|6|P0.7|✓(SCB0_CTS)|✓(SCB0_SCLK)||✓(TCPWM2_N)|✓|||✓|✓<br>(SWDCLK)|✓|
|7|VDD|Digital Power Supply Input (1.71 to 5.5V)<br><br><br><br>||||||||||
|8|P1.4|✓(SCB0_RX) <br>|✓(SCB0_MOSI) <br>|✓(SCB0_SDA) <br>|✓(TCPWM2_P)<br>|✓<br>|||✓<br>||✓<br>|
|9|P0.4|✓(SCB0_RX) <br>|✓(SCB0_MOSI) <br>|✓(SCB0_SDA) <br>|✓(TCPWM1_P)<br>|✓<br>||✓|✓<br>||✓<br>|
|10|P0.5|✓(SCB0_TX) <br>|✓(SCB0_MISO) <br>|✓(SCB0_SCL)|✓(TCPWM1_N)|✓|||✓||✓|
|11|P0.6|✓(SCB0_RTS)|✓(SCB0_SS0)<br>||✓(TCPWM2_P)<br>|✓<br>|||✓<br>|✓<br>(SWDIO)|✓<br>|
|12|P1.2||✓(SCB1_SS2)||✓(TCPWM1_P)|✓|||✓||✓|
|13|VDDR|Radio Power Supply (1.9V to 5.5V)<br><br><br>||||||||||
|14|P2.6|||||✓<br>|||✓<br>||✓<br>|
|15|P1.3||✓(SCB1_SS3)||✓(TCPWM1_N)<br>|✓<br>|||✓<br>||✓<br>|
|16|P3.0|✓(SCB0_RX)||✓(SCB0_SDA)|✓(TCPWM0_P)|✓<br>|||✓<br>||✓<br>|
|17|P2.1||✓(SCB0_SS2)<br>|||✓<br>|||✓<br>||✓<br>|
|18|P2.2||✓(SCB0_SS3)|||✓<br>|||✓<br>||✓<br>|
|19|P2.3|||||✓|✓||✓||✓|
|20|VDDA|Analog Power Supply Input (1.71 to 5.5V)<br><br><br><br><br>||||||||||
|21|P3.4|✓(SCB1_RX)<br>||✓(SCB1_SDA) <br>|✓(TCPWM2_P)<br>|✓<br>|||✓<br>||✓<br>|
|22|P3.1|✓(SCB0_TX)<br>||✓(SCB0_SCL)|✓(TCPWM0_N)<br>|✓<br>|||✓<br>||✓<br>|
|23|P3.7|✓(SCB1_CTS)<br>|||✓(TCPWM3_N)<br>|✓<br>|✓||✓<br>||✓<br>|
|24|P3.5|✓(SCB1_TX)<br>||✓(SCB1_SCL)|✓(TCPWM2_N)<br>|✓<br>|||✓<br>||✓<br>|
|25|P3.3|✓(SCB0_CTS)|||✓(TCPWM1_N)|✓|||✓||✓|
|26|VREF|Reference Voltage Input<br><br><br><br><br>||||||||||
|27|P3.2|✓(SCB0_RTS)<br>|||✓(TCPWM1_P)<br>|✓<br>|||✓<br>||✓<br>|
|28|P3.6|✓(SCB1_RTS)|||✓(TCPWM3_P)|✓|||✓||✓|
|29|XRES|External Reset Hardware Connection Input<br><br><br>||||||||||
|30|P2.4|||||✓<br>|||✓<br>||✓<br>|
|31|P2.5|||||✓|||✓||✓|
|32|GND|Ground Connection||||||||||
> 2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.
> 3. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.
**Notes**
Document Number: 002-00023 Rev. *G
Page 9 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 5. Analog Peripheral Capabilities**
|**Pad Number**|**Device Port Pin**|**SARMUX**|**OPAMP**|**LPCOMP**|
|---|---|---|---|---|
|1|GND[3]|Ground Connection<br>|||
|2|P1.1||✓(CTBm1_OA0_INN)<br>||
|3|P1.0||✓(CTBm1_OA0_INP)<br>||
|4|P1.5||✓(CTBm1_OA1_INP)||
|5|P0.1||||
|6|P0.7||||
|7|VDD|Digital Power Supply Input (1.71 to 5.5V)<br>|||
|8|P1.4||✓(CTBm1_OA1_INN)||
|9|P0.4|||✓(COMP1_INP)<br>|
|10|P0.5|||✓(COMP1_INN)|
|11|P0.6||||
|12|P1.2||✓(CTBm1_OA0_OUT)||
|13|VDDR|Radio Power Supply (1.9V to 5.5V)<br>|||
|14|P2.6||✓(CTBm1_OA0_INP)<br>||
|15|P1.3||✓(CTBm1_OA1_OUT)||
|16|P3.0|✓|||
|17|P2.1||✓(CTBm1_OA0_INN)<br>||
|18|P2.2||✓(CTBm1_OA0_OUT)<br>||
|19|P2.3||✓(CTBm1_OA1_OUT)||
|20|VDDA|Analog Power Supply Input (1.71 to 5.5V)<br>|||
|21|P3.4|✓<br>|||
|22|P3.1|✓<br>|||
|23|P3.7|✓<br>|||
|24|P3.5|✓<br>|||
|25|P3.3|✓|||
|26|VREF|Reference Voltage Input (Optional)<br>|||
|27|P3.2|✓<br>|||
|28|P3.6|✓|||
|29|XRES|External Reset Hardware Connection Input<br>|||
|30|P2.4||✓(CTBm1_OA1_INN)<br>||
|31|P2.5||✓(CTBm1_OA1_INP)||
|32|GND|Ground Connection|||
Document Number: 002-00023 Rev. *G
Page 10 of 44
**CYBLE-014008-00**
## **Power Supply Connections and Recommended External Components**
## **Power Connections**
The CYBLE-014008-00 contains three power supply connections, VDD, VDDA, and VDDR. The VDD and VDDA connections supply power for the digital and analog device operation respectively. VDDR supplies power for the device radio.
VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR accepts a supply range of 1.9 V to 5.5 V. These specifications can be found in Table 10. The maximum power supply ripple for both power connections on the module is 100 mV, as shown in Table 8.
The power supply ramp rate of VDD and VDDA must be equal to or greater than that of VDDR when the radio is used.
## **Connection Options**
## **External Component Recommendation**
In either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pin connection.
Figure 7 details the recommended host schematic options for a single supply scenario. The use of one or two ferrite beads will depend on the specific application and configuration of the CYBLE-014008-00.
Figure 8 details the recommended host schematic for an independent supply scenario.
The recommended ferrite bead value is 330 , 100 MHz (Murata BLM21PG331SN1D).
Two connection options are available for any application:
1. Single supply: Connect VDD, VDDA, and VDDR to the same supply.
2. Independent supply: Power VDD, VDDA, and VDDR separately.
**Figure 7. Recommended Host Schematic Options for Single Supply Option**
**Single Ferrite Bead Option**
**Three Ferrite Bead Option**
Document Number: 002-00023 Rev. *G
Page 11 of 44
**CYBLE-014008-00**
**Figure 8. Recommended Host Schematic for Independent Supply Option**
Document Number: 002-00023 Rev. *G
Page 12 of 44
**CYBLE-014008-00**
The CYBLE-014008-00 schematic is shown in Figure 9.
**Figure 9. CYBLE-014008-00 Schematic Diagram**
Document Number: 002-00023 Rev. *G
Page 13 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Critical Components List**
Table 6 details the critical components used in the CYBLE-014008-00 module.
## **Table 6. Critical Component List**
|**Component**|**Reference Designator**|**Description**|
|---|---|---|
|Silicon|U1|68-pin WLCSP Programmable System-on-Chip (PSoC) with BLE|
|Crystal|Y1|24.000 MHz, 10PF|
|Crystal|Y2|32.768 kHz, 12.5PF|
## **Antenna Design**
Table 7 details antenna used on the CYBLE-014008-00 module. The Cypress module performance improves many of these characteristics. For more information, see Table 9 on page 15.
**Table 7. Trace Antenna Specifications**
|**Item**|**Description**|
|---|---|
|Frequency Range|2400 MHz–2500 MHz|
|Peak Gain|0.5 dBi typical|
|Average Gain|–0.5 dBi typical|
|Return Loss|10 dB minimum|
Document Number: 002-00023 Rev. *G
Page 14 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Electrical Specification**
Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module.
## **Table 8. CYBLE-014008-00 Absolute Maximum Ratings**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VDDD_ABS|VDD, VDDAor VDDRsupply relative to VSS(VSSD<br>= VSSA)|–0.5|–|6|V|Absolute maximum|
|VCCD_ABS|Direct digital core voltage input relative to VSSD|–0.5|–|1.95|V|Absolute maximum|
|VDDD_RIPPLE|Maximum power supply ripple for VDD, VDDAand<br>VDDRinput voltage|–|–|100|mV|3.0V supply<br>Ripple frequency of 100 kHz<br>to 750 kHz|
|VGPIO_ABS|GPIO voltage|–0.5|–|VDD+0.5|V|Absolute maximum|
|IGPIO_ABS|Maximum current per GPIO|–25|–|25|mA|Absolute maximum|
|IGPIO_injection|GPIO injection current: Maximum for VIH> VDD<br>and minimum for VIL< VSS|–0.5|–|0.5|mA|Absolute maximum current<br>injected per pin|
|LU|Pin current for latch up|–200||200|mA|–|
Table 9 details the RF characteristics for the Cypress BLE module.
**Table 9. CYBLE-014008-00 RF Performance Characteristics**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|RFO|RF output power on ANT|–18|0|3|dBm|Configurable via register<br>settings|
|RXS|RF receive sensitivity on ANT|–|–87|–|dBm|Guaranteed by design<br>simulation|
|FR|Module frequency range|2400|–|2480|MHz|–|
|GP|Peak gain|–|0.5|–|dBi|–|
|GAvg|Average gain|–|–0.5|–|dBi|–|
|RL|Return loss|–|–10|–|dB|–|
Table 10 through Table 51 list the module level electrical characteristics for the CYBLE-014008-00. All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
**Table 10. CYBLE-014008-00 DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VDD1|Power supply input voltage (VDD =VDDA =VDDR)|1.71|–|5.5|V|With regulator enabled|
|VDD2|Power supply input voltage unregulated<br>(VDD= VDDA= VDDR)|1.71|1.8|1.89|V|Internally unregulated<br>supply|
|VDDR1|Radio supply voltage (radio on)|1.9|–|5.5|V|–|
|VDDR2|Radio supply voltage (radio off)|1.71|–|5.5|V|–|
|**Active Mode, VDD = 1.71V to 5.5 V**|||||||
|IDD3|Execute from flash; CPU at 3 MHz|–|1.7|–|mA|T = 25 °C,<br>VDD= 3.3 V|
|IDD4|Execute from flash; CPU at 3 MHz|–|–|–|mA|T = –40 °C to 85 °C|
|IDD5|Execute from flash; CPU at 6 MHz|–|2.5|–|mA|T = 25 °C,<br>VDD= 3.3 V|
|IDD6|Execute from flash; CPU at 6 MHz|–|–|–|mA|T = –40 °C to 85 °C|
|IDD7|Execute from flash; CPU at 12 MHz|–|4|–|mA|T = 25 °C,<br>VDD= 3.3 V|
Document Number: 002-00023 Rev. *G
Page 15 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 10. CYBLE-014008-00 DC Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IDD8|Execute from flash; CPU at 12 MHz|–|–|–|mA|T = –40 °C to 85 °C|
|IDD9|Execute from flash; CPU at 24 MHz|–|7.1|–|mA|T = 25 °C,<br>VDD= 3.3 V|
|IDD10|Execute from flash; CPU at 24 MHz|–|–|–|mA|T = –40 °C to 85 °C|
|IDD11|Execute from flash; CPU at 48 MHz|–|13.4|–|mA|T = 25 °C,<br>VDD= 3.3 V|
|IDD12|Execute from flash; CPU at 48 MHz|–|–|–|mA|T = –40 °C to 85 °C|
|**Sleep Mode, VDD = 1.71 to 5.5 V**|||||||
|IDD13|IMO on|–|–|–|mA|T = 25 °C, VDD= 3.3 V,<br>SYSCLK = 3 MHz|
|**Sleep Mode, VDD and VDDR = 1.9 to 5.5 V**|||||||
|IDD14|ECO on|–|–|–|mA|T = 25 °C, VDD= 3.3 V,<br>SYSCLK = 3 MHz|
|**Deep-Sleep Mode, VDD = 1.71 to 3.6 V**|||||||
|IDD15|WDT with WCO on|–|1.3|–|µA|T = 25 °C,<br>VDD= 3.3 V|
|IDD16|WDT with WCO on|–|–|–|µA|T = –40 °C to 85 °C|
|IDD17|WDT with WCO on|–|–|–|µA|T = 25 °C,<br>VDD= 5 V|
|IDD18|WDT with WCO on|–|–|–|µA|T = –40 °C to 85 °C|
|**Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)**|||||||
|IDD19|WDT with WCO on|–|–|–|µA|T = 25 °C|
|IDD20|WDT with WCO on|–|–|–|µA|T = –40 °C to 85 °C|
|**Hibernate Mode, VDD = 1.71 to 3.6 V**|||||||
|IDD27|GPIO and reset active|–|150|–|nA|T = 25 °C,<br>VDD= 3.3 V|
|IDD28|GPIO and reset active|–|–|–|nA|T = –40 °C to 85 °C|
|**Hibernate Mode, VDD = 3.6 to 5.5 V**|||||||
|IDD29|GPIO and reset active|–|–|–|nA|T = 25 °C,<br>VDD= 5 V|
|IDD30|GPIO and reset active|–|–|–|nA|T = –40 °C to 85 °C|
|**Stop Mode, VDD = 1.71 to 3.6 V**|||||||
|IDD33|Stop-mode current (VDD)|–|20|–|nA|T = 25 °C,<br>VDD= 3.3 V|
|IDD34|Stop-mode current (VDDR)|–|40|–-|nA|T = 25 °C,<br>VDDR= 3.3 V|
|IDD35|Stop-mode current (VDD)|–|–|–|nA|T = –40 °C to 85 °C|
|IDD36|Stop-mode current (VDDR)|–|–|–|nA|T = –40 °C to 85 °C,<br>VDDR= 1.9 V to 3.6 V|
|**Stop Mode, VDD = 3.6 to 5.5 V**|||||||
|IDD37|Stop-mode current (VDD)|–|–|–|nA|T = 25 °C,<br>VDD= 5 V|
|IDD38|Stop-mode current (VDDR)|–|–|–|nA|T = 25 °C,<br>VDDR= 5 V|
|IDD39|Stop-mode current (VDD)|–|–|–|nA|T = –40 °C to 85 °C|
|IDD40|Stop-mode current (VDDR)|–|–|–|nA|T = –40 °C to 85 °C|
Document Number: 002-00023 Rev. *G
Page 16 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Table 11. AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FCPU|CPU frequency|DC|–|48|MHz|1.71VVDD 5.5V|
|TSLEEP|Wakeup from Sleep mode|–|0|–|µs|Guaranteed by characterization|
|TDEEPSLEEP|Wakeup from Deep-Sleep mode|–|–|25|µs|24-MHz IMO. Guaranteed by<br>characterization|
|THIBERNATE|Wakeup from Hibernate mode|–|–|800|µs|Guaranteed by characterization|
|TSTOP|Wakeup from Stop mode|–|–|2|ms|XRES wakeup|
## **GPIO**
## **Table 12. GPIO DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VIH<br>[4]|Input voltage HIGH threshold|0.7 × VDD|–|–|V|CMOS input|
||LVTTL input, VDD< 2.7V|0.7 × VDD|–|–|V|–|
||LVTTL input, VDD 2.7V|2.0|–|–|V|–|
|VIL|Input voltage LOW threshold|–|–|0.3 × VDD|V|CMOS input|
||LVTTL input, VDD< 2.7V|–|–|0.3 × VDD|V|–|
||LVTTL input, VDD 2.7V|–|–|0.8|V|–|
|VOH|Output voltage HIGH level|VDD– 0.6|–|–|V|IOH= 4 mA at 3.3-V VDD|
||Output voltage HIGH level|VDD– 0.5|–|–|V|IOH= 1 mA at 1.8-V VDD|
|VOL|Output voltage LOW level|–|–|0.6|V|IOL= 8 mA at 3.3-V VDD|
||Output voltage LOW level|–|–|0.6|V|IOL= 4 mA at 1.8-V VDD|
||Output voltage LOW level|–|–|0.4|V|IOL= 3 mA at 3.3-V VDD|
|RPULLUP|Pull-up resistor|3.5|5.6|8.5|k|–|
|RPULLDOWN|Pull-down resistor|3.5|5.6|8.5|k|–|
|IIL|Input leakage current (absolute value)|–|–|2|nA|25 °C, VDD= 3.3V|
|IIL_CTBM|Input leakage on CTBm input pins|–|–|4|nA|–|
|CIN|Input capacitance|–|–|7|pF|–|
|VHYSTTL|Input hysteresis LVTTL|25|40|–|mV|VDD> 2.7V|
|VHYSCMOS|Input hysteresis CMOS|0.05 × VDD|–|–|1|–|
|IDIODE|Current through protection diode to<br>VDD/VSS|–|–|100|µA|–|
|ITOT_GPIO|Maximum total source or sink chip<br>current|–|–|200|mA|–|
> 4. VIH must not exceed VDD + 0.2 V.
**Note**
Document Number: 002-00023 Rev. *G
Page 17 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 13. GPIO AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TRISEF|Rise time in Fast-Strong mode|2|–|12|ns|3.3-V VDDD, CLOAD= 25 pF|
|TFALLF|Fall time in Fast-Strong mode|2|–|12|ns|3.3-V VDDD, CLOAD= 25 pF|
|TRISES|Rise time in Slow-Strong mode|10|–|60|ns|3.3-V VDDD, CLOAD= 25 pF|
|TFALLS|Fall time in Slow-Strong mode|10|–|60|ns|3.3-V VDDD, CLOAD= 25 pF|
|FGPIOUT1|GPIO Fout; 3.3VVDD5.5V<br>Fast-Strong mode|–|–|33|MHz|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOUT2|GPIO Fout; 1.7VVDD3.3V<br>Fast-Strong mode|–|–|16.7|MHz|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOUT3|GPIO Fout; 3.3VVDD5.5V<br>Slow-Strong mode|–|–|7|MHz|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOUT4|GPIO Fout; 1.7VVDD3.3V<br>Slow-Strong mode|–|–|3.5|MHz|90/10%, 25 pF load, 60/40 duty<br>cycle|
|FGPIOIN|GPIO input operating frequency<br>1.71VVDD5.5V|–|–|48|MHz|90/10% VIO|
## **XRES**
## **Table 14. XRES DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VIH|Input voltage HIGH threshold|0.7 × VDDD|–|–|V|CMOS input|
|VIL|Input voltage LOW threshold|–|–|0.3 × VDDD|V|CMOS input|
|RPULLUP|Pull-up resistor|3.5|5.6|8.5|k|–|
|CIN|Input capacitance|–|3|–|pF|–|
|VHYSXRES|Input voltage hysteresis|–|100|–|mV|–|
|IDIODE|Current through protection diode to<br>VDD/VSS|–|–|100|µA|–|
**Table 15. XRES AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TRESETWIDTH|Reset pulse width|1|–|–|µs|–|
## **Analog Peripherals**
_Opamp_
## **Table 16. Opamp Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**IDD(Opamp Block Current. VDD = 1.8V. No Load)**|||||||
|IDD_HI|Power = high|–|1000|1300|µA|–|
|IDD_MED|Power = medium|–|500|–|µA|–|
|IDD_LOW|Power = low|–|250|350|µA|–|
|**GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7V)**|||||||
|GBW_HI|Power = high|6|–|–|MHz|–|
|GBW_MED|Power = medium|4|–|–|MHz|–|
|GBW_LO|Power = low|–|1|–|MHz|–|
Document Number: 002-00023 Rev. *G
Page 18 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 16. Opamp Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**IOUT_MAX(VDDA** **2.7V, 500 mV from Rail)**|||||||
|IOUT_MAX_HI|Power = high|10|–|–|mA|–|
|IOUT_MAX_MID|Power = medium|10|–|–|mA|–|
|IOUT_MAX_LO|Power = low|–|5|–|mA|–|
|**IOUT(VDDA= 1.71V, 500 mV from Rail)**|||||||
|IOUT_MAX_HI|Power = high|4|–|–|mA|–|
|IOUT_MAX_MID|Power = medium|4|–|–|mA|–|
|IOUT_MAX_LO|Power = low|–|2|–|mA|–|
|VIN|Charge pump on, VDDA2.7V|–0.05|–|VDDA– 0.2|V|–|
|VCM|Charge pump on, VDDA2.7V|–0.05|–|VDDA– 0.2|V|–|
|**VOUT(VDDA****2.7V)**|||||||
|VOUT_1|Power = high, ILOAD= 10 mA|0.5|–|VDDA– 0.5|V|–|
|VOUT_2|Power = high, ILOAD= 1 mA|0.2|–|VDDA– 0.2|V|–|
|VOUT_3|Power = medium, ILOAD= 1 mA|0.2|–|VDDA– 0.2|V|–|
|VOUT_4|Power = low, ILOAD=0.1 mA|0.2|–|VDDA– 0.2|V|–|
|VOS_TR|Offset voltage, trimmed|1|±0.5|1|mV|High mode|
|VOS_TR|Offset voltage, trimmed|–|±1|–|mV|Medium mode|
|VOS_TR|Offset voltage, trimmed|–|±2|–|mV|Low mode|
|VOS_DR_TR|Offset voltage drift, trimmed|–10|±3|10|µV/C|High mode|
|VOS_DR_TR|Offset voltage drift, trimmed|–|±10|–|µV/C|Medium mode|
|VOS_DR_TR|Offset voltage drift, trimmed|–|±10|–|µV/C|Low mode|
|CMRR|DC|65|70|–|dB|VDDD= 3.6V,<br>High-power mode|
|PSRR|At 1 kHz, 100-mV ripple|70|85|–|dB|VDDD= 3.6V|
|**Noise**|||||||
|VN1|Input referred, 1 Hz–1 GHz, power = high|–|94|–|µVrms|–|
|VN2|Input referred, 1 kHz, power = high|–|72|–|nV/rtHz|–|
|VN3|Input referred, 10 kHz, power = high|–|28|–|nV/rtHz|–|
|VN4|Input referred, 100 kHz, power = high|–|15|–|nV/rtHz|–|
|CLOAD|Stable up to maximum load. Performance<br>specs at 50 pF.|–|–|125|pF|–|
|Slew_rate|Cload = 50 pF, Power = High,<br>VDDA 2.7V|6|–|–|V/µs|–|
|T_op_wake|From disable to enable, no external RC<br>dominating|–|300|–|µs|–|
|**Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.)**|||||||
|TPD1|Response time; power = high|–|150|–|ns|–|
|TPD2|Response time; power = medium|–|400|–|ns|–|
|TPD3|Response time; power = low|–|2000|–|ns|–|
|Vhyst_op|Hysteresis|–|10|–|mV|–|
|**Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for VDDA > 2.5V)**|||||||
|GBW_DS|Gain bandwidth product|–|50|–|kHz|–|
|IDD_DS|Current|–|15|–|µA|–|
|Vos_DS|Offset voltage|–|5|–|mV|–|
Document Number: 002-00023 Rev. *G
Page 19 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 16. Opamp Specifications** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|Vos_dr_DS|Offset voltage drift|–|20|–|µV/°C|–|
|Vout_DS|Output voltage|0.2|–|VDD–0.2|V|–|
|Vcm_DS|Common mode voltage|0.2|–|VDD–1.8|V|–|
**Table 17. Comparator DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VOFFSET1|Input offset voltage, Factory trim|–|–|±10|mV|–|
|VOFFSET2|Input offset voltage, Custom trim|–|–|±6|mV|–|
|VOFFSET3|Input offset voltage, ultra-low-power mode|–|±12|–|mV|–|
|VHYST|Hysteresis when enabled|–|10|35|mV|–|
|VICM1|Input common mode voltage in normal mode|<br>0|–|VDDD– 0.1|V|Modes 1 and 2|
|VICM2|Input common mode voltage in low-power<br>mode|0|–|VDDD|V|–|
|VICM3|Input common mode voltage in ultra<br>low-power mode|0|–|VDDD– 1.15|<br>V|–|
|CMRR|Common mode rejection ratio|50|–|–|dB|VDDD 2.7V|
|CMRR|Common mode rejection ratio|42|–|–|dB|VDDD 2.7V|
|ICMP1|Block current, normal mode|–|–|400|µA|–|
|ICMP2|Block current, low-power mode|–|–|100|µA|–|
|ICMP3|Block current in ultra-low-power mode|–|6|–|µA|–|
|ZCMP|DC input impedance of comparator|35|–|–|M|–|
**Table 18. Comparator AC Specifications**
|**Parameter**|**Description**|**Min**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|---|
|TRESP1|Response time, normal mode, 50-mV<br>overdrive|–||38|–|ns|50-mV overdrive|
|TRESP2|Response time, low-power mode, 50-mV<br>overdrive|–||70|–|ns|50-mV overdrive|
|TRESP3|Response time, ultra-low-power mode,<br>50-mV overdrive|–||2.3|–|µs|200-mV overdrive|
|_Temperature Sensor_<br>**Table 19. Temperature Sensor Specifications**||||||||
|**Parameter**|**Description**|**Min**|**Typ**||**Max**|**Unit**|**Details/Conditions**|
|TSENSACC|Temperature-sensor accuracy|–5|±1||5|°C|–40 to +85 °C|
Document Number: 002-00023 Rev. *G
Page 20 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
_SAR ADC_
## **Table 20. SAR ADC DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|A_RES|Resolution|–|–|12|bits|–|
|A_CHNIS_S|Number of channels - single-ended|–|–|8|–|8 full-speed|
|A-CHNKS_D|Number of channels - differential|–|–|4|–|Diff inputs use<br>neighboring I/O|
|A-MONO|Monotonicity|–|–|–|–|Yes|
|A_GAINERR|Gain error|–|–|±0.1|%|With external<br>reference|
|A_OFFSET|Input offset voltage|–|–|2|mV|Measured with 1-V<br>VREF|
|A_ISAR|Current consumption|–|–|1|mA|–|
|A_VINS|Input voltage range - single-ended|VSS|–|VDDA|V|–|
|A_VIND|Input voltage range - differential|VSS|–|VDDA|V|–|
|A_INRES|Input resistance|–|–|2.2|k|–|
|A_INCAP|Input capacitance|–|–|10|pF|–|
|VREFSAR|Trimmed internal reference to SAR|–1|–|1|%|Percentage of Vbg<br>(1.024V)|
**Table 21. SAR ADC AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|A_PSRR|Power-supply rejection ratio|70|–|–|dB|Measured at 1-V<br>reference|
|A_CMRR|Common-mode rejection ratio|66|–|–|dB|–|
|A_SAMP|Sample rate|–|–|1|Msps|–|
|Fsarintref|SAR operating speed without external ref.<br>bypass|–|–|100|Ksps|12-bit resolution|
|A_SNR|Signal-to-noise ratio (SNR)|65|–|–|dB|FIN= 10 kHz|
|A_BW|Input bandwidth without aliasing|–|–|A_SAMP/2|kHz|–|
|A_INL|Integral nonlinearity. VDD= 1.71V to 5.5V,<br>1 Msps.|–1.7|–|2|LSB|VREF= 1V to VDD|
|A_INL|Integral nonlinearity. VDDD= 1.71V to 3.6V,<br>1 Msps.|–1.5|–|1.7|LSB|VREF= 1.71V to VDD|
|A_INL|Integral nonlinearity. VDD= 1.71V to 5.5V,<br>500 Ksps.|–1.5|–|1.7|LSB|VREF= 1V to VDD|
|A_dnl|Differential nonlinearity. VDD= 1.71V to 5.5V,<br>1 Msps.|–1|–|2.2|LSB|VREF= 1V to VDD|
|A_DNL|Differential nonlinearity. VDD= 1.71V to 3.6V,<br>1 Msps.|–1|–|2|LSB|VREF= 1.71V to VDD|
|A_DNL|Differential nonlinearity. VDD= 1.71V to 5.5V,<br>500 Ksps.|–1|–|2.2|LSB|VREF= 1V to VDD|
|A_THD|Total harmonic distortion|–|–|–65|dB|FIN= 10 kHz|
Document Number: 002-00023 Rev. *G
Page 21 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
_CSD_
## **Table 22. CSD Block Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VCSD|Voltage range of operation|1.71|–|5.5|V|–|
|IDAC1|DNL for 8-bit resolution|–1|–|1|LSB|–|
|IDAC1|INL for 8-bit resolution|–3|–|3|LSB|–|
|IDAC2|DNL for 7-bit resolution|–1|–|1|LSB|–|
|IDAC2|INL for 7-bit resolution|–3|–|3|LSB|–|
|SNR|Ratio of counts of finger to noise|5|–|–|Ratio|Capacitance range of 9 pF<br>to 35 pF, 0.1-pF sensitivity.<br>Radio is not operating<br>during the scan.|
|IDAC1_CRT1|Output current of IDAC1 (8 bits) in High range|–|612|–|µA|–|
|IDAC1_CRT2|Output current of IDAC1 (8 bits) in Low range|–|306|–|µA|–|
|IDAC2_CRT1|Output current of IDAC2 (7 bits) in High range|–|305|–|µA|–|
|IDAC2_CRT2|Output current of IDAC2 (7 bits) in Low range|–|153|–|µA|–|
## **Digital Peripherals**
_Timer_
## **Table 23. Timer DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|ITIM1|Block current consumption at 3 MHz|–|–|42|µA|16-bit timer|
|ITIM2|Block current consumption at 12 MHz|–|–|130|µA|16-bit timer|
|ITIM3|Block current consumption at 48 MHz|–|–|535|µA|16-bit timer|
**Table 24. Timer AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TTIMFREQ|Operating frequency|FCLK|–|48|MHz|–|
|TCAPWINT|Capture pulse width (internal)|2 × TCLK|–|–|ns|–|
|TCAPWEXT|Capture pulse width (external)|2 × TCLK|–|–|ns|–|
|TTIMRES|Timer resolution|TCLK|–|–|ns|–|
|TTENWIDINT|Enable pulse width (internal)|2 × TCLK|–|–|ns|–|
|TTENWIDEXT|Enable pulse width (external)|2 × TCLK|–|–|ns|–|
|TTIMRESWINT|Reset pulse width (internal)|2 × TCLK|–|–|ns|–|
|TTIMRESEXT|Reset pulse width (external)|2 × TCLK|–|–|ns|–|
Document Number: 002-00023 Rev. *G
Page 22 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
_Counter_
## **Table 25. Counter DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|ICTR1|Block current consumption at 3 MHz|–|–|42|µA<br>|16-bit counter|
|ICTR2|Block current consumption at 12 MHz|–|–|130|µA<br>|16-bit counter|
|ICTR3|Block current consumption at 48 MHz|–|–|535|µA<br>|16-bit counter|
**Table 26. Counter AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TCTRFREQ|Operating frequency|FCLK|–|48|MHz|–|
|TCTRPWINT|Capture pulse width (internal)|2 × TCLK|–|–|ns|–|
|TCTRPWEXT|Capture pulse width (external)|2 × TCLK|–|–|ns|–|
|TCTRES|Counter Resolution|TCLK|–|–|ns|–|
|TCENWIDINT|Enable pulse width (internal)|2 × TCLK|–|–|ns|–|
|TCENWIDEXT|Enable pulse width (external)|2 × TCLK|–|–|ns|–|
|TCTRRESWINT|Reset pulse width (internal)|2 × TCLK|–|–|ns|–|
|TCTRRESWEXT|Reset pulse width (external)|2 × TCLK|–|–|ns|–|
_Pulse Width Modulation (PWM)_
**Table 27. PWM DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IPWM1|Block current consumption at 3 MHz|–|–|42|µA|16-bit PWM|
|IPWM2|Block current consumption at 12 MHz|–|–|130|µA|16-bit PWM|
|IPWM3|Block current consumption at 48 MHz|–|–|535|µA|16-bit PWM|
**Table 28. PWM AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TPWMFREQ|Operating frequency|FCLK|–|48|MHz|–|
|TPWMPWINT|Pulse width (internal)|2 × TCLK|–|–|ns|–|
|TPWMEXT|Pulse width (external)|2 × TCLK|–|–|ns|–|
|TPWMKILLINT|Kill pulse width (internal)|2 × TCLK|–|–|ns|–|
|TPWMKILLEXT|Kill pulse width (external)|2 × TCLK|–|–|ns|–|
|TPWMEINT|Enable pulse width (internal)|2 × TCLK|–|–|ns|–|
|TPWMENEXT|Enable pulse width (external)|2 × TCLK|–|–|ns|–|
|TPWMRESWINT|Reset pulse width (internal)|2 × TCLK|–|–|ns|–|
|TPWMRESWEXT|Reset pulse width (external)|2 × TCLK|–|–|ns|–|
Document Number: 002-00023 Rev. *G
Page 23 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
_LCD Direct Drive_
## **Table 29. LCD Direct Drive DC Specifications**
|**Spec ID**|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|---|
|SID228<br>|ILCDLOW|Operating current in low-power mode|–|17.5|–|µA|16 × 4 small segment<br>display at 50 Hz|
|SID229<br>|CLCDCAP|LCD capacitance per segment/common driver|<br>–|500|5000|pF|–|
|SID230<br>|LCDOFFSET|Long-term segment offset|–|20|–|mV|–|
|SID231<br>|ILCDOP1|LCD system operating current<br>VBIAS= 5V|–|2|–|mA|32 × 4 segments.<br>50 Hz at 25 °C|
|SID232<br>|ILCDOP2|LCD system operating current<br>VBIAS= 3.3V|–|2|–|mA|32 × 4 segments<br>50 Hz at 25 °C|
## **Table 30. LCD Direct Drive AC Specifications**
|**Spec ID**|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|---|
|SID233|FLCD|LCD frame rate|10|50|150|Hz|–|
## **Serial Communication**
**Table 31. Fixed I[2] C DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|II2C1|Block current consumption at 100 kHz|–|–|50|µA|–|
|II2C2|Block current consumption at 400 kHz|–|–|155|µA|–|
|II2C3|Block current consumption at 1 Mbps|–|–|390|µA|–|
|II2C4|I2C enabled in Deep-Sleep mode|–|–|1.4|µA|–|
**Table 32. Fixed I[2] C AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FI2C1|Bit rate|–|–|400|kHz|–|
**Table 33. Fixed UART DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IUART1|Block current consumption at 100 kbps|–|–|55|µA|–|
|IUART2|Block current consumption at 1000 kbps|–|–|312|µA|–|
**Table 34. Fixed UART AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FUART|Bit rate|–|–|1|Mbps|–|
**Table 35. Fixed SPI DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|ISPI1|Block current consumption at 1 Mbps|–|–|360|µA|–|
|ISPI2|Block current consumption at 4 Mbps|–|–|560|µA|–|
|ISPI3|Block current consumption at 8 Mbps|–|–|600|µA|–|
Document Number: 002-00023 Rev. *G
Page 24 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Table 36. Fixed SPI AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FSPI|SPI operating frequency (master; 6x over sampling)|–|–|8|MHz|–|
## **Table 37. Fixed SPI Master Mode AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TDMO|MOSI valid after SCLK driving edge|–|–|18|ns|–|
|TDSI|MISO valid before SCLK capturing edge<br>Full clock, late MISO sampling used|20|–|–|ns|Full clock, late MISO sampling|
|THMO|Previous MOSI data hold time|0|–|–|ns|Referred to Slave capturing edge|
**Table 38. Fixed SPI Slave Mode AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|TDMI|MOSI valid before SCLK capturing edge|40|–|–|ns|
|TDSO|MISO valid after SCLK driving edge|–|–|42 + 3 × TCPU|ns|
|TDSO_ext|MISO Valid after SCLK driving edge in external clock mode.<br>VDD< 3.0V|–|–|50|ns|
|THSO|Previous MISO data hold time|0|–|–|ns|
|TSSELSCK|SSEL valid to first SCK valid edge|100|–|–|ns|
## **Memory**
## **Table 39. Flash DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VPE|Erase and program voltage|1.71|–|5.5|V|–|
|TWS48|Number of Wait states at 32–48 MHz|2|–|–|–|CPU execution from flash|
|TWS32|Number of Wait states at 16–32 MHz|1|–|–|–|CPU execution from flash|
|TWS16|Number of Wait states for 0–16 MHz|0|–|–|–|CPU execution from flash|
## **Table 40. Flash AC Specifications**
|**Parameter**<br>|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TROWWRITE<br>[5]|Row (block) write time (erase and program)|–|–|20|ms|Row (block) = 128 bytes|
|TROWERASE<br>[5]|Row erase time|–|–|13|ms|–|
|TROWPROGRAM<br>[5]|Row program time after erase|–|–|7|ms|–|
|TBULKERASE<br>[5]|Bulk erase time (128 KB)|–|–|35|ms|–|
|TDEVPROG<br>[5]|Total device program time|–|–|25|second<br>s|–|
|FEND|Flash endurance|100 K|–|–|cycles|–|
|FRET|Flash retention. TA 55 °C, 100 K P/E cycles.|20|–|–|years|–|
|FRET2|Flash retention. TA 85 °C, 10 K P/E cycles.|10|–|–|years|–|
## **Note**
> 5. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
Document Number: 002-00023 Rev. *G
Page 25 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **System Resources**
_Power-on-Reset (POR)_
**Table 41. POR DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VRISEIPOR|Rising trip voltage|0.80|–|1.45|V|–|
|VFALLIPOR|Falling trip voltage|0.75|–|1.40|V|–|
|VIPORHYST|Hysteresis|15|–|200|mV|–|
## **Table 42. POR AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TPPOR_TR|Precision power-on reset (PPOR) response<br>time in Active and Sleep modes|–|–|1|µs|–|
## **Table 43. Brown-Out Detect**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VFALLPPOR|BOD trip voltage in Active and Sleep modes|1.64|–|–|V|–|
|VFALLDPSLP|BOD trip voltage in Deep Sleep|1.4|–|–|V|–|
## **Table 44. Hibernate Reset**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VHBRTRIP|BOD trip voltage in Hibernate|1.1|–|–|V|–|
_Voltage Monitors (LVD)_
## **Table 45. Voltage Monitor DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|VLVI1|LVI_A/D_SEL[3:0] = 0000b|1.71|1.75|1.79|V|–|
|VLVI2|LVI_A/D_SEL[3:0] = 0001b|1.76|1.80|1.85|V|–|
|VLVI3|LVI_A/D_SEL[3:0] = 0010b|1.85|1.90|1.95|V|–|
|VLVI4|LVI_A/D_SEL[3:0] = 0011b|1.95|2.00|2.05|V|–|
|VLVI5|LVI_A/D_SEL[3:0] = 0100b|2.05|2.10|2.15|V|–|
|VLVI6|LVI_A/D_SEL[3:0] = 0101b|2.15|2.20|2.26|V|–|
|VLVI7|LVI_A/D_SEL[3:0] = 0110b|2.24|2.30|2.36|V|–|
|VLVI8|LVI_A/D_SEL[3:0] = 0111b|2.34|2.40|2.46|V|–|
|VLVI9|LVI_A/D_SEL[3:0] = 1000b|2.44|2.50|2.56|V|–|
|VLVI10|LVI_A/D_SEL[3:0] = 1001b|2.54|2.60|2.67|V|–|
|VLVI11|LVI_A/D_SEL[3:0] = 1010b|2.63|2.70|2.77|V|–|
|VLVI12|LVI_A/D_SEL[3:0] = 1011b|2.73|2.80|2.87|V|–|
|VLVI13|LVI_A/D_SEL[3:0] = 1100b|2.83|2.90|2.97|V|–|
|VLVI14|LVI_A/D_SEL[3:0] = 1101b|2.93|3.00|3.08|V|–|
|VLVI15|LVI_A/D_SEL[3:0] = 1110b|3.12|3.20|3.28|V|–|
|VLVI16|LVI_A/D_SEL[3:0] = 1111b|4.39|4.50|4.61|V|–|
|LVI_IDD|Block current|–|–|100|µA|–|
Document Number: 002-00023 Rev. *G
Page 26 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 46. Voltage Monitor AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TMONTRIP|Voltage monitor trip time|–|–|1|µs|–|
_SWD Interface_
## **Table 47. SWD Interface Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|F_SWDCLK1|3.3VVDD 5.5V|–|–|14|MHz|SWDCLK1/3 CPU clock frequency|
|F_SWDCLK2|1.71VVDD 3.3V|–|–|7|MHz|SWDCLK1/3 CPU clock frequency|
|T_SWDI_SETUP|T = 1/f SWDCLK|0.25 × T|–|–|ns|–|
|T_SWDI_HOLD|T = 1/f SWDCLK|0.25 × T|–|–|ns|–|
|T_SWDO_VALID|T = 1/f SWDCLK|–|–|0.5 × T|ns|–|
|T_SWDO_HOLD|T = 1/f SWDCLK|1|–|–|ns|–|
_Internal Main Oscillator_
## **Table 48. IMO DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IIMO1<br>|IMO operating current at 48 MHz|–|–|1000|µA|–|
|IIMO2<br>|IMO operating current at 24 MHz|–|–|325|µA|–|
|IIMO3<br>|IMO operating current at 12 MHz|–|–|225|µA|–|
|IIMO4<br>|IMO operating current at 6 MHz|–|–|180|µA|–|
|IIMO5<br>|IMO operating current at 3 MHz|–|–|150|µA|–|
**Table 49. IMO AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|FIMOTOL3|Frequency variation from 3 to 48 MHz|–|–|±2|%|With API-called calibration|
|FIMOTOL3|IMO startup time|–|12|–|µs|–|
_Internal Low-Speed Oscillator_
## **Table 50. ILO DC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|IILO2|ILO operating current at 32 kHz|–|0.3|1.05|µA|–|
**Table 51. ILO AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TSTARTILO1|ILO startup time|–|–|2|ms|–|
|FILOTRIM1|32-kHz trimmed frequency|15|32|50|kHz|–|
## **Table 52. Recommended ECO Trim Value**
|**Parameter**|**Description**|**Value**|**Details/Conditions**|
|---|---|---|---|
|ECOTRIM|24-MHz trim value<br>(firmware configuration)|0x00009595|Recommended trim value that needs to be loaded to register<br>CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG|
Document Number: 002-00023 Rev. *G
Page 27 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Table 53. UDB AC Specifications**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**Data Path performance**|||||||
|FMAX-TIMER|Max frequency of 16-bit timer in a UDB<br>pair|–|–|48|MHz|–|
|FMAX-ADDER|Max frequency of 16-bit adder in a UDB<br>pair|–|–|48|MHz|–|
|FMAX_CRC|Max frequency of 16-bit CRC/PRS in a<br>UDB pair|–|–|48|MHz|–|
|**PLD Performance in UDB**|||||||
|FMAX_PLD|Max frequency of 2-pass PLD function<br>in a UDB pair|–|–|48|MHz|–|
|**Clock to Output Performance**|||||||
|TCLK_OUT_UDB1|Prop. delay for clock in to data out at<br>25 °C, Typical|–|15|–|ns|–|
|TCLK_OUT_UDB2|Prop. delay for clock in to data out,<br>Worst case|–|25|–|ns|–|
**Table 54. BLE Subsystem**
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|**RF Receiver Specification**|||||||
|RXS, IDLE<br>|RX sensitivity with idle transmitter|–|–89|–|dBm|–|
|<br>|RX sensitivity with idle transmitter<br>excluding Balun loss|–|–91|–|dBm|Guaranteed by design<br>simulation|
|RXS, DIRTY<br>|RX sensitivity with dirty transmitter|–|–87|–70|dBm|RF-PHY Specification<br>(RCV-LE/CA/01/C)|
|RXS, HIGHGAIN<br> <br>|RX sensitivity in high-gain mode with idle<br>transmitter|<br>–|–91|–|dBm|–|
|PRXMAX<br>|Maximum input power|–10|–1|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/06/C)|
|CI1<br> <br> <br>|Cochannel interference,<br>Wanted signal at –67 dBm and Interferer<br>at FRX|<br>–|9|21|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI2<br> <br> <br>|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>at FRX ±1 MHz|<br>–|3|15|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI3<br> <br> <br>|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>at FRX ±2 MHz|<br>–|–29|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI4<br> <br> <br>|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>atFRX ±3 MHz|<br>–|–39|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI5<br> <br> <br>|Adjacent channel interference<br>Wanted Signal at –67 dBm and Interferer<br>at Image frequency (FIMAGE)|<br>–|–20|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
|CI3<br> <br> <br>|Adjacent channel interference<br>Wanted signal at –67 dBm and Interferer<br>at Image frequency (FIMAGE± 1 MHz)|<br>–|–30|–|dB|RF-PHY Specification<br>(RCV-LE/CA/03/C)|
Document Number: 002-00023 Rev. *G
Page 28 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 54. BLE Subsystem** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|OBB1|Out-of-band blocking,<br>Wanted signal at –67 dBm and Interferer<br>at F = 30–2000 MHz|–30|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|OBB2|Out-of-band blocking,<br>Wanted signal at –67 dBm and Interferer<br>at F = 2003–2399 MHz|–35|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|OBB3|Out-of-band blocking,<br>Wanted signal at –67 dBm and Interferer<br>at F = 2484–2997 MHz|–35|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|OBB4|Out-of-band blocking,<br>Wanted signal a –67 dBm and Interferer<br>at F = 3000–12750 MHz|–30|–27|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/04/C)|
|IMD|Intermodulation performance<br>Wanted signal at –64 dBm and 1-Mbps<br>BLE, third, fourth, and fifth offset channel|–50|–|–|dBm|RF-PHY Specification<br>(RCV-LE/CA/05/C)|
|RXSE1|Receiver spurious emission<br>30 MHz to 1.0 GHz|–|–|–57|dBm|100-kHz measurement<br>bandwidth<br>ETSI EN300 328 V1.8.1|
|RXSE2|Receiver spurious emission<br>1.0 GHz to 12.75 GHz|–|–|–47|dBm|1-MHz measurement<br>bandwidth<br>ETSI EN300 328 V1.8.1|
|**RF Transmitter Specifications**|||||||
|TXP, ACC|RF power accuracy|–|±1|–|dB|–|
|TXP, RANGE|RF power control range|–|20|–|dB|–|
|TXP, 0dBm|Output power, 0-dB Gain setting (PA7)|–|0|–|dBm|–|
|TXP, MAX|Output power, maximum power setting<br>(PA10)|–|3|–|dBm|–|
|TXP, MIN|Output power, minimum power setting<br>(PA1)|–|–18|–|dBm|–|
|F2AVG|Average frequency deviation for<br>10101010 pattern|185|–|–|kHz|RF-PHY Specification<br>(TRM-LE/CA/05/C)|
|F1AVG|Average frequency deviation for<br>11110000 pattern|225|250|275|kHz|RF-PHY Specification<br>(TRM-LE/CA/05/C)|
|EO|Eye opening =F2AVG/F1AVG|0.8|–|–||RF-PHY Specification<br>(TRM-LE/CA/05/C)|
|FTX, ACC|Frequency accuracy|–150|–|150|kHz|RF-PHY Specification<br>(TRM-LE/CA/06/C)|
|FTX, MAXDR|Maximum frequency drift|–50|–|50|kHz|RF-PHY Specification<br>(TRM-LE/CA/06/C)|
|FTX, INITDR|Initial frequency drift|–20|–|20|kHz|RF-PHY Specification<br>(TRM-LE/CA/06/C)|
|FTX, DR|Maximum drift rate|–20|–|20|kHz/50 µs|RF-PHY Specification<br>(TRM-LE/CA/06/C)|
|IBSE1|In-band spurious emission at 2-MHz<br>offset|–|–|–20|dBm|RF-PHY Specification<br>(TRM-LE/CA/03/C)|
|IBSE2|In-band spurious emission at3-MHz<br>offset|–|–|-30|dBm|RF-PHY Specification<br>(TRM-LE/CA/03/C)|
|TXSE1|Transmitter spurious emissions<br>(average), <1.0 GHz|–|–|-55.5|dBm|FCC-15.247|
Document Number: 002-00023 Rev. *G
Page 29 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 54. BLE Subsystem** (continued)
|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details/Conditions**|
|---|---|---|---|---|---|---|
|TXSE2|Transmitter spurious emissions<br>(average), >1.0 GHz|–|–|-41.5|dBm|FCC-15.247|
|**RF Current Specifications**|||||||
|IRX|Receive current in normal mode|–|18.7|–|mA|–|
|IRX_RF|Radio receive current in normal mode|–|16.4|–|mA|Measured at VDDR|
|IRX, HIGHGAIN|Receive current in high-gain mode|–|21.5|–|mA|–|
|ITX, 3dBm|TX current at 3-dBm setting (PA10)|–|20|–|mA|–|
|ITX, 0dBm|TX current at 0-dBm setting (PA7)|–|16.5|–|mA|–|
|ITX_RF, 0dBm|Radio TX current at 0 dBm setting (PA7)|–|15.6|–|mA|Measured at VDDR|
|ITX_RF, 0dBm|Radio TX current at 0 dBm excluding<br>Balun loss|–|14.2|–|mA|Guaranteed by design<br>simulation|
|ITX,-3dBm|TX current at –3-dBm setting (PA4)|–|15.5|–|mA|–|
|ITX,-6dBm|TX current at –6-dBm setting (PA3)|–|14.5|–|mA|–|
|ITX,-12dBm|TX current at –12-dBm setting (PA2)|–|13.2|–|mA|–|
|ITX,-18dBm|TX current at –18-dBm setting (PA1)|–|12.5|–|mA|–|
|Iavg_1sec, 0dBm|Average current at 1-second BLE<br>connection interval|–|17.1|–|µA|TXP: 0 dBm; ±20-ppm<br>master and slave clock<br>accuracy.<br>For empty PDU exchange|
|Iavg_4sec, 0dBm|Average current at 4-second BLE<br>connection interval|–|6.1|–|µA|TXP: 0 dBm; ±20-ppm<br>master and slave clock<br>accuracy.<br>For empty PDU exchange|
|**General RF Specifications**|||||||
|FREQ|RF operating frequency|2400|–|2482|MHz|–|
|CHBW|Channel spacing|–|2|–|MHz|–|
|DR|On-air data rate|–|1000|–|kbps|–|
|IDLE2TX|BLE.IDLE to BLE. TX transition time|–|120|140|µs|–|
|IDLE2RX|BLE.IDLE to BLE. RX transition time|–|75|120|µs|–|
|**RSSI Specifications**|||||||
|RSSI, ACC|RSSI accuracy|–|±5|–|dB|–|
|RSSI, RES|RSSI resolution|–|1|–|dB|–|
|RSSI, PER|RSSI sample period|–|6|–|µs|–|
Document Number: 002-00023 Rev. *G
Page 30 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Environmental Specifications**
## **Environmental Compliance**
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
## **RF Certification**
The CYBLE-014008-00 module is certified under the following RF certification standards:
■ FCC ID: WAP4008
■ CE
- IC: 7922A-4008
- MIC: 203-JN0505
■ KC: MSIP-CRM-Cyp-4008
## **Environmental Conditions**
Table 55 describes the operating and storage conditions for the Cypress BLE module.
## **Table 55. Environmental Conditions for CYBLE-014008-00**
|**Description**|**Minimum Specification**|**Maximum Specification**|
|---|---|---|
|Operating temperature|–40 °C|85 °C|
|Operating humidity (relative, non-condensation)|5%|85%|
|Thermal ramp rate|–|3 °C/minute|
|Storage temperature|–40 °C|85 °C|
|Storage temperature and humidity|–|85 °C at 85%|
|ESD: Module integrated into system<br>Components[6]|–|15 kV Air<br>2.2 kV Contact|
## **ESD and EMI Protection**
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
**Device Handling** : Proper ESD protocol must be followed in manufacturing to ensure component reliability.
> 6. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
**Note**
Document Number: 002-00023 Rev. *G
Page 31 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Regulatory Information**
## **FCC**
## FCC NOTICE:
The device CYBLE-014008-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
## CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna.
■ Increase the separation between the equipment and receiver.
■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
■ Consult the dealer or an experienced radio/TV technician for help
## LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP4008.
In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"
## ANTENNA WARNING:
This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 14. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.
## RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-014008-00 is far below the FCC radio frequency exposure limits. Nevertheless, use CYBLE-014008-00 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-00023 Rev. *G
Page 32 of 44
**CYBLE-014008-00**
## **Industry Canada (IC) Certification**
CYBLE-014008-00 is licensed to meet the regulatory requirements of Industry Canada (IC),
## License: IC: 7922A-4008
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 7 on page 14, having a maximum gain of 0.5 dBi. Antennas not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
## IC NOTICE:
The device CYBLE-014008-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
## IC RADIATION EXPOSURE STATEMENT FOR CANADA
This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
## LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-4008".
## **European R&TTE Declaration of Conformity**
Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-014008-00 complies with the essential requirements and other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the Directive 1999/5/EC, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-014008-00 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.
Document Number: 002-00023 Rev. *G
Page 33 of 44
**CYBLE-014008-00**
## **MIC Japan**
CYBLE-014008-00 is certified as a module with type certification number 203-JN0505. End products that integrate CYBLE-014008-00 do not need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
## **KC Korea**
CYBLE-014008-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008.
Document Number: 002-00023 Rev. *G
Page 34 of 44
**CYBLE-014008-00**
## **Packaging**
## **Table 56. Solder Reflow Peak Temperature**
|**Module Part Number**|**Package**|**Maximum Peak Temperature**|**Maximum Time at PeakTemperature**|**No. of Cycles**|
|---|---|---|---|---|
|CYBLE-014008-00|32-pad SMT|260 °C|30 seconds|2|
**Table 57. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2**
|**Module Part Number**|**Package**|**MSL**|
|---|---|---|
|CYBLE-014008-00|32-pad SMT|MSL 3|
The CYBLE-014008-00 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-014008-00.
**Figure 10. CYBLE-014008-00 Tape Dimensions**
Figure 11 details the orientation of the CYBLE-014008-00 in the tape as well as the direction for unreeling.
**Figure 11. Component Orientation in Tape and Unreeling Direction**
Document Number: 002-00023 Rev. *G
Page 35 of 44
**CYBLE-014008-00**
Figure 12 details reel dimensions used for the CYBLE-014008-00.
**Figure 12. Reel Dimensions**
The CYBLE-014008-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBLE-014008-00 is detailed in Figure 13.
Document Number: 002-00023 Rev. *G
Page 36 of 44
**CYBLE-014008-00**
**Figure 13. CYBLE-014008-00 Center of Mass**
## **Ordering Information**
Table 58 lists the CYBLE-014008-00 part number and features. Table 59 lists the reel shipment quantities for the CYBLE-014008-00.
**Table 58. Ordering Information**
|**MPN**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Features**|**Package**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**Max CPU Speed (MHz)**|**Flash (KB)**|**SRAM (KB)**|**UDB**|**Opamp (CTBm)**|**CapSense**|**Direct LCD Drive**|**12-bit SAR ADC**|**LP Comparators**|**TCPWM Blocks**|**SCB Blocks**|**PWMs (using UDBs)**|**I2S (using UDB)**|**GPIO**||
|CYBLE-014008-00|48|128|16|4|4|✓|✓|1 Msps|1|4|2|4|✓|25|32-SMT|
**Table 59. Tape and Reel Package Quantity and Minimum Order Amount**
|**Description**|**Minimum Reel Quantity**|**Maximum Reel Quantity**|**Comments**|
|---|---|---|---|
|Reel Quantity|500|500|Ships in 500 unit reel quantities.|
|Minimum Order Quantity (MOQ)|500|–||
|Order Increment (OI)|500|–||
The CYBLE-014008-00 is offered in tape and reel packaging. The CYBLE-014008-00 ships with a maximum of 500 units/reel.
Document Number: 002-00023 Rev. *G
Page 37 of 44
**CYBLE-014008-00**
## **Part Numbering Convention**
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website.
|U.S. Cypress Headquarters Address|198 Champion Court, San Jose, CA 95134|
|---|---|
|U.S. Cypress Headquarter Contact Info|(408) 943-2600|
|Cypress website address|http://www.cypress.com|
Document Number: 002-00023 Rev. *G
Page 38 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Acronyms**
**Table 60. Acronyms Used in this Document**
|**Acronym**|**Description**|
|---|---|
|ABUS|analog local bus|
|ADC|analog-to-digital converter|
|AG|analog global|
|AHB|AMBA (advanced microcontroller bus<br>architecture) high-performance bus, an ARM<br>data transfer bus|
|ALU|arithmetic logic unit|
|AMUXBUS|analog multiplexer bus|
|API|application programming interface|
|APSR|application program status register|
|ARM®|advanced RISC machine, a CPU architecture|
|ATM|automatic thump mode|
|BLE|Bluetooth Low Energy|
|Bluetooth<br>SIG|Bluetooth Special Interest Group|
|BW|bandwidth|
|CAN|Controller Area Network, a communications<br>protocol|
|CE|European Conformity|
|CSA|Canadian Standards Association|
|CMRR|common-mode rejection ratio|
|CPU|central processing unit|
|CRC|cyclic redundancy check, an error-checking<br>protocol|
|DAC|digital-to-analog converter, see also IDAC, VDAC|
|DFB|digital filter block|
|DIO|digital input/output, GPIO with only digital<br>capabilities, no analog. See GPIO.|
|DMIPS|Dhrystone million instructions per second|
|DMA|direct memory access, see also TD|
|DNL|differential nonlinearity, see also INL|
|DNU|do not use|
|DR|port write data registers|
|DSI|digital system interconnect|
|DWT|data watchpoint and trace|
|ECC|error correcting code|
|ECO|external crystal oscillator|
|EEPROM|electrically erasable programmable read-only<br>memory|
|EMI|electromagnetic interference|
**Table 60. Acronyms Used in this Document** (continued)
|**Acronym**|**Description**|
|---|---|
|EMIF|external memory interface|
|EOC|end of conversion|
|EOF|end of frame|
|EPSR|execution program status register|
|ESD|electrostatic discharge|
|ETM|embedded trace macrocell|
|FCC|Federal Communications Commission|
|FET|field-effect transistor|
|FIR|finite impulse response, see also IIR|
|FPB|flash patch and breakpoint|
|FS|full-speed|
|GPIO|general-purpose input/output, applies to a PSoC<br>pin|
|HCI|host controller interface|
|HVI|high-voltage interrupt, see also LVI, LVD|
|IC|integrated circuit|
|IDAC|current DAC, see also DAC, VDAC|
|IDE|integrated development environment|
|I2C, or IIC|Inter-Integrated Circuit, a communications<br>protocol|
|IC|Industry Canada|
|IIR|infinite impulse response, see also FIR|
|ILO|internal low-speed oscillator, see also IMO|
|IMO|internal main oscillator, see also ILO|
|INL|integral nonlinearity, see also DNL|
|I/O|input/output, see also GPIO, DIO, SIO, USBIO|
|IPOR|initial power-on reset|
|IPSR|interrupt program status register|
|IRQ|interrupt request|
|ITM|instrumentation trace macrocell|
|KC|Korea Certification|
|LCD|liquid crystal display|
|LIN|Local Interconnect Network, a communications<br>protocol.|
|LR|link register|
|LUT|lookup table|
|LVD|low-voltage detect, see also LVI|
|LVI|low-voltage interrupt, see also HVI|
|LVTTL|low-voltage transistor-transistor logic|
Document Number: 002-00023 Rev. *G
Page 39 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
**Table 60. Acronyms Used in this Document** (continued)
|**Acronym**|**Description**|
|---|---|
|MAC|multiply-accumulate|
|MCU|microcontroller unit|
|MIC|Ministry of Internal Affairs and Communications<br>(Japan)|
|MISO|master-in slave-out|
|NC|no connect|
|NMI|nonmaskable interrupt|
|NRZ|non-return-to-zero|
|NVIC|nested vectored interrupt controller|
|NVL|nonvolatile latch, see also WOL|
|Opamp|operational amplifier|
|PAL|programmable array logic, see also PLD|
|PC|program counter|
|PCB|printed circuit board|
|PGA|programmable gain amplifier|
|PHUB|peripheral hub|
|PHY|physical layer|
|PICU|port interrupt control unit|
|PLA|programmable logic array|
|PLD|programmable logic device, see also PAL|
|PLL|phase-locked loop|
|PMDD|package material declaration data sheet|
|POR|power-on reset|
|PRES|precise power-on reset|
|PRS|pseudo random sequence|
|PS|port read data register|
|PSoC®|Programmable System-on-Chip™|
|PSRR|power supply rejection ratio|
|PWM|pulse-width modulator|
|QDID|qualification design ID|
|RAM|random-access memory|
|RISC|reduced-instruction-set computing|
|RMS|root-mean-square|
|RTC|real-time clock|
|RTL|register transfer language|
|RTR|remote transmission request|
|RX|receive|
|SAR|successive approximation register|
|SC/CT|switched capacitor/continuous time|
|SCL|I2C serial clock|
**Table 60. Acronyms Used in this Document** (continued)
|**Acronym**|**Description**|
|---|---|
|SDA|I2C serial data|
|S/H|sample and hold|
|SINAD|signal to noise and distortion ratio|
|SIO|special input/output, GPIO with advanced<br>features. See GPIO.|
|SMT|surface-mount technology; a method for<br>producing electronic circuitry in which the<br>components are placed directly onto the surface<br>of PCBs|
|SOC|start of conversion|
|SOF|start of frame|
|SPI|Serial Peripheral Interface, a communications<br>protocol|
|SR|slew rate|
|SRAM|static random access memory|
|SRES|software reset|
|STN|super twisted nematic|
|SWD|serial wire debug, a test protocol|
|SWV|single-wire viewer|
|TD|transaction descriptor, see also DMA|
|THD|total harmonic distortion|
|TIA|transimpedance amplifier|
|TN|twisted nematic|
|TRM|technical reference manual|
|TTL|transistor-transistor logic|
|TUV|Germany: Technischer Überwachungs-Verein<br>(Technical Inspection Association)|
|TX|transmit|
|UART|Universal Asynchronous Transmitter Receiver, a<br>communications protocol|
|UDB|universal digital block|
|USB|Universal Serial Bus|
|USBIO|USB input/output, PSoC pins used to connect to<br>a USB port|
|VDAC|voltage DAC, see also DAC, IDAC|
|WDT|watchdog timer|
|WOL|write once latch, see also NVL|
|WRES|watchdog timer reset|
|XRES|external reset I/O pin|
|XTAL|crystal|
Document Number: 002-00023 Rev. *G
Page 40 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Document Conventions**
## **Units of Measure**
## **Table 61. Units of Measure**
|**Symbol**|**Unit of Measure**|
|---|---|
|°C|degrees Celsius|
|dB|decibel|
|dBm|decibel-milliwatts|
|fF|femtofarads|
|Hz|hertz|
|KB|1024 bytes|
|kbps|kilobits per second|
|Khr|kilohour|
|kHz|kilohertz|
|k|kilo ohm|
|ksps|kilosamples per second|
|LSB|least significant bit|
|Mbps|megabits per second|
|MHz|megahertz|
|M|mega-ohm|
|Msps|megasamples per second|
|µA|microampere|
|µF|microfarad|
|µH|microhenry|
|µs|microsecond|
|µV|microvolt|
|µW|microwatt|
|mA|milliampere|
|ms|millisecond|
|mV|millivolt|
|nA|nanoampere|
|ns|nanosecond|
|nV|nanovolt|
||ohm|
|pF|picofarad|
|ppm|parts per million|
|ps|picosecond|
|s|second|
|sps|samples per second|
|sqrtHz|square root of hertz|
|V|volt|
Document Number: 002-00023 Rev. *G
Page 41 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Document History Page**
**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC[®] Module Document Number: 002-00023**
|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|**|4895738|DSO|8/26/2015|Preliminary datasheet for CYBLE-014008-00 module.|
|*A|4910660|DSO|9/07/2015|Modify reference of VDD/VDDA minimum voltage from 1.8V to 1.71V.<br>UpdateTable 2on page 6 Connections number from 21 to 32.<br>Remove Footnotes 4, 5, and 6 on Page 8.<br>UpdateTable 5on page 10 to remove LPCOMP capabilities from Pads 2, 3, 4,<br>14, 30, and 31.<br>UpdateTable 5on page 10 to specify Vref (Pad 26) as Optional.<br>UpdateFigure 7on page 11 to swap diagram descriptions.<br>UpdateTable 11on page 17 THibernatefrom 2 ms to 800 µs.<br>UpdateTable 54on page 28 - changed power consumption Iavg_1sec from<br>18.5 mA to 17.1 mA.<br>UpdateTable 54on page 28 - changed power consumption Iavg_4sec from<br>6.25 mA to 6.1 mA.|
|*B|4944131|DSO|09/25/2015|UpdateTable 3on page 8 to correct a typo in seventh row - changed “Distance<br>from top right corner to Pad 6 center” to ““Distance from Pad 5 center to Pad<br>6 center”.<br>Corrected Footnotes 3 to specify ground connection as Pad 1 and Pad 32.<br>Added VDDAto VDDD_RIPPLEspecification descriptionTable 8on page 15.<br>UpdateTable 10on page 15, parameters VDD1and VDD2to specify that<br>VDD= VDDA= VDDR<br>Removed Table 14 (OVT GPIO DC Specifications) and Table 15 (OVT GPIO<br>AC Specifications).<br>Added regulatory certification country inRF Certificationon page 31.<br>AddedDocument History Pagesection on page 42.|
|*C|5060713|DSO|01/07/2016|UpdateGeneral Descriptionto add reference link to PSoC®4 BLE datasheet<br>and include Declaration ID number.<br>AddedMore Informationsection to the datasheet.<br>UpdatedFigure 1,Figure 2,Figure 3, andFigure 4to improve clarity and<br>viewing.<br>AddedFigure 5inRecommended Host PCB Layoutsection to show solder pad<br>location from module origin.<br>UpdatedFigure 6andTable 3inRecommended Host PCB Layoutsection to<br>show solder pad location from module origin.<br>UpdateRegulatory Informationsection to include final FCC, IC, and KC<br>certification identification numbers.<br>Added French translation for IC Radiation Exposure Statement For Canada in<br>Industry Canada (IC) Certificationsection on page 33 in accordance with IC<br>requirements.<br>UpdatedMIC Japansection on page 34 to specify final MIC certification<br>number.<br>AddedPackagingsection.<br>AddedTable 56andTable 57on page 35.|
|*D|5099201|DSO|01/22/2016|Remove Preliminary from datasheet header and release as final.<br>UpdateMore Informationsection to add KBA210574 (Certification Test<br>Reports) to reference list.<br>UpdateGeneral Descriptionto include reference and link for QDID and<br>Declaration ID.<br>Updated orientation of module drawings inFigure 1,Figure 2,Figure 3,<br>Figure 4,Figure 5,Figure 6,Figure 7,Figure 8,Figure 9, andFigure 13to<br>match<br>orientation in PSoC Creator.|
Document Number: 002-00023 Rev. *G
Page 42 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Document History Page** (continued)
## **Document Title: CYBLE-014008-00, EZ-BLE™ PSoC[®] Module Document Number: 002-00023**
|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|**Document Title: CYBLE-014008-00, EZ-BLE™ PSoC® Module**<br>**Document Number: 002-00023**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|*E|5146846|DSO|02/22/2016|UpdatedTable 4to add Positive (P) and Negative (N) indicator to TCPWM<br>functionalities.|
|*F|5152410|DSO|02/26/2016|UpdatedUp to 25 Programmable GPIOs.|
|*G|5424383|DSO|09/02/2016|UpdatedGeneral Description:<br>UpdatedPower Consumption:<br>Replaced “Stop: 60 nA with XRES wakeup” with “Stop: 60 nA with GPIO (P2.2)<br>or XRES wakeup” under “Low power mode support”.<br>UpdatedMore Information:<br>Added additional Knowledge Base Article references.<br>UpdatedElectrical Specification:<br>UpdatedSystem Resources:<br>UpdatedInternal Low-Speed Oscillator:<br>UpdatedTable 52(Updated details in “Value” column corresponding to<br>ECOTRIMparameter).<br>UpdatedOrdering Information:<br>No change in part numbers.<br>AddedTable 59(To specify minimum and maximum reel quantities that ship<br>for orders of the CYBLE-014008-00 module).<br>Updated to new template.|
Document Number: 002-00023 Rev. *G
Page 43 of 44
**CYBLE-014008-00**
**==> picture [120 x 47] intentionally omitted <==**
## **Sales, Solutions, and Legal Information**
## **Worldwide Sales and Design Support**
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
## **Products**
ARM[®] Cortex[®] Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Lighting & Power Control cypress.com/powerpsoc Memory cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless
## **PSoC[®] Solutions**
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
## **Cypress Developer Community**
Forums | Projects | Video | Blogs | Training | Components
## **Technical Support**
cypress.com/support
© Cypress Semiconductor Corporation, 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00023 Rev. *G
Revised September 2, 2016
Page 44 of 44
Updated at April 28, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →