BTHQ21603V-SRE WC

**Feb/2002** 

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## _**BATRON**_ 

DOCUMENT NUMBER AND REVISION **VL-FS-BTHQ 21603VSS-01 REV.B (BTHQ 21603V-SRE-CONN.)** 

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## DISTRIBUTION LIST: MARKETING 

## **DOCUMENT  REVISION  HISTORY 1:** 

|DOCUMENT|DATE|DESCRIPTION||CHANGED|CHECKED|
|---|---|---|---|---|---|
|REVISION||||BY|BY|
|FROM   TO||||||
|A|2002.01.04|First Release||PHILIP|TOM LEE|
|||||CHENG||
|A         B|2002.01.14|Items 1 to 3 were updated:||PHILIP|M.Y.LU|
|||1.) (Page 4, point 1)||CHENG||
|||“(CON-IL-402)” was added.||||
|||2.)(Page 4, point 2)||||
|||“(Excluded<br>connector)”|was|was||
|||added.||||
|||3.)(Page 5, Fig. 1)||||
|||Outline drawing was updated.|Outline drawing was updated.|||



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## **CONTENTS** 

||**CONTENTS**||
|---|---|---|
|||Page No.|
|1.|GENERAL  DESCRIPTION|4|
|2.|MECHANICAL  SPECIFICATIONS|4|
|3.|ABSOLUTE  MAXIMUM  RATINGS|6|
|3.1|ELECTRICAL  MAXIMUM  RATINGS (Ta=25°C)|6|
|3.2|ENVIRONMENTAL  CONDITION|6|
|4.|ELECTRICAL  SPECIFICATIONS|7|
|4.1|INTERFACE  SIGNALS|7|
|4.2|TYPICAL ELECTRICAL CHARACTERISTICS|8|
|4.3|TIMING SPECIFICATIONS|9|
|4.4|TIMING DIAGRAM OF VDD AGAINST V0|11|
|4.5|CORRESPONDENCE BETWEEN CHARACTER CODES AND|12|
||CHARACTER PATTERNS (NOVATEK STANDARD NT3881D-01)||



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## **Specification of LCD Module Type Item No.: BTHQ 21603VSS-01** 

## **1. General Description** 

- 16 characters (5x8 dots) x 2 lines STN Positive Yellow Reflective Dot Matrix LCD module. 

- Viewing Angle: 6 O’clock direction. 

- Driving scheme: 1/16 Duty, 1/5 bias. 

- ‘NOVATEK’ NT3881DH-01/AI (Die form) LCD Controller and Driver or equivalent 

- ’SAMSUNG’ KS0065B-PCC (Die form) or equivalent 40-Channel Segment/Common Driver 

- for Dot Matrix LCD. 

- Connector: 16 pins ZIF SMD connector (CON-IL-402). 

## **2.  Mechanical Specifications** 

The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. 

Table 1 

|Table 1|Table 1|Table 1|
|---|---|---|
||||
|Parameter|Specifications|Unit|
|Outline dimensions|53.0(W)x 20.0(H)x 8.0 MAX.(D) (Excluded connector)|mm|
|Effective viewingarea|36.0(W)x 10.0(H)|mm|
|Displayformat|16 characters x 2 lines|-|
|Character size|1.85(W)x 3.15(H) (5 x 8 dots)|mm|
|Character spacing|0.30(W)x 1.10(H)|mm|
|Characterpitch|2.15(W)x 4.25(H)|mm|
|Dot size|0.358(W)x 0.381(H)|mm|
|Dot spacing|0.015(W)x 0.015(H)|mm|
|Dotpitch|0.373(W)x 0.396(H)|mm|
|Weight:|TBD|grams|



D 

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## **3. Absolute Maximum Ratings** 

## **3.1 Electrical Maximum Ratings(Ta = 25 ºC)** 

## Table 2 

|Parameter|Symbol|Min.|Max.|Unit|
|---|---|---|---|---|
|Power Supplyvoltage(Logic)|VDD - VSS|-0.3|+7.0|V|
|Power Supplyvoltage(LCD drive)|VLCD=VDD – V0|-0.3|+13.5|V|
|Input voltage|Vin|-0.3|VDD +0.3|V|



Note: 

The modules may be destroyed if they are used beyond the absolute maximum ratings. All voltage values are referenced to VSS = 0V. 

## **3.2 Environmental Condition** 

## Table 3 

|Item|Operating<br>Temperature<br>(Topr)|Operating<br>Temperature<br>(Topr)|Storage<br>Temperature<br>(Tstg)|Storage<br>Temperature<br>(Tstg)|Remark|
|---|---|---|---|---|---|
||Min.|Max.|Min.|Max.||
|Ambient Temperature|0°C|+50°C|-10°C|+60°C|Dry|
|Humidity|95% max. RH for Ta≤40°C<br>< 95%RH for Ta > 40°C||||no condensation|
|Vibration (IEC 68-2-6)<br>cells must be mounted<br>on a suitable connector|Frequency:  10∼55 Hz<br>Amplitude:  0.75 mm<br>Duration: 20 cycles in each direction.||||3 directions|
|Shock (IEC 68-2-27)<br>Half-sine pulse shape|Pulse duration : 11 ms<br>Peak acceleration: 981 m/s2 = 100g<br>Number of shocks : 3 shocks in 3<br>mutually perpendicular axes.||||3 directions|



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## **4.  Electrical Specifications** 

## **4.1 Interface signals** 

Table 4 

|Pin No.|Symbol|Description|
|---|---|---|
|1|VSS|Ground(0V).|
|2|VDD|Power supplyfor logic(+5V)|
|3|V0|Power supplyfor LCD driver|
|4|RS|Register Select Input:<br>“High” for Data register (for read and write)<br>”Low” for Instruction register (for write),<br>Busyflag,address counter(for read)|
|5|R/W|Read/Write signal:<br>” High” for Read mode.<br>“Low” for Write mode.|
|6|E|Enable.<br>Start signal for data read /write.|
|7|DB0|Data input/output(LSB)|
|8|DB1|Data input/output|
|9|DB2|Data input/output|
|10|DB3|Data input/output|
|11|DB4|Data input/output|
|12|DB5|Data input/output|
|13|DB6|Data input/output|
|14|DB7|Data input/output(MSB)|
|15|LED(+)|Anode of LED backlight|
|16|LED(-)|Cathode of LED backlight|



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## **4.2   Typical Electrical Characteristics** 

## **At Ta = 25 ° C, VDD = 5V ± 5%, VSS=0V.** 

Table 5 

|Parameter|Symbol|Conditions|Min.|Typ.|Max.|Unit|
|---|---|---|---|---|---|---|
|Supplyvoltage(Logic)|VDD-VSS|VDD-VSS|4.75|5.00|5.25|V|
|Supply voltage (LCD)|VLCD<br>=VDD-V0|VDD =5.0V,<br>Note1.|4.0|4.5|5.0|V|
|Input signal voltage 1<br>for E,DB0-DB7,R/W,RS.|VIH1|”H” level|2.2|-|VDD|V|
||VIL1|” L” level|-0.3|-|0.8|V|
|Input signal voltage 2<br>for OSC1.|VIH2|” H” level|VDD -1.0|-|VDD|V|
||VIL2|” L” level|VSS|-|1.0|V|
|Supply Current<br>(Logic & LCD)|IDD|Character mode,<br>Note 1|-|1.3|2.0|mA|
|Supply Current (LCD)|I0|Character mode,<br>Note 1|-|0.2|0.3|mA|



Note (1) :  There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. 

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## **4.3 Timing Specifications** 

At Ta = 0 °C To +50 °C , VDD = +5V±5%, VSS = 0V. 

Refer to Fig. 2, the bus timing diagram for write mode. 

Table 6 

|Parameter<br>~~a~~|Symbol|Min.|Max.|Unit|Remarks|
|---|---|---|---|---|---|
|Enable cycle time<br>~~a~~|tCYCE|500|-|ns||
|Enable ”High” levelpulse width<br>~~GQ~~|tWHE<br>~~GQ~~|300<br>~~GQ~~|-<br>~~GQ~~|ns<br>~~GQ~~|~~GQ~~|
|Enable rise time<br>~~a~~|tRE|-|25|ns||
|Enable fall time<br>~~GQ~~|tFE<br>~~GQ~~|-<br>~~GQ~~<br>~~ee~~|25<br>~~GQ~~<br>~~ee ee~~|ns<br>~~GQ~~<br>~~ee~~|~~GQ~~<br>~~ee~~|
|RS, R/W set-up time<br>~~ee~~<br>~~a~~<br>~~a~~|tAS<br>~~ee~~|60<br>~~ee~~<br>~~ee~~<br>~~a~~|-<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|8-bit operation mode<br>~~ee~~<br>~~ee~~|
|||100<br>~~ee~~<br>~~ee~~<br>~~a~~|~~ee~~<br>~~ee ee~~<br>~~ee~~<br>~~Q~~|~~ee~~<br>~~ee~~<br>~~ee~~<br>~~Q~~|4-bit operation mode<br>~~ee~~<br>~~ee~~|
|RS,R/W address hold time<br>~~a~~<br>~~a~~|tAH|10<br>~~ee~~<br>~~a~~|-<br>~~ee ee~~<br>~~ee ~~<br>~~Q~~|ns<br>~~ee~~<br> ~~ee~~<br>~~Q~~|~~ee~~|
|Data output delay<br>~~a~~|tDS|100|-<br>~~Q~~|ns<br>~~Q~~||
|Data hold time<br>~~GQ~~|tDHR<br>~~GQ~~|10<br>~~GQ~~|-<br>~~GQ~~|ns<br>~~GQ~~|~~GQ~~|



Refer to Fig. 3, the bus timing diagram for read mode . 

## Table 7 

|Parameter<br>~~a~~|Symbol|Min.|Max.|Unit|Remarks|
|---|---|---|---|---|---|
|Enable cycle time<br>~~GQ~~<br>~~a~~|tCYCE<br>~~GQ~~|500<br>~~GQ~~|-<br>~~GQ~~<br>~~Q~~|ns<br>~~GQ~~<br>~~Q~~|~~GQ~~|
|Enable ”High” levelpulse width<br>~~a~~|tWHE|300|-<br>~~Q~~|ns<br>~~Q~~||
|Enable rise time<br>~~a~~<br>~~a~~|tRE|-|25<br>~~Q~~|ns<br>~~Q~~||
|Enable fall time<br>~~GQ~~|tFE<br>~~GQ~~|-<br>~~GQ~~<br>~~ee~~|25<br>~~GQ~~<br>~~ee ee~~|ns<br>~~GQ~~<br>~~ee~~|~~GQ~~<br>~~ee~~|
|RS, R/W set-up time<br>~~ee~~<br>~~a~~|tAS<br>~~ee~~|60<br>~~ee~~<br>~~ee~~<br>~~a~~|-<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|8-bit operation mode<br>~~ee~~<br>~~ee~~|
|||100<br>~~ee~~<br>~~ee~~<br>~~a~~|~~ee~~<br>~~ee ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|4-bit operation mode<br>~~ee~~<br>~~ee~~|
|RS,R/W address hold time<br>~~a~~|tAH|10<br>~~ee~~<br>~~a~~|-<br>~~ee ee~~<br>~~ee ~~|ns<br>~~ee~~<br> ~~ee~~|~~ee~~|
|Read data output delay<br>~~GQ~~|tRD<br>~~GQ~~|-<br>~~GQ~~|190<br>~~GQ~~|ns<br>~~GQ~~|~~GQ~~|
|Read data hold time<br>~~ee~~|tDHR<br>~~ee~~|20<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|~~ee~~|



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## _**BATRON**_ 

Figure 2: Bus write operation sequence (Writing data from MPU to NT3881). 

Figure 3: Bus read operation sequence (Reading out data from NT3881 to MPU). 

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## **4.4  Timing Diagram of VDD against V0.** 

Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against V0. 

**==> picture [474 x 267] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>95%<br>LOGIC SUPPLY<br>VOLTAGE<br>0V V0<br>50ms(typical)<br>OV<br>LCD SUPPLY<br>VOLTAGE<br>**----- End of picture text -----**<br>


Figure 4: Timing diagram of VDD against V0. 

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**4.5  Correspondence between Character Codes and Character Patterns (NOVATEK Standard NT3881D-01)**