# Triac, 600 V, 8 A, TO-220AB, 1.7 V, 90 A, 35 mA ![Product image](https://novapart.co/image/farnell:1961701/) **URL**: https://novapart.co/products/BTA08-800CW3LFG/triac-600-v-8-a-to-220ab-17-90-35-ma **SKU**: BTA08-800CW3LFG **Manufacturer**: LITTELFUSE **Price**: €1.3700 **Stock**: 10+ **Lead Time**: 85 days (indicative) ## Description Peak Repetitive Off-State Voltage, Vdrm:600V; On State RMS Current IT(rms):8A; Triac Case Style:TO-220AB; Gate Trigger Current Max (QI), Igt:35mA; Gate Trigger Voltage Max Vgt:1.7V; Peak ## Specifications | Parameter | Value | |---|---| | Svhc | No SVHC (15-Jan-2018) | | No. Of Pins | 4Pins | | Product Range | - | | Triac Case Style | TO-220AB | | Thyristor Mounting | Through Hole | | Holding Current Max | 35mA | | On State Rms Current | 8A | | Peak On State Voltage | 1.55V | | Gate Trigger Voltage Max | 1.7V | | Operating Temperature Max | 125°C | | Peak Non Repetitive Surge Current | 90A | | Peak Repetitive Off State Voltage | 600V | ## Datasheet 📄 [Download PDF](https://novapart.co/datasheet/farnell:1961701/) ## BTA08-800CW3G ## Triacs ## **Silicon Bidirectional Thyristors** Designed for high performance full-wave ac control applications where high noise immunity and high commutating di/dt are required. ## **http://onsemi.com** ## **Features** - Blocking Voltage to 800 V - On-State Current Rating of 8 A RMS at 25°C - Uniform Gate Trigger Currents in Three Quadrants # **TRIACS 8 AMPERES RMS 800 VOLTS** - High Immunity to dV/dt − 1500 V/ | s minimum at 125°C - Minimizes Snubber Networks for Protection **==> picture [170 x 195] intentionally omitted <==** **----- Start of picture text -----**
MT2 MT1
~ G
4 MARKING
DIAGRAM
Kel
BTA08−xCWG
TO−220AB AYWW
1 CASE 221A
4 2 3 STYLE 12
x = 6 or 8
A = Assembly Location Wh
Y = Year
WW = Work Week
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- Industry Standard TO-220AB Package - High Commutating dI/dt − 1.5 A/ms minimum at 125°C - Internally Isolated (2500 VRMS) - These are Pb−Free Devices **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) **Rating Symbol Value Unit** ~~es es Kel~~ Peak Repetitive Off−State Voltage (Note 1) VDRM, V BTA08−xCWG (TJ = −40 to 125 ° C, Sine Wave, VRRM **TO−220AB** AYWW 50 to 60 Hz, Gate Open) 1 **CASE 221A** ~~CT~~ BTA08−800CW3G 800 4 2 3 **STYLE 12** On-State RMS Current(Full Cycle Sine Wave, 60 Hz, TC = 80 ° C) IT(RMS) 8.0 A x = 6 or 8 ~~ee~~ A = Assembly Location Wh Peak Non-Repetitive Surge Current ITSM 90 A Y = Year (One Full Cycle Sine Wave, 60 Hz, TC = 25 ° C) WW = Work Week G = Pb−Free Package ~~pT~~ Circuit Fusing Consideration (t = 8.3 ms) I[2] t 36 A[2] sec Non−Repetitive Surge Peak Off−State VDSM/ VDSM/VRSM V ~~ee~~ Voltage (TJ = 25 ° C, t = 10ms) VRSM ~~ee~~ +100 **PIN ASSIGNMENT** Peak Gate Current (TJ = 125 ° C, t = 20ms) IGM 4.0 A 1 Main Terminal 1 Peak Gate Power(Pulse Width ≤ 1.0 s, TC = 80 ° C) PGM 20 W 2 Main Terminal 2 Average Gate Power (TJ = 125 ° C) PG(AV) 1.0 W 3 Gate ° 4 No Connection ~~=~~ Operating Junction Temperature Range TJ −40 to +125 C ~~=~~ Storage Temperature Range Tstg −40 to +150 ° C RMS Isolation Voltage(t = 300 ms, R.H. ≤ 30%, TA = 25 ° C) Viso 2500 V **ORDERING INFORMATION** Stresses exceeding Maximum Ratings may damage the device. Maximum **Device Package Shipping** Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the BTA08−800CW3G TO−220AB 50 Units / Rail (Pb−Free) Recommended Operating Conditions may affect device reliability. ~~es ee TEE~~ 1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking voltages shall not be tested with a constant current source such that the voltage ratings of the devices are exceeded. - *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Publication Order Number: **BTA08−800CW3/D** **1** © Semiconductor Components Industries, LLC, 2012 **January, 2012 − Rev. 0** **BTA08−800CW3G** ## **THERMAL CHARACTERISTICS** |**THERMAL CHARACTERISTICS**|||||| |---|---|---|---|---|---| |**Characteristic**|**Symbol**|**Value**|||**Unit**| |Thermal Resistance,
Junction−to−Case (AC)
Junction−to−Ambient|R�JC
R�JA|2.5
60|||°C/W| |Maximum Lead Temperature for Soldering Purposes 1/8″from Case for 10 seconds|TL|260|||°C| |**ELECTRICAL CHARACTERISTICS**(TJ= 25°C unless otherwise noted; Electricals apply in both directions)|||||| |**Characteristic**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**| |**OFF CHARACTERISTICS**|||||| |Peak Repetitive Blocking Current
(VD= Rated VDRM, VRRM; Gate Open)
TJ= 25°C
TJ= 125°C|IDRM,
IRRM|−
−|−
−|0.005
2.0|mA| |**ON CHARACTERISTICS**|||||| |Peak On-State Voltage (Note 2)
(ITM=±11 A Peak)|VTM|−|−|1.55|V| |Gate Trigger Current (Continuous dc) (VD= 12 V, RL= 30�)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)|IGT|2.5
2.5
2.5|−
−
−|35
35
35|mA| |Holding Current
(VD= 12 V, Gate Open, Initiating Current =±100 mA)|IH|−|−|35|mA| |Latching Current (VD= 24 V, IG= 42 mA)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)|IL|−
−
−|−
−
−|50
60
50|mA| |Gate Trigger Voltage (VD= 12 V, RL= 30�)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)|VGT|0.5
0.5
0.5|−
−
−|1.7
1.1
1.1|V| |Gate Non−Trigger Voltage (TJ= 125°C)
MT2(+), G(+)
MT2(+), G(−)
MT2(−), G(−)|VGD|0.2
0.2
0.2|−
−
−|−
−
−|V| |**DYNAMIC CHARACTERISTICS**|||||| |Rate of Change of Commutating Current, See Figure 10.
(Gate Open, TJ= 125°C, No Snubber)|(dI/dt)c|1.5|−|−|A/ms| |Critical Rate of Rise of On−State Current
(TJ= 125°C, f = 120 Hz, IG= 2 x IGT, tr≤100 ns)|dI/dt|−|−|50|A/�s| |Critical Rate of Rise of Off-State Voltage
(VD= 0.66 x VDRM, Exponential Waveform, Gate Open, TJ= 125°C)|dV/dt|1500|−|−|V/�s| 2. Indicates Pulse Test: Pulse Width ≤ 2.0 ms, Duty Cycle ≤ 2%. **http://onsemi.com** **2** **BTA08−800CW3G** ## **Voltage Current Characteristic of Triacs (Bidirectional Device)** |**Symbol**|**Parameter**| |---|---| |VDRM|Peak Repetitive Forward Off State Voltage| |IDRM|Peak Forward Blocking Current| |VRRM|Peak Repetitive Reverse Off State Voltage| |IRRM|Peak Reverse Blocking Current| |VTM|
Maximum On State Voltage| |IH|Holding Current| **==> picture [248 x 153] intentionally omitted <==** **----- Start of picture text -----**
+ Current
Quadrant 1
MainTerminal 2 +
VTM
on state
IH
IRRM at VRRM
off state + Voltage
IH IDRM at VDRM
Quadrant 3
VTM
MainTerminal 2 −
**----- End of picture text -----**
## **Quadrant Definitions for a Triac** **==> picture [349 x 339] intentionally omitted <==** **----- Start of picture text -----**
MT2 POSITIVE
(Positive Half Cycle)
+
(+) MT2 (+) MT2
Quadrant II (−) IGT (+) IGT Quadrant I
GATE GATE
MT1 MT1
REF REF
IGT − + IGT
(−) MT2 (−) MT2
Quadrant III (−) IGT (+) IGT Quadrant IV
GATE GATE
MT1 MT1
REF REF
−
MT2 NEGATIVE
(Negative Half Cycle)
**----- End of picture text -----**
All polarities are referenced to MT1. With in−phase signals (using standard AC lines) quadrants I and III are used. **http://onsemi.com** **3** **BTA08−800CW3G** **==> picture [490 x 661] intentionally omitted <==** **----- Start of picture text -----**
125 12
DC
10
120 180 °
� = 120, 90, 60, 30 °
8 120 °
115
� = 180 ° 6
110
4 60 °
DC 90 °
105 � = 30 °
2
100 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
IT(RMS), RMS ON-STATE CURRENT (A) IT(RMS), ON-STATE CURRENT (A)
Figure 1. RMS Current Derating Figure 2. On-State Power Dissipation
100 1
0.1
10
0.01
0.1 1 10 100 1000 1·10 [4]
t, TIME (ms)
Figure 4. Thermal Response
55
1
45
35
MT2 POSITIVE
25
15
MT2 NEGATIVE
0.1 5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 −40 −25 −10 5 20 35 50 65 80 95 110 125
VT, INSTANTANEOUS ON-STATE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( ° C)
C)
° , AVERAGE POWER (W)
, CASE TEMPERATURE ( AV
C P
T
(NORMALIZED)
r(t), TRANSIENT THERMAL RESISTANCE
, INSTANTANEOUS ON−STATE CURRENT (A)
IT
, HOLDING CURRENT (mA)
IH
**----- End of picture text -----**
**Figure 3. On-State Characteristics** **Figure 5. Hold Current Variation** **http://onsemi.com** **4** **BTA08−800CW3G** **==> picture [510 x 425] intentionally omitted <==** **----- Start of picture text -----**
100 2.00
VD = 12 V VD = 12 V
1.80
RL = 30 � RL = 30 �
1.60
Q1
1.40
Q1
10 Q2 1.20
1.00
Q3 Q3
0.80
0.60 Q2
1 0.40
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Gate Trigger Current Variation Figure 7. Gate Trigger Voltage Variation
5000 120
VD = 800 Vpk VD = 800 Vpk
4K TJ = 125°C 100 TJ = 125°C
80
3K Q1
60
2K Q2
40
1K 20 Q3
0 0
10 100 1000 10000 −40 −25 −10 5 20 35 50 65 80 95 110 125
RG, GATE TO MAIN TERMINAL 1 RESISTANCE (OHMS) TJ, TEMPERATURE ( ° C)
Figure 8. Critical Rate of Rise of Off-State Voltage Figure 10. Latching Current Variation
(Exponential Waveform)
, GATE TRIGGER CURRENT (mA) GATE TRIGGER VOLTAGE (V)
IGT
s)
μ
LATCHING CURRENT (mA)
dv/dt , CRITICAL RATE OF RISE OF OFF‐STATE VOLTAGE (V/
**----- End of picture text -----**
**==> picture [402 x 172] intentionally omitted <==** **----- Start of picture text -----**
LL 1N4007
200 VRMS
ADJUST FOR MEASURE
ITM, 60 Hz VAC I
CHARGE
TRIGGER -
CONTROL
CHARGE 200 V
+
MT2
1N914 51 �
NON‐POLAR MT1
G
CL
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
TRIGGER CONTROL
**----- End of picture text -----**
**Figure 9. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c** **http://onsemi.com** **5** **BTA08−800CW3G** ## **PACKAGE DIMENSIONS** **TO−220** CASE 221A−07 ISSUE O NOTES: **−T− SEATINGPLANE** 1. Y14.5M, 1982.DIMENSIONING AND TOLERANCING PER ANSIDIMENSIONING AND TOLERANCING PER ANSI 2. CONTROLLING DIMENSION: INCH. **B F T C S** 3. BODY AND LEAD IRREGULARITIES AREALLOWED.DIMENSION Z DEFINES A ZONE WHERE ALLALLOWED.DIMENSION Z DEFINES A ZONE WHERE ALLDIMENSION Z DEFINES A ZONE WHERE ALL **INCHES MILLIMETERS DIM MIN MAX MIN MAX 4 Q A AB** 0.5700.380 0.6200.405 14.489.66 15.7510.28 **C** 0.160 0.190 4.07 4.82 **1 2 3 U D** 0.025 0.035 0.64 0.88 **H F** 0.142 0.147 3.61 3.73 **G** 0.095 0.105 2.42 2.66 **K H** 0.110 0.155 2.80 3.93 **Z J** 0.014 0.022 0.36 0.55 **K** 0.500 0.562 12.70 14.27 ~~fs A ==~~ **L** 0.045 0.060 1.15 1.52 **L R QN** 0.1900.100 0.2100.120 4.832.54 5.333.04 **V J RS** 0.0800.045 0.0550.110 2.041.15 2.791.39 **G T** 0.235 0.255 5.97 6.47 **U** 0.000 0.050 0.00 1.27 **D V** 0.045 --1.15 --- ~~rl~~ **N Z** --0.080 --2.04 STYLE 12: PIN 1. MAIN TERMINAL 1 2. MAIN TERMINAL 2 3. GATE 4. NOT CONNECTED 1. Y14.5M, 1982.DIMENSIONING AND TOLERANCING PER ANSIDIMENSIONING AND TOLERANCING PER ANSI 2. CONTROLLING DIMENSION: INCH. 3. BODY AND LEAD IRREGULARITIES AREALLOWED.DIMENSION Z DEFINES A ZONE WHERE ALLALLOWED.DIMENSION Z DEFINES A ZONE WHERE ALLDIMENSION Z DEFINES A ZONE WHERE ALL **ON Semiconductor** and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. ## **PUBLICATION ORDERING INFORMATION** **N. American Technical Support** : 800−282−9855 Toll Free USA/Canada ## **LITERATURE FULFILLMENT** : Literature Distribution Center for ON Semiconductor USA/Canada P.O. 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