# Bluetooth Module, BLE 5.0, 3 Mbps, -94 dBm, 3 V to 3.6 V, -30 °C 85 °C

![Product image](https://novapart.co/image/farnell:4216110RL/)

**URL**: https://novapart.co/products/BT851/bluetooth-module-ble-50-3-mbps-94-dbm-v-to-36-30-c
**SKU**: BT851
**Manufacturer**: EZURIO
**Category**: Wireless Modules & Adaptors || Communications & Networking Modules || Bluetooth Modules & Adaptors
**Price**: €13.7600
**Stock**: 200+
**Lead Time**: 232 days (indicative)

## Specifications

| Parameter | Value |
|---|---|
| Svhc | To Be Advised |
| Interfaces | I2S, USB |
| Product Range | BT85x Series |
| Certifications | EU, FCC, ISED, KC, MIC, RCM |
| Bluetooth Class | Class 1 |
| Bluetooth Version | Bluetooth LE 5.0 |
| Supply Voltage Range | 3 V to 3.6 V |
| Receiver Sensitivity Rx | -94 dBm |
| Operating Temperature Range | -30 °C to 85 °C |

## Datasheet

📄 [Download PDF](https://novapart.co/datasheet/farnell:4216110RL/)

A 

_Version 2.1_ 

|**Version**||**Date**|**Notes**||||**Contributor**|**Approver**|
|---|---|---|---|---|---|---|---|---|
|1.0|12 Jan 2018|12 Jan 2018|Initial Release||||Jacky Kuo<br>Raj Khatri|Jonathan Kaye|
|1.1|05 Feb 2018|05 Feb 2018|Updated moisture sensitivity level from 4<br>to 3||Updated moisture sensitivity level from 4||Connie Lin|Jonathan Kaye|
|1.2|11 Apr 2018|11 Apr 2018|Removed<br>reference; updated template|_inbuilt Bluetooth stack_<br>reference; updated template|||Raymond Au|Jonathan Kaye|
|1.3|05 Dec 2018|05 Dec 2018|Added BT851 mechanical drawing;<br>updated dongle measurements||||Maggie Teng|Jonathan Kaye|
||||Updated logos and URLs;||||||
|1.4|18 Feb 2019|18 Feb 2019|Updated BT SIG section;||||Sue White|Jonathan Kaye|
||||Add KC regulatory information||||||
|1.5|26 Sept 2019|26 Sept 2019|Added_Section 8.5 Reset and POR_<br>_(Power on Reset)_||||Andrew Chen|Jonathan Kaye|
|1.6|02 Oct 2019|02 Oct 2019|Fixed tolerance error – changed ±1.3 to<br>±0.15 in the Mechanical Drawing section||||Maggie Teng|Jonathan Kaye|
|1.7|03 Sept 2020|03 Sept 2020|Updated the EU regulatory section<br>including updated standards||||Ryan Urness|Jonathan Kaye|
|1.8|13 Oct 2020|13 Oct 2020|Removed references to the EN 301 893<br>EU standard||||Miles Chung|Jonathan Kaye|
|1.9|30 Oct 2020|30 Oct 2020|Updated all regulatory information||||Ryan Urness|Jonathan Kaye|
|2.0|02 Feb 2021|02 Feb 2021|Transferred all regulatory information to<br>a separate document||||Sue White|Jonathan Kaye|
|2.1|05 Feb 2021|05 Feb 2021|Updated mechanical dimension||||Jacky Kuo|Jonathan Kaye|



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2 © Copyright 2021 Laird Connectivity, Inc.. All Rights Reserved 

|1|Scope .................................................................................................................................................................................. 4|
|---|---|
|2|Operational Description ....................................................................................................................................................... 4|
|3|Block Diagram and Descriptions .......................................................................................................................................... 5|
|4|Specifications ...................................................................................................................................................................... 6|
|5|Pin Definitions ...................................................................................................................................................................... 7|
|6|DC Electrical Characteristics ............................................................................................................................................... 8|
|7|RF Characteristics ............................................................................................................................................................... 9|
|8|Interface ............................................................................................................................................................................ 10|
||Global Coexistence Interface ................................................................................................................................... 10<br>8.1|
||USB Interface ........................................................................................................................................................... 10<br>8.2|
||PCM Interface .......................................................................................................................................................... 10<br>8.3|
||I2S Interface.............................................................................................................................................................. 16<br>8.4|
||Reset and POR (Power on Reset) ........................................................................................................................... 18<br>8.5|
|9|Antenna Performance ........................................................................................................................................................ 19|
|10|Mechanical Dimensions and Land Pattern ........................................................................................................................ 21|
|11|Implementation Note ......................................................................................................................................................... 23|
||PCB Layout on Host PCB ........................................................................................................................................ 23<br>11.1|
||11.1.1<br>Antenna Keep-out and Proximity to Metal or Plastic .......................................................................................... 23|
||11.1.2<br>USB Dongle Design Example Using BT850-SA ................................................................................................. 24|
|12|Application Note for Surface Mount Modules..................................................................................................................... 25|
||Introduction .............................................................................................................................................................. 25<br>12.1|
||Shipping ................................................................................................................................................................... 25<br>12.2|
||12.2.1<br>Tape and Reel Package Information .................................................................................................................. 25|
||12.2.2<br>Packaging Process ............................................................................................................................................. 26|
||Reflow Parameters ................................................................................................................................................... 27<br>12.3|
|13|Regulatory ......................................................................................................................................................................... 28|
|14|Ordering Information .......................................................................................................................................................... 28|
|15|Bluetooth SIG Approvals ................................................................................................................................................... 29|
||Application Note: Subsystem Combinations ............................................................................................................. 29<br>15.1|
||15.1.1<br>Laird Customer Declaration ID Procedure .......................................................................................................... 29|
|16|Additional Assistance ........................................................................................................................................................ 30|



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3 © Copyright 2021 Laird Connectivity, Inc.. All Rights Reserved 

This document describes key hardware aspects of the Laird BT85x Bluetooth HCI module and Adapter. This document is mainly intended to assist device manufacturers and related parties with the integration of this module into their host devices. Data in this document are drawn from several sources including data sheets for the Cypress CYW20704A2. 

Because the BT850-Sx is currently in development stage, this document is preliminary and the information in this document is subject to change. Please contact Laird Connectivity or visit the product page on the Laird website to obtain the most recent version of this document. 

**==> picture [376 x 19] intentionally omitted <==**

**----- Start of picture text -----**<br>
BT851<br>BT850-SA  BT850-ST<br>**----- End of picture text -----**<br>


The BT85x series of USB HCI modules and Adapter leverage the Cypress CYW20704 A2 chipset to provide exceptionally low power consumption with outstanding range for OEMs needing both Classic Bluetooth and Bluetooth Low Energy support. The Bluetooth v5.0 core specification shortens your development time and provides enhanced throughput, security and privacy. 

The BT850 modules are ideal when designers need both performance and minimum size. For maximum flexibility in integration, they support a host USB interface, I[2] S and PCM audio interfaces, GPIO, and Cypress’GCI coexistence (2-wire). The modules provide excellent RF performance and identical footprint options for integrated antenna or an external antenna via a trace pin. 

These modules present a Bluetooth standard HCI interface with native support for Windows, Linux and Android Bluetooth software stacks for operating system backed devices. The BT851 Pluggable USB Adapter simply plugs into any Windows, Android, or Linux device via external USB connection. 

Additionally, Laird has partnered with Searan for support of their ultra small, flexible ‘dotstack’ platform for embedded Cortex M3 and M4 implementations. 

- Bluetooth v5.0 - Dual Mode (Classic Bluetooth and BLE) 

- Compact footprint 

- 2-wire Cypress Global Coexistence Interface (GCI) 

- High antenna radiation gain and efficiency 

- Good interference rejection for multi-com system (GSM/WCDMA) 

- Class 1 output – 8 dBm 

- USB, I[2] S, and PCM 

   - Medical devices 

   - ePOS terminals 

   - Barcode scanners 

   - Industrial cable replacement 

   - IoT Platforms Automotive Diagnostic Equipment 

   - Personal Digital Assistants (PDA) 

- Industrial temperature range 

- 512 k EEPROM support 

- Bluetooth Controller subsystem 

- FCC, ISED, EU, RCM, KC, and Giteki approvals 

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_**Figure 1: BT850 module block diagram**_ 

|**_Table 1: Block diagram descriptions_**|**_Table 1: Block diagram descriptions_**|
|---|---|
|**CYW20704A2**|The BT85x is based on CYW20704A2 dual mode chip. The chip is a single-chip radio with on-chip LDO|
|**(Main chip)**|regulators and baseband IC for Bluetooth 2.4 GHz systems including EDR to 3 Mbps.|
||Dedicated signal and baseband processing is included for full Bluetooth operation. The chip provides|
||I2S/PCM and USB interfaces. There are two general purpose I/Os be configured for proprietary of|
||Cypress GCI used and a general purpose I/O can be configured for scan/inquire/paging/data traffic of|
||indicator. These three I/O pins are controlled by firmware.|
|**Antenna**|BT850-SA and BT851 – The antenna is a ceramic monopole chip antenna.|
||BT850-ST – Trace Pad provision for use with a range of certified External Antennas|
|**Band Pass**|The band pass filter filters the out-of-band emissions from the transmitter to meet the specific regulations|
|**Filter**|for type approvals of various countries.|
|**EEPROM**|There are 512 k bits EEPROM embedded on the BT85x which can be used to store parameters, such as|
||BD_ADDR, USB enumeration information, maximum TX power, PCM configuration, USB product ID,|
||USB vendor ID, and USB product description.|
|**Crystal**|The embedded 40 MHz crystal is used for generating the clock for the entire module.|



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_**Table 2: BT850 specifications**_ 

|**Categories**|**Feature**|**Implementation**|
|---|---|---|
||Bluetooth®|V5.0 Dual Mode – BR / EDR / LE|
||Frequency|2.402 - 2.480 GHz|
|||Class 1|
|**Wireless**|Maximum Transmit Power|+8 dBm from antenna|
|**Specification**|||
||Receive Sensitivity|-94 dBm|
||Range|Circa 100 meters|
||Data Rates|Up to 3 Mbps (over-the-air)|
|**Host Interface**|USB|Full speed USB 2.0|
||GPIO|3.3V for all general purpose I/Os|
|**Operational Mode**|HCI|Host Controller Interface over USB|
|**EEPROM**|2-wire|512 K bits|
|**Coexistence**|802.11 (Wi-Fi)|2-Wire Cypress Global Coexistence Interface (GCI)|
|**Supply Voltage**|Supply|3.0V - 3.6V|
|**Power Consumption**|Current|Idle Mode ~8 mA<br>File Transfer ~43 mA|
|**Antenna Options**|Internal<br>External|Multilayer ceramic antenna<br>Trace Pad|
|||8.5 x 12.85 x 2.2 mm (BT850-SA)|
|**Physical**<br>(Width x Length x Height)|Dimensions|8.5 x 12.85 x 1.9 mm (BT850-ST)<br>16 x 43 x 11 (BT851 – USB dongle)|
|||17.4 (± 0.2) x 46.75 (± 0.4) x 12 (± 0.15) mm (BT851 – USB Dongle)|
|**Environmental**|Operating|-30° C to +85° C|
||Storage|-40° C to +85° C|
|**Miscellaneous**|Lead Free|Lead-free and RoHS-compliant|
||Warranty|One-year warranty|
|**Approvals**|Bluetooth®<br>FCC/ISED/EU/RCM/Giteki/KC|Controller Subsystem Approved<br>All BT85x series|



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_**Table 3: BT850 pin definitions**_ 

|**Pin**<br>**No.**||**Pin Name**|||**I/O**|**Supply**<br>**Domain**||**Description**|**If Unused**|
|---|---|---|---|---|---|---|---|---|---|
|1||NC|||||||NC|
|2||NC||||||||
|3||GND|||GND|||Ground|GND|
|4||USB_D+|||Bidirectional|3V3||USB data plus|N/A|
|5||USB_D-|||Bidirectional|3V3||USB data negative|N/A|
|6||GND|||GND|||Ground|GND|
|7||NC|||||||NC|
|8||RESET|||Input|3v3||Active-low reset input|N/A|
|9||3v3|||Input|3v3||Module main DC power supply,<br>Input to internal 1.2V and 2.5V LDO|N/A|
|10||NC|||||||NC|
|11||GND|||GND|||Ground|GND|
|12||GND|||GND|||Ground|GND|
|13||GND|||GND|||Ground|GND|
|14||GND|||GND|||Ground|GND|
|15||GND|||GND|||Ground|GND|
|16||GND|||GND|||Ground|GND|
|17||RF||||||BT850-ST RF signal output (50Ω)||
|||||||||BT850-SA No connection||
|18||GND|||GND|||Ground|GND|
|19|I2S_WS/PCM_SYNC||I2S_WS/PCM_SYNC||Bidirectional|3V3||PCM sync/I2S word select|NC|
|20|I2S_CLK/PCM_CLK||||Bidirectional|3V3||PCM/I2S clock|NC|
|21|I2S_DI/PCM_IN||||Bidirectional|3V3||PCM/I2S data input|NC|
|22|I2S_OUT/PCM_OUT||I2S_OUT/PCM_OUT||Bidirectional|3V3||PCM/I2S data output|NC|
|23||NC|||||||NC|
|24||GND|||GND|||Ground|GND|
|25|BT_SECI_IN||||Input|3V3||Coexistence data input|NC|
|26|BT_SECI_OUT||||Output|3V3||Coexistence data output|NC|
|27||NC|||||||NC|
|28||GPIO_5|||Bidirectional|3V3||Programmable input/output line|NC|
|**Pin Definition**<br>**Note 1:**||**Pin Definition**<br>The GPIO_5 is controlled by the default firmware for the status of BT850 indications.|The GPIO_5 is controlled by the default firmware for the status of BT850 indications.||The GPIO_5 is controlled by the default firmware for the status of BT850 indications.|||The GPIO_5 is controlled by the default firmware for the status of BT850 indications.||



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_**Table 4: Absolute Maximum Rating**_ 

|**_Table 4: Absolute Maximum Rating_**||||
|---|---|---|---|
|**Rating**|**Min**|**Max**|**Unit**|
|Storage temperature|-40|+150|⁰C|
|Operating Temperature|-30|+85|⁰C|
|ESD Contact Discharge|-4|+4|KV|
|ESD Air Discharge|-8|+8|KV|
|Moisture Sensitivity Level|3|-|-|
|3V3 Input|3.0|3.6|V|



## _**Table 5: Recommended operating conditions**_ 

|**_Table 5: Recommended operating conditions_**||||
|---|---|---|---|
|**Rating**|**Min**|**Max**|**Unit**|
|Storage temperature|-40|+150|⁰C|
|Operating Temperature|-30|+85|⁰C|
|3V3 Input|3.0|3.6|V|



## _**Table 6: Digital I/O characteristics**_ 

|**_Table 6: Digital I/O characteristics_**|||||
|---|---|---|---|---|
|**Normal Operation**|**Min**|**Typ.**|**Max**|**Unit**|
|VILInput Low Voltage (VDDO* = 3V3)|-|-|0.8|V|
|VIHInput High Voltage (VDDO* =  3V3)|2.0|-|-|V|
|VOLOutput Low Voltage|-|-|0.4|V|
|VOHOutput High Voltage|3V3-0.4|-|-|V|
|IILInput Low Current|-|-|1.0|µA|
|IIHInput High Current|-|-|1.0|µA|
|IOLOutput Low Current|-|-|2.0|mA|
|(VDDO* = 3V3, VOL= 0.4V)|||||
|IOHOutput Low Current|-|-|2.0|mA|
|(VDDO* = 3V3, VOH= 2.9V)|||||
|CINInput Capacitance|-|-|0.4|pF|



*: The VDDO is denoted the digital I/O voltage and it’s depended on the Pin9 (3V3) input of module. 

## _**Table 7: Current consumption**_ 

|**_Table 7: Current consumption_**|||
|---|---|---|
|**Normal Operation**|**Peak (8 dBm)**|**Unit**|
|Idle|8|mA|
|Inquiry|23|mA|
|File Transfer|43|mA|
|BLE Connected (Master)|26|mA|
|BLE Scan (Master)|26|mA|
|BLE File Transfer|27|mA|



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8 

© Copyright 2021 Laird Connectivity, Inc.. All Rights Reserved 

_**Table 8: BDR/EDR/LE transmitter characteristics (Input = 3V3 @ 25**_ ℃ _**)**_ 

|**Parameter**||**Min**|**Typ.**|**Max**|**BT. Spec.**|**Unit**|
|---|---|---|---|---|---|---|
|Classic BT (BDR) - GFSK Maximum RF Transmit Power||6|8|10|20|dBm|
|Classic BT - EDR Maximum RF Transmit Power||2|4|6|20|dBm|
|BLE Maximum RF Transmit Power||6|8|10|20|dBm|
|RF power variation over temperature range||-|2.0|-|-|dB|
|RF power variation over BT band||-|2|-|-|dB|
|RF power control step||2|4|8|-|dB|
|Initial Carrier Frequency Tolerance||-|10|-|±75|kHz|
|BLE Frequency Accuracy|||10||±150|kHz|
|20 dB Bandwidth||-|920|-|1000|kHz|
||1.0 MHz < |M-N| < 1.5 MHz|-|-|-39|-26|dBc|
|In-Band Spurious<br>Emissions|1.5 MHz < |M-N| < 2.5 MHz|-|-|-39|-20|dBm|
|||M-N|≧2.5 MHz|-|-|-47|-40|dBm|
||fTX ±2 MHz|-|-|-48|-20|dBm|
|BLE In-Band Emission|||||||
||fTX ±[3 + n] MHz|-|-|-47|-30|dBm|
|Drift rate||-|10|-|+/-25|kHz|
|ΔF1Avg||-|152|-|140<>175|kHz|
|ΔF2Max||100|-|-|99.9|%|
|ΔF2Avg / ΔF1Avg||-|1.0|-|≧0.8||
|BLE ΔF1Avg||-|245|-|225<>275|kHz|
|BLE ΔF2Max||100|-|-|99.9|%|
|BLE ΔF2Avg/ ΔF1Avg||-|1.0|-|≧0.8||



_**Table 9: BDR/EDR/LE receiver sensitivity (Input = 3V3 @ 25**_ ℃ _**)**_ 

|**Parameter**|**Conditions**|**Min**|**Typ.**|**Max**|**BT. Spec.**|**Unit**|
|---|---|---|---|---|---|---|
||GFSK, 0.1% BER, 1 Mbps||-90||-70|dBm|
|Sensitivity|/4-DQPSK, 0.01% BER, 2 Mbps<br>8-DPSK, 0.01% BER, 3 Mbps||-94<br>-87||-70<br>-70|dBm<br>dBm|
||BLE GFSK, 30.8% PER, 1 Mbps||-94||-70|dBm|
|Sensitivity variation|All Modulations (Over BT band)||2|||dB|



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The BT850-Sx supports the proprietary Cypress Global Coexistence Interface (GCI) which is a two-wire interface. 

The following key features are associated with the interface: 

- Enhanced coexistence data can be exchanged over GCI_SECI_IN and GCI_SECI_OUT a two-wire interface, one serial input (GCI_SECI_IN), and one serial output (GCI_SECI_OUT). The both pins are controlled by the configuration file that is stored in EEPROM from the host. 

- It supports generic UART communication between WLAN and Bluetooth devices. 

- To conserve power, it is disabled when inactive. 

- It supports automatic resynchronization upon waking from sleep mode. 

- It supports a baud rate of up to 4 Mbps. 

Table 10 shows the two-wire BT coexistence interface assignments. 

## _**Table 10: BDR/EDR/LE receiver sensitivity (Input = 3V3 @ 25**_ ℃ _**)**_ 

|**Coexistence Signal Name**|**Signal Assignment**|
|---|---|
|BT_SECI_IN|GPIO_6|
|BT_SECI_OUT|GPIO_7|



BT85x has a full-speed (12 Mbps) USB interface for communicating with other compatible digital devices. The USB interface on the BT85x acts as a USB peripheral, responding to requests from a master host controller. 

BT85x supports the Universal Serial Bus Specification (USB v2.0 Specification) and USB Battery Charging Specification, available from http://www.usb.org. For more information on how to integrate the USB interface on BT85xd, see Figure 17 located in the following section: USB Dongle Design Example Using BT850. 

The following USB interface features are supported: 

- USB Protocol, revision 2.0, full-speed compliant with LPM support (up to 12 Mbps) 

- Bluetooth HCI 

- Integrated detach resistor 

- USB termination when interface is not in use 

- Internal modules, certification, and non-specification compliant operation 

The BT850-Sx supports two independent PCM interfaces that share the pins with I[2] S interfaces. The PCM interface on the BT850-Sx can connect to linear PCM Codec devices in master or slave mode. In master mode, the BT850-Sx generates the PCM_CLK and PCM_SYNC signals; in slave mode, these signals are provided by another master on the PCM interface and are inputs to the BT850-Sx. 

The configuration of the PCM interface may be adjusted by the host using vendor-specific HCI commands. 

For additional information, refer to the DVK-BT85x-Sx User Guide available from the BT85x product page of the Laird website. 

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The BT850-Sx supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. 

## 8.3.2 Frame Synchronization 

The BT850-Sx supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signals an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. 

Figure 2 and Table 11 shows PCM Timing Diagram and Specifications for the master mode of short-frame. 

_**Figure 2: PCM timing diagram (Short-Frame Sync, Master Mode)**_ 

_**Table 11: PCM Interface timing specifications (Short-Frame Sync, Master Mode)**_ 

|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|-|-|12|MHz|
|2|PCM bit clock LOW|41|-|-|ns|
|3|PCM bit clock HIGH|41|-|-|ns|
|4|PCM_SYNC setup|0|-|25|ns|
|5|PCM_OUT delay|0|-|25|ns|
|6|PCM_IN setup|8|-|-|ns|
|7|PCM_IN hold|8|-|-|ns|
|8|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance|0|-|25|ns|



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Figure 3 and Table 12 shows PCM Timing Diagram and Specifications for the slave mode of short-frame. 

_**Figure 3: PCM timing diagram (Short-Frame Sync, Slave Mode)**_ 

_**Table 12: PCM Interface timing specifications (Short-Frame Sync, Slave Mode)**_ 

|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|-|-|12|MHz|
|2|PCM bit clock LOW|41|-|-|ns|
|3|PCM bit clock HIGH|41|-|-|ns|
|4|PCM_SYNC setup|8|-|-|ns|
|5|PCM_SYNC_hold|8|-|-|ns|
|6|PCM_OUT delay|0|-|25|ns|
|7|PCM_IN setup|8|-|-|ns|
|8|PCM_IN hold|8|-|-|ns|
|9|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance|0|-|25|ns|



In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. 

Figure 4 and Table 13 shows PCM Timing Diagram and Specifications for the master mode of long-frame. 

_**Figure 4: PCM timing diagram (Long-Frame Sync, Master Mode)**_ 

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_**Table 13: PCM Interface timing specifications (Long-Frame Sync, Master Mode)**_ 

|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|-|-|12|MHz|
|2|PCM bit clock LOW|41|-|-|ns|
|3|PCM bit clock HIGH|41|-|-|ns|
|4|PCM_SYNC delay|0|-|25|ns|
|5|PCM_OUT delay|0|-|25|ns|
|6|PCM_IN setup|8|-|-|ns|
|7|PCM_IN hold|8|-|-|ns|
|8|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becominghigh impedance|0|-|25|ns|



Figure 5 and Table 14 shows PCM Timing Diagram and Specifications for the slave mode of long-frame. 

_**Figure 5: PCM timing diagram (Long-Frame Sync, Slave Mode)**_ 

_**Table 14: PCM Interface timing specifications (Long-Frame Sync, Slave Mode)**_ 

|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|-|-|12|MHz|
|2|PCM bit clock LOW|41|-|-|ns|
|3|PCM bit clock HIGH|41|-|-|ns|
|4|PCM_SYNC setup|8|-|-|ns|
|5|PCM_SYNC_hold|8|-|-|ns|
|6|PCM_OUT delay|0|-|25|ns|
|7|PCM_IN setup|8|-|-|ns|
|8|PCM_IN hold|8|-|-|ns|
|9|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becominghigh impedance|0|-|25|ns|



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## 8.3.5 Data Formatting 

The BT850-Sx may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the BT850-Sx uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. 

## 8.5.4 Wideband Speech Support 

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4-kHz sync rate with 16-bit samples, resulting in a 64 Kbps bit rate. The BT850-Sx also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 Kbps rate) is transferred over the PCM bus. 

## 8.3.5 Multiplexed Bluetooth Over PCM 

Bluetooth supports multiple audio streams within the Bluetooth channel and both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 6 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration. 

_**Figure 6: Functional multiples data diagram**_ 

## 8.3.6 Burst PCM Mode 

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. 

Figure 7 and Table 15 shows PCM Burst mode timing diagram and specifications for the receive-only mode of short-frame sync. 

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_**Figure 7: PCM burst mode timing (Receive Only, Short Frame Sync)**_ 

|**_Table 15: PCM burst mode specifications (Receive Only, Short-Frame Sync)_**|**_Table 15: PCM burst mode specifications (Receive Only, Short-Frame Sync)_**|**_Table 15: PCM burst mode specifications (Receive Only, Short-Frame Sync)_**|**_Table 15: PCM burst mode specifications (Receive Only, Short-Frame Sync)_**||||
|---|---|---|---|---|---|---|
|**Ref No.**|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|1||PCM bit clock frequency|-|-|24|MHz|
|2||PCM bit clock LOW|20.8|-|-|ns|
|3||PCM bit clock HIGH|20.8|-|-|ns|
|4||PCM_SYNC setup|8|-|-|ns|
|5||PCM_SYNC_hold|8|-|-|ns|
|6||PCM_IN setup|8|-|-|ns|
|7||PCM_IN hold|8|-|-|ns|



Figure 8 and Table 16 shows PCM Burst mode timing diagram and specifications for the receive-only mode of long-frame sync. 

_**Figure 8: PCM burst mode timing (Receive Only, Long Frame Sync)**_ 

_**Table 16: PCM burst mode specifications (Receive Only, Long-Frame Sync)**_ 

|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|PCM bit clock frequency|-|-|24|MHz|
|2|PCM bit clock LOW|20.8|-|-|ns|
|3|PCM bit clock HIGH|20.8|-|-|ns|



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|**Ref No.**<br>4<br>~~**e**e~~|**Ref No.**<br>4<br>~~**e**e~~|**Characteristics**<br>**Minimum**<br>**Typical**<br>**Maximum**<br>**Unit**<br>PCM_SYNC setup<br>8<br>-<br>-<br>ns<br>~~e~~<br>~~es es~~<br>~~es~~|**Characteristics**<br>**Minimum**<br>**Typical**<br>**Maximum**<br>**Unit**<br>PCM_SYNC setup<br>8<br>-<br>-<br>ns<br>~~e~~<br>~~es es~~<br>~~es~~|**Characteristics**<br>**Minimum**<br>**Typical**<br>**Maximum**<br>**Unit**<br>PCM_SYNC setup<br>8<br>-<br>-<br>ns<br>~~e~~<br>~~es es~~<br>~~es~~|**Characteristics**<br>**Minimum**<br>**Typical**<br>**Maximum**<br>**Unit**<br>PCM_SYNC setup<br>8<br>-<br>-<br>ns<br>~~e~~<br>~~es es~~<br>~~es~~|**Characteristics**<br>**Minimum**<br>**Typical**<br>**Maximum**<br>**Unit**<br>PCM_SYNC setup<br>8<br>-<br>-<br>ns<br>~~e~~<br>~~es es~~<br>~~es~~|
|---|---|---|---|---|---|---|
||5|PCM_SYNC_hold|8|-|-|ns|
||6|PCM_IN setup|8|-|-|ns|
||7|PCM_IN hold|8|-|-|ns|



The BT850-Sx supports two independent I[2] S digital audio ports. The I[2] S interface supports both master and slave modes. The I[2] S signals are: 

- I[2] S clock: I[2] S SCK 

- I[2] S Word Select: I[2] S WS 

- I[2] S Data Out: I[2] S SDO 

- I[2] S Data In: I[2] S SDI 

I[2] S SCK and I[2] S WS become outputs in master mode and inputs in slave mode, while I[2] S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I[2] S bus, per the I[2] S specification. The MSB of each data word is transmitted one bit clock cycle after the I[2] S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I[2] S WS is low, and right-channel data is transmitted when I[2] S WS is high. Data bits sent by the BT850 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. 

The clock rate in master mode is either of the following: 

- 48 kHz x 32 bits per frame = 1.536 MHz 

- 48 kHz x 50 bits per frame = 2.400 MHz 

The master clock is generated from the input reference clock using a N/M clock divider. 

In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. 

Timing values specified in Table 17 are relative to high and low threshold levels. 

|**_Table 17: Timing for I2S transmitters and receivers_**<br>~~ee a~~<br>~~ee~~|**_Table 17: Timing for I2S transmitters and receivers_**<br>**Transmitter**<br>~~a~~<br>|**_Table 17: Timing for I2S transmitters and receivers_**<br>**Transmitter**<br>~~a~~<br>|**_Table 17: Timing for I2S transmitters and receivers_**<br>**Transmitter**<br>~~a~~<br>|**_Table 17: Timing for I2S transmitters and receivers_**<br>**Transmitter**<br>~~a~~<br>|**Receiver**<br>~~ee~~<br>~~(~~|**Receiver**<br>~~ee~~<br>~~(~~|**Receiver**<br>~~ee~~<br>~~(~~|**Receiver**<br>~~ee~~<br>~~(~~|**Notes**|
|---|---|---|---|---|---|---|---|---|---|
|~~ee a~~<br>~~en~~<br>~~ee~~|**Lower Limit**<br>~~a~~<br>~~en~~<br>~~eeee~~||**Upper Limit**<br>~~a~~<br>~~en~~<br>~~eeee~~||**Lower Limit**<br>~~ee~~<br>~~en~~<br>~~(~~<br>~~ee~~<br>~~ee~~||**Upper Limit**<br>~~ee~~<br>~~en~~<br>~~eeee~~||~~en~~<br>~~ee~~|
|~~en~~<br>~~ee~~|**Min**<br>~~en~~<br>~~ee~~|**Max**<br>~~en~~<br>~~ee~~|**Min**<br>~~en~~<br>~~ee~~|**Max**<br>~~en~~<br>~~ee~~|**Min**<br>~~en~~<br>~~(~~<br>~~ee~~|**Max**<br>~~en~~<br>~~(~~<br>~~ee~~|**Min**<br>~~en~~<br>~~ee~~|**Max**<br>~~en~~<br>~~ee~~|~~en~~<br>~~ee~~|
|Clock Period T<br>~~ee ~~|Ttr<br> ~~ee ~~|-<br> ~~ee~~|-<br>~~ee ~~|-<br> ~~ee~~|Tr<br>~~(~~<br>~~ee~~|-<br>~~(~~<br>~~ee~~|-<br>~~ee ~~|-<br> ~~ee~~|~~ee~~|
|**Master Mode: Clock generated by transmitter or receiver**<br>~~ee~~<br>~~a~~||||||||||
|HIGH tHC|0.35Ttr<br>~~a~~<br>~~a~~|-<br>~~ee~~|-<br>~~ee~~|-<br>~~ee~~|0.35Ttr<br>~~ee~~<br>~~ee~~|-<br>~~ee~~|-<br>~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~eee~~||
|LOW tLC|0.35Ttr<br>~~a~~<br>~~a~~|-<br>~~ee~~<br>~~a ee~~|-<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|0.35Ttr<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~eee~~|-<br>~~ee~~<br>~~ee~~<br>~~eee~~||
|**Master Mode: Clock generated by transmitter or receiver**<br>~~ee~~<br>~~a~~<br>~~a ee~~<br>~~eee~~<br>~~aeeee~~||||||||||
|HIGH tHC|-<br>~~a~~<br>~~a~~|0.35Ttr<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~es~~|-<br>~~ee~~|0.35Ttr<br>~~ee~~|-<br>~~ee~~|-||
|LOW tLC|-<br>~~a ~~<br>~~a~~<br>~~a~~|0.35Ttr<br> ~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee ~~<br>~~ee~~<br>~~ee~~|-<br> ~~ee~~<br>~~es~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|0.35Ttr<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|-<br>~~ee~~||
|Rise time tRC|-<br>~~a ~~<br>~~a~~|-<br> ~~ee~~<br>~~ee~~|0.15Ttr<br>~~ee ~~<br>~~ee~~|-<br> ~~es ~~<br>~~ee~~|-<br> ~~ee ~~<br>~~ee~~|-<br> ~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|-<br>~~ee~~||
|**Transmitter**<br>~~a ee ee ee~~<br>~~ee ee~~<br>~~aee ee eeee~~||||||||||
|Delay tdtr|-<br>~~a~~|-<br>~~ee~~|-<br>~~ee ee ee~~|0.8T<br>~~ee ee~~|-<br>~~ee ee~~|-<br>~~ee~~|-|-||
|Hold time thtr|0<br>~~a ~~<br>~~a~~|-<br> ~~ee~~<br>~~ee~~|-<br>~~ee ee ee~~<br>~~ee ~~|-<br>~~ee ee~~<br> ~~se~~|-<br>~~ee ee ~~<br>~~se~~|-<br> ~~ee~~|-|-||



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|||**Transmitter**|**Transmitter**|||**Receiver**|**Receiver**|**Receiver**||**Notes**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Receiver**|||||||||||
|Setup time tsr|-|-|-|-|-|0.2Tr||-|-||
|Hold time thr|-|-|-|-|-|0||-|-||



The time periods specified in Figure 9 and Figure 10 are defined by the transmitter speed. The receiver specifications must match transmitter performance. 

_**Figure 9: I2S transmitter timing**_ 

_**Figure 10: I2S receiver timing**_ 

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A power on reset (POR) timing requirement is shown in Figure 11. 

## _**Figure 11: Power on reset (POR) timing**_ 

When the system requires a reset, you must hold the rest line in low state for longer than 3.96 milliseconds to complete the reset cycle. 

## **WARNING** 

An improper low state on the reset line (such as a voltage glitch) causes a system error due to a crash on the EEPROM content. 

A bypass cap such as 0.1uF placed on the reset line overcomes the issue caused by the glitch. 

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Table 18, Figure 12, Figure 13, and Figure 14 shows the antenna gain and performance. 

|**_Table 18: Antenna gain_**<br>**Unit in dBi @ 2440 MHz**<br>~~a~~|**XY-plane**<br>~~~~|~~|**XY-plane**<br>~~~~|~~|**XZ-plane**<br>~~|||~~|**XZ-plane**<br>~~|||~~|**YZ-plane**<br>~~|||~~|**YZ-plane**<br>~~|||~~|**Efficiency**<br>~~|~~<br>||
|---|---|---|---|---|---|---|---|
|AT3216-B2R7HAA<br>~~a~~<br>~~|~~<br>~~a~~|Peak<br>~~~~~~<br>~~|~~|Avg.<br>~~~~|~~|Peak<br>~~||~~<br>||Avg.<br>~~||~~<br>||Peak<br>~~||~~<br>||Avg.<br>~~||~~<br>|||
||0.1<br>~~~~~~<br>~~|~~|-4.1<br>~~~~ |~~|1.8<br>~~| |~~<br>||-3.3<br>~~| |~~<br>||-0.2<br>~~| |~~<br>||-6.8<br>~~| |~~<br>||41%<br>~~|~~<br>||



_**Figure 12: Antenna return loss**_ 

_**Figure 13: Measurement XYZ polarization**_ 

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## _**Table 19: Plane definitions**_ 

XY - Plane Theta = 90 `°` XZ – Plane Phi = 0 `°` YZ - Plane Phi = 90 `°` 

_**Figure 14: Antenna patterns**_ 

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BT850 PCB Ed 

**Note:** Dimensions are in millimeters Tolerances:     .xx ±0.03 mm for PCB PAD; ±0.15 mm for module size .x ±1.3 mm 

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## 10.2 BT851 Mechanical Drawing 

_**Figure 15: BT851 mechanical drawing**_ 

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Checklist (for PCB): 

- **MUST** locate the BT850 module close to the edge of PCB. 

- Use solid GND plane on inner layer (for best EMC and RF performance). 

- Place GND vias close to module GND pads as possible 

- Route traces to avoid noise being picked up on VCC supply. 

- Antenna Keep-out area: 

   - Ensure there is no copper in the antenna keep-out area on any layers of the host PCB. 

   - 

   - Keep all mounting hardware and metal clear of the area to allow proper antenna radiation. 

- For best antenna performance, place the BT850 module on the edge of the host PCB, preferably in the corner with the antenna facing the corner. 

- 

A different host PCB thickness dielectric will have small effect on antenna. 

_**Figure 16: Recommend antenna keep-out area (in blue) used on the BT850**_ 

Checklist (for metal/plastic enclosure): 

- Minimum safe distance for metals without seriously compromising the antenna (tuning) is 40 mm top/bottom and 30 mm left or right. 

- Metal close to the BT850-SA chip monopole antenna (bottom, top, left, right, any direction) will have degradation on the antenna performance. The amount of degradation is entirely system-dependent which means some testing by customers is required (in their host application). 

- Any metal closer than 20 mm starts to significantly degrade performance (S11, gain, radiation efficiency). 

- It is best that the customer tests the range with mock-up (or actual prototype) of the product to assess effects of enclosure height (and material, whether metal or plastic). 

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## 11.1.2 USB Dongle Design Example Using BT850-SA 

_**Figure 17: USB dongle design schematic**_ 

_**Figure 18: BT851 USB dongle, containing embedded BT850-SA**_ 

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Laird surface mount modules are designed to conform to all major manufacturing guidelines. This application note is intended to provide additional guidance beyond the information that is presented in the user manual. This application note is considered a living document and is updated as new information is presented. 

The modules are designed to meet the needs of a number of commercial and industrial applications. They are easy to manufacture and they conform to current automated manufacturing processes. 

## 12.2.1 Tape and Reel Package Information 

**Note:** Ordering information for Tape and Reel packaging is an addition of T/R to the end of the full module part number. For example, BT850-Sx becomes BT850-Sx-T/R. 

_**Figure 19: Reel specifications**_ 

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_**Figure 20: Tape specifications**_ 

There are 2500 BT850-Sx modules taped in a reel (and packaged in a pizza box) and five boxes per carton (12,500 modules per carton). Reel, boxes, and carton are labeled with the appropriate labels. See Figure 21. 

## 12.2.2 Packaging Process 

_**Figure 21: Packaging process**_ 

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Laird surface mount modules are designed to be easily manufactured, including reflow soldering to a PCB. Ultimately it is the responsibility of the customer to choose the appropriate solder paste and to ensure oven temperatures during reflow meet the requirements of the solder paste. Laird’s surface mount modules conform to J-STD-020D1 standards for reflow temperatures. 

**Important** : During reflow, modules should not be above 260° and not for more than 30 seconds. In addition, strongly recommend doesn’t let the module to go through the reflow over 1 time. Otherwise, it will to impact the soldering of module own. 

_**Figure 22: Recommended reflow temperature**_ 

Temperatures should not exceed the minimums or maximums presented in Table 20. 

_**Table 20: Recommended maximum and minimum temperatures**_ 

|**Specification**|**Value**|**Unit**|
|---|---|---|
|Temperature Inc./Dec. Rate(max)|1~3|°C / Sec|
|Temperature Decrease rate(goal)|2-4|°C / Sec|
|Soak TempIncrease rate(goal)|.5 - 1|°C / Sec|
|Flux Soak Period(Min)|70|Sec|
|Flux Soak Period(Max)|120|Sec|
|Flux Soak Temp (Min)|150|°C|
|Flux Soak Temp (max)|190|°C|
|Time Above Liquidous(max)|70|Sec|
|Time Above Liquidous(min)|50|Sec|
|Time in Target Reflow Range(goal)|30|Sec|
|Time at Absolute Peak(max)|5|Sec|
|Liquidous Temperature(SAC305)|218|°C|
|Lower Target Reflow Temperature|240|°C|
|Upper Target Reflow Temperature|250|°C|
|Absolute Peak Temperature|260|°C|



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**Note:** For complete regulatory information, refer to the BT850/BT851 Regulatory Information document which is also available from the BT850/BT851 product page. 

The BT850-Sx/BT851/DVK-BT850-Sx holds current certifications in the following countries: 

|**Country/Region**|**Regulatory ID**|
|---|---|
|USA (FCC)|SQGBT850|
|EU|N/A|
|Canada (ISED)|3147A-BT850|
|Japan (MIC)|201-170970|
|Australia|N/A|
|New Zealand|N/A|
|Korea (KC)|R-C-LAI-BT850-SA|



|**Part Number**<br>BT850-SA<br>~~ee~~|**Part Number**<br>BT850-SA<br>~~ee~~|**Description**<br>BTv5.0 Dual Mode USB HCI Module – Integrated Antenna|
|---|---|---|
||BT851|BTv5.0 Dual Mode USB Dongle|
||BT850-ST|BTv5.0 Dual Mode USB HCI Module – External Antenna|
||DVK-BT850-SA|Development Kit for BT850-SA Module – Integrated Antenna|
||DVK-BT850-ST|Development Kit for BT850-SA Module – External Antenna|



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This application note covers the procedure for generating a new Declaration ID for a Subsystem combination on the Bluetooth SIG website. In the instance of subsystems, a member can combine two or more subsystems to create a complete Bluetooth End Product solution. 

Subsystem listings referenced as an example: 

## _**Table 21: Subsystem combinations**_ 

|**Design Name**|**Owner**|**Declaration ID**|**Link to listing on the SIG website**|
|---|---|---|---|
|BT85x – BTv4.2|Laird|D037603|https://www.bluetooth.org/tpg/QLI_viewQDL.cfm?qid=37603|
|BT85x – BTv5|Laird|D043711|https://launchstudio.bluetooth.com/ListingDetails/78666|
|Windows 8<br>(Host Subsystem)|Microsoft<br>Corporation|B012854|https://www.bluetooth.org/tpg/QLI_viewQDL.cfm?qid=12854|



This procedure assumes that the member is simply combining two subsystems to create a new design, without any modification to the existing, qualified subsystems. This is achieved by using the Listing interface on the Bluetooth SIG website. Table 21 shows the basic subsystem combination of a controller and host subsystem. The Controller provides the RF/BB/LM and HCI layers, with the Host providing L2CAP, SDP, GAP, RFCOMM/SPP and any other specific protocols and profiles existing in the Host subsystem listing. The design may also include a Profile Subsystem. 

The controller provides the RF/BB/LM and HCI layers, with the Host providing L2CAP, SDP, GAP, RFCOMM/SPP and any other specific protocols and profiles existing in the Host subsystem listing. The design may also include a Profile Subsystem. 

_**Figure 23: Basic subsystem combination of a controller and host subsystem**_ 

The Qualification Process requires each company to registered as a member of the Bluetooth SIG – http://www.bluetooth.org 

The following link provides a link to the Bluetooth Registration page: https://www.bluetooth.org/login/register/ 

For each Bluetooth Design it is necessary to purchase a Declaration ID. This can be done before starting the new qualification, either through invoicing or credit card payment. The fees for the Declaration ID will depend on your membership status, please refer to the following webpage: 

https://www.bluetooth.org/en-us/test-qualification/qualification-overview/fees 

For a detailed procedure of how to obtain a new Declaration ID for your design, please refer to the following SIG document: 

https://www.bluetooth.org/DocMan/handlers/DownloadDoc.ashx?doc_id=283698&vId=317486 

To start the listing, go to: https://www.bluetooth.org/tpg/QLI_SDoc.cfm. 

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In step 1, select the option, **Reference a Qualified Design** and enter the Declaration IDs of each subsystem used in the End Product design. You can then select your pre-paid Declaration ID from the drop-down menu or go to the Purchase Declaration ID page, (please note that unless the Declaration ID is pre-paid or purchased with a credit card, it will not be possible to proceed until the SIG invoice is paid. 

Once all the relevant sections of step 1 are finished, complete steps 2, 3, and 4 as described in the help document. Your new Design will be listed on the SIG website and you can print your Certificate and DoC. 

For further information please refer to the following training material: 

https://www.bluetooth.org/en-us/test-qualification/qualification-overview/listing-process-updates 

Please contact your local sales representative or our support team for further assistance: 

Laird Connectivity Support Centre: https://www.lairdconnect.com/resources/support Email: wireless.support@lairdconnectivity.com Phone: Americas: +1-800-492-2320 Europe: +44-1628-858-940 Hong Kong: +852 2923 0610 Web: https://www.lairdconnect.com/products 

**Note:** Information contained in this document is subject to change. 

© Copyright 2020 Laird Connectivity. All Rights Reserved. Patent pending. Any information furnished by Laird Connectivity and its agents is believed to be accurate and reliable. All specifications are subject to change without notice. Responsibility for the use and application of Laird Connectivity materials or products rests with the end user since Laird Connectivity and its agents cannot be aware of all potential uses. Laird Connectivity makes no warranties as to non-infringement nor as to the fitness, merchantability, or sustainability of any Laird Connectivity materials or products for any specific or general uses. Laird Connectivity or any of its affiliates or agents shall not be liable for incidental or consequential damages of any kind. All Laird Connectivity products are sold pursuant to the Laird Connectivity Terms and Conditions of Sale in effect from time to time, a copy of which will be furnished upon request. Nothing herein provides a license under any Laird Connectivity or any third-party intellectual property right. 

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## Links

- [View this product on Novapart](https://novapart.co/products/BT851/bluetooth-module-ble-50-3-mbps-94-dbm-v-to-36-30-c)
- [Request a quote for this part](https://novapart.co/quote/)
- [Supplier page](https://es.farnell.com/laird-connectivity/bt851/bluetooth-module-ble-5-0-2-4-2/dp/4216110RL)
---

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