AX5045-1-TW30

## Ultra-Low Power Narrow-Band Sub GHz (60-1050 MHz) RF Transceiver with Integrated +23 dBm Hi h Power Am lifier g p 

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## AX5045 

## **OVERVIEW** 

## **Features** 

Narrow−Band Sub−GHz RF Transceiver with integrated +23 dBm high power amplifier (PA). 

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1 28<br>QFN28<br>CASE 485EH<br>**----- End of picture text -----**<br>


## _Low−Power_ 

- Receive 

   - ♦ 15 mA @ 915 MHz FSK, 1 kbps 

   - ♦ 35 A, Wake On Radio (WOR), Period of 200 msec | 

- Transmit 

   - ♦ 255 mA @ 23 dBm, 915 MHz FSK, 1 kbps 

- Standby Currents 

   - ♦ 121 nA Deep Sleep 

   - ♦ 640 nA Power Down with Wakeup Timer Running 

   - ♦ 700 nA Wake On Radio Standby 

## _Supply Voltage Range_ 

- 3.0 V to 3.6 V Single Supply 

## _Transmitter_ 

- Data−rates from 0.1 kbps to 200 kbps (FSK), 50 kbps (ASK), 10 kbps (PSK) 

- High Efficiency Integrated Power Amplifier 

- Unrestricted and Highly Linear Power Ramp Shaping 

- Maximum Output Power 

   - ♦ 23 dBm @ 915 MHz 

- Power Level Programmable in less than 0.5 dB Steps 

- GFSK Shaping with BT = 0.3 or BT = 0.5 

## **MARKING DIAGRAM** 

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1<br>ON<br>AX5045−1<br>AWLYYWW<br>AX5045−1 = Specific Device Code<br>A = Assembly Location<br>WL = Wafer Lot<br>YY = Year<br>WW = Work Week<br>= Pb−Free Package<br>(Note: Microdot may be in either location)<br>**----- End of picture text -----**<br>


(Note: Microdot may be in either location) **ORDERING INFORMATION Device Package Shipping** AX5045−1−TW30 QFN28 3000/ (Pb−Free) Tape & Reel ~~==~~ †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

## _Receiver_ 

- Data Rates from 0.1 kbps to 200 kbps (FSK), 50 kbps (ASK), 10 kbps (PSK) 

- Optional Forward Error Correction (FEC) 

- Sensitivity without FEC 

   - ♦ −132 dBm @ 0.1 kbps, 915 MHz, FSK, combined Rx and Tx match 

Publication Order Number: **AX5045/D** 

**1** 

© Semiconductor Components Industries, LLC, 2015 **May, 2021 − Rev. 0** 

## **AX5045** 

## **Features** (continued) 

- 0 dBm Maximum Input Power 

- Rx Sensitivity can be improved up to +3 dB by Using an External Tx/Rx Switch 

- Or Antenna Diversity can be used with Automatic Switching Control 

- Support for External Antenna Switch 

- Short Preamble Modes allow the Receiver to work with as little as 16 Preamble Bits 

## _Automatic Gain Control (AGC) and Automatic Frequency Control (AFC)_ 

- AFC up to ±10% 

## _Fast State Switching Times_ 

- 200 �s TX → RX Switching Time 

- 62 �s RX → TX Switching Time 

## _Frequency Generation_ 

- Configurable for Usage in 60 − 525 and 700 to 1050 MHz Bands 

- RF Carrier Frequency and FSK Deviation Programmable in 1 Hz Steps 

- Fully Integrated RF Frequency Synthesizer with VCO Auto−ranging and Band−width Boost Modes for Fast Locking 

- Configurable for either Fully Integrated or External Synthesizer Loop Filter for a Large Range of Bandwidths 

- Channel Hopping up to 2000 hops/s 

- Automatic Frequency Control (AFC) 

## _Wake on Radio (WOR)_ 

- Wake on Radio Dramatically Lowers Power Consumption during Receive Operation 

- 640 Hz or 10 kHz Lowest Power Wake−up Timer 

- Wake−up Time Interval programmable between 98 �s and 102 s 

- Ability to store RSSI, Frequency Offset and Data−rate Offset with the Packet Data 

- Multiple Receiver Parameter Sets allow the use of more aggressive Receiver Parameters during Preamble, dramatically shortening the Required Preamble Length with no Sensitivity Degradation 

_Advanced Crystal Oscillator (RF Reference Oscillator)_ 

- Fast Start−up and Lowest Power Steady−state XTAL Oscillator for a Wide Range of Crystals 

- Possibility of Applying an External Clock Reference (TCXO) 

## _Miscellaneous Features_ 

- SPI Microcontroller Interface 

- Extended Radio Register Set 

- Fully Integrated Current/Voltage References 

- QFN28 5 mm x 5 mm Package 

- Internal Power−on−Reset 

- Internal Brown−out Detection 

- 12 Bit 0.5 MS/s General Purpose ADC (GPADC) 

## **Applications** 

_60 − 525 and 700 to 1050 MHz Licensed and Unlicensed Radio Systems_ 

- Internet of Things (IoT) 

- Smart Retail Including Electronic Shelf Labels (ESL) 

- Automatic Meter Reading (AMR) 

- Security and Tracking Applications 

- Agriculture 

- Building Automation 

- Wireless Networks 

- Target Regulatory Regimes: EN 300 220 including the Narrow−band 12.5 kHz, 20 kHz and 25 kHz Definitions; EN 300 422; FCC Part 15.247; FCC Part 15.249; FCC Part 90 6.25 kHz, 12.5 kHz and 25 kHz 

## _Sophisticated Radio Controller_ 

- Antenna Diversity and Optional External RX/TX Switch Control 

- Fully Automatic Packet Reception and Transmission without Micro−controller Intervention 

- Hardware Support for HDLC, Raw, Wireless M−Bus Frames and Arbitrary Defined Frames 

- Automatic Channel Noise Level Tracking 

- �s Resolution Timestamps for Exact Timing 

   - (eg. for Frequency Hopping Systems) 

- 256 Byte Micro−programmable FIFO, optionally supports Packet Sizes > 256 Bytes 

- Three Matching Units for Preamble Byte, Sync−word and Address 

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**AX5045** 

## **BLOCK DIAGRAM** 

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25 26 AX5045 11 12<br>RX_NRX_P 56 LNA Mixer IF Filter &AGC PGAs ADC Digital IFchafilter nn el modulatorDe-<br>AGC<br>TX_P 3 Modulator<br>TX_N 4 PA<br>VCHOKE<br>27<br>VDD_IO FOUT Chip configuration Communication Controller &<br>Serial Interface<br>1,23 POR<br>FXTAL RF Frequency References Registers<br>Generation<br>Subsystem Low Power SPI<br>Oscillator Wake on Radio<br>RF Output 640 Hz/10kHz<br>60 MHz –<br>1.05 GHz<br>Crystal<br>Oscillator Divider<br>typ.<br>16 MHz Voltage<br>Regulator<br>19 20 21<br>28 27 13 8 7 23,1 14 15 16 17<br>23<br>GPADC1 GPADC2 DATA DCLK<br>Encoder Framing timing FIFO<br>Correction<br>Forward Error Radio Controller<br>and packet handling<br>Voltage<br>Regulator<br>CLKP CLKN<br>SYSCLK FILT VDD_ANA VDD_IO IRQ PWRAMP ANTSEL SEL CLK MISO MOSI<br>**----- End of picture text -----**<br>


**Figure 1. Functional Block Diagram of the AX5045** 

**Table 1. PIN FUNCTION DESCRIPTION** 

|**Symbol**|**Pin(s)**|**Type**|**Description**|
|---|---|---|---|
|VDD_IO|1|P|Power supply 3.0 V – 3.6 V|
|VCHOKE|2|P|Regulator Output to External PA choke inductors|
|TX_P|3|A|Differential TX antenna output|
|TX_N|4|A|Differential TX antenna output|
|RX_P|5|A|Differential RX antenna input|
|RX_N|6|P|Differential RX antenna input|
|VDD_ANA|7|P|Analog power output, decoupling|
|FILT|8|A|Optional synthesizer filter|
|NC|9|A|Not used|
|NC|10|A|Not used|
|DATA|11|I/O|In wire mode: Data input/output<br>Can be programmed to be used as a general purpose I/O pin Selectable<br>internal 65 k�pull−up resistor|
|DCLK|12|I/O|In wire mode: Clock output<br>Can be programmed to be used as a general purpose I/O pin Selectable<br>internal 65 k�pull−up resistor|



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**AX5045** 

**Table 1. PIN FUNCTION DESCRIPTION** (continued) 

|**Symbol**|**Pin(s)**|**Type**|**Description**|
|---|---|---|---|
|SYSCLK|13|I/O|Default functionality: Crystal oscillator (or divided) clock output Can be pro-<br>grammed to be used as a general purpose I/O pin Selectable internal 65 k�<br>pull−up resistor|
|SEL|14|I|Serial peripheral interface select|
|CLK|15|I|Serial peripheral interface clock|
|MISO|16|O|Serial peripheral interface data output|
|MOSI|17|I|Serial peripheral interface data input|
|NC|18|N|Must be left unconnected|
|IRQ|19|I/O|Default functionality: Transmit and receive interrupt<br>Can be programmed to be used as a general purpose I/O pin Selectable<br>internal 65 k�pull−up resistor|
|PWRAMP|20|I/O|Default functionality: Power amplifier control output<br>Can be programmed to be used as a general purpose I/O pin Selectable<br>internal 65 k�pull−up resistor|
|ANTSEL|21|I/O|Default functionality: Diversity antenna selection output<br>Can be programmed to be used as a general purpose I/O pin Selectable<br>internal 65 k�pull−up resistor|
|NC|22|N|Must be left unconnected|
|VDD_IO|23|P|Power supply 3.0 V – 3.6 V|
|NC|24|N|Must be left unconnected|
|GPADC1|25|A|GPADC input, must be connected to GND if not used|
|GPADC2|26|A|GPADC input, must be connected to GND if not used|
|CLKN|27|A|Crystal oscillator input/output. Leave unconnected when using TCXO|
|CLKP|28|A|Crystal oscillator input/output. TCXO input.|
|GND|Center pad|P|Ground on center pad of QFN, must be connected|



NOTE: All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5 V tolerant. A = analog input I = digital input signal O = digital output signal I/O = digital input/output signal N = not to be connected P = power or ground 

**PINOUT DRAWING** 

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28 27 26 25 24 23 22<br>VDD_IO 1 21 ANTSEL<br>VCHOKE 2 20 PWRAMP<br>TX_P 3 19 IRQ<br>GND<br>TX_N 4 center pad 18 NC<br>RX_P 5 17 MOSI<br>RX_N 6 16 MISO<br>VDD_ANA 7 15 CLK<br>8 9 10 11 12 13 14<br>CLKP CLKN GPADC2 GPADC1 NC VDD_IO NC<br>FILT NC NC DATA DCLK SYSCLK SEL<br>**----- End of picture text -----**<br>


**Figure 2. Pinout Drawing (Top View)** 

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**4** 

**AX5045** 

## **Table 2. ABSOLUTE MAXIMUM RATINGS** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|VDD_IO|Supply voltage||−0.5|5.5|V|
|IDD|Supply current|||300|mA|
|Ptot|Total power consumption|||900|mW|
|Pi|Absolute maximum input power at receiver input|RX_P and RX_N<br>pins in RX mode||10|dBm|
|II1|DC current into any pin except TX_P, TX_N, RX_P,<br>RX_N||−10|10|mA|
|II2|DC current into pins TX_P, TX_N, RX_P, RX_N||−100|100|mA|
|IO|Output Current|||40|mA|
|Via|Input voltage TX_P, TX_N, RX_P, RX_N pins||−0.5|5.5|V|
||Input voltage digital pins||−0.5|5.5|V|
|Vesd|Electrostatic handling|HBM|−2000|2000|V|
|Tamb|Operating temperature||−40|85|°C|
|Tstg|Storage temperature||−65|150|°C|
|Tj|Junction Temperature|||150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Exposure to absolute maximum rating conditions for extended periods may affect device reliabiloty. 

## **DC CHARACTERISTICS** 

**Table 3. SUPPLIES** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|TAMB|Operational ambient<br>temperature||−40|27|85|°C|
|VDD_IO|I/O and voltage regulator supply<br>voltage||3.0|3.3|3.6|V|
|VBOUT|Brown−out threshold|||1.3||V|
|IDSLLEP|Deep Sleep current:<br>All analog and digital functions<br>are powered down|PWRMODE = 0x01||121||nA|
|IPDOWN|Power−down current:<br>Register file contents preserved|PWRMODE = 0x00||640||nA|
|IWOR|Wakeup−on−radio mode:<br>Low power timer and WOR<br>state−machine are running at<br>640 Hz|PWRMODE = 0x0B||700||nA|
|ISTANBY|Standby−current:<br>All power domains are powered<br>up, crystal oscillator and<br>references are running|PWRMODE = 0x06||960||�A|
|IRX|Current consumption RX<br>PWRMODE = 0x09<br>RF Frequency Subsystem:<br>Internal loop−filter|915 MHz, datarate 6 kbps||15||mA|
|||915 MHz, datarate 100 kbps||16||mA|



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**5** 

**AX5045** 

**Table 3. SUPPLIES** (continued) 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ITX|Current consumption TX|915 MHz, 23 dBm, CW,<br>RF Frequency Subsystem: Internal<br>loop−filter  (Note 1)||255||mA|



1. With combined RX/TX matching network on 915 MHz DVK board at 3 V. 

**Table 4. LOGIC** 

|**Table 4. LOGIC**|||||||
|---|---|---|---|---|---|---|
|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|**DIGITAL INPUTS**|||||||
|VT+|Schmitt trigger low to high threshold point|||1.9||V|
|VT−|Schmitt trigger high to low threshold point|||1.2||V|
|VIL|Input voltage, low||||0.8|V|
|VIH|Input voltage, high||2.0|||V|
|IL|Input leakage current||−10||10|�A|
|Rpullup|Pull−up resistors<br>Pins DATA, DCLK, SYSCLK, IRQ,<br>PWRAMP, ANTSEL|Pull−up enabled in the rele-<br>vant pin configuration regis-<br>ters||65||k�|
|**DIGITAL INPUTS**|||||||
|IOH|Output Current, high|VDD_IO = 3 V, VOH= 2.4 V|4|||mA|
|IOL|Output Current, low|VDD_IO = 3 V, VOL= 0.4 V|4|||mA|
|IOZ|Tri−state output leakage current||−10||10|�A|



## **AC CHARACTERISTICS** 

**Table 5. CRYSTAL OSCILLATOR** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|fXTAL|Crystal frequency|Note 2, 3, 4|16|48|50|MHz|
|gmmaxosc_E|Oscillator transconductance<br>control range max|Set to 0xE||11||mS|
|gmminosc_1|Oscillator transconductance<br>control range min|Set to 0x1||1.1||mS|
|fext|External clock input (TCXO)|Note 3, 4, 6|10|16|50|MHz|
|RINosc|Input DC impedance||10|||k�|
|NDIVSYSCLK|Divider ratio fSYSCLK= fXTAL/<br>NDIVSYSCLK||20|24|210||



2. Tolerances and start−up times depend on the crystal used. Depending on the RF frequency and channel spacing the IC must be calibrated to the exact crystal frequency using the readings of the register TRKFREQ. 

3. The choice of crystal oscillator or TCXO frequency depends on the targeted regulatory regime for TX, see separate documentation on meeting regulatory requirements. 

4. To avoid spurious emission, the crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not an integer multiple of the crystal or TCXO frequency. 

5. The oscillator transconductance is regulated for fastest start−up time during start−up and for lowest power curing steady state oscillation. This means that values depend on the crystal used. 

6. Register XTALOSCMODE is used to select either a quartz crystal or TCXO as reference clock. TCXO mode is the default. 

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**6** 

**AX5045** 

**Table 6. LOW−POWER OSCILLATOR** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|fosc−slow|Oscillator frequency slow mode<br>LPOSC FAST = 0 in<br>AX5043_LPOSCCONFIG<br>register|No calibration|480|640|800|Hz|
|||After optional software calibration<br>against the crystal oscillator or TCXO,<br>does not include temperature or time<br>drift|630|640|650||
|fosc−fast|Oscillator frequency fast mode<br>LPOSC FAST = 1 in<br>AX5043_LPOSCCONFIG<br>register|No calibration|7.6|10.2|12.8|kHz|
|||After optional software calibration<br>against the crystal oscillator or TCXO,<br>does not include temperature or time<br>drift|9.8|10.2|10.8||



**Table 7. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|fREF|Reference frequency|The reference frequency<br>must be chosen so that the<br>RF carrier frequency is not<br>an integer multiple of the<br>reference frequency|16|48|50|MHz|
|**DIVIDERS**|||||||
|NDIVref|Reference divider ratio range|Controlled directly with<br>register REFDIV|20||22||
|NDIVm|Main divider ratio range|Controlled indirectly with<br>register FREQ|4.5||66.5||
|NDIVRF|RF divider range|Controlled directly with<br>register RFDIV|1||12||
|**CHARGE PUMP**|||||||
|ICPmax|Charge pump current max|||2186||�A|
|ICPmin|Charge pump current min|||8.6||�A|
|**INTERNAL VCO**|||||||
|fRF|RF frequency range|Depends on divider settings,<br>Excluding 525−699 MHz<br>Band|60||1050|MHz|
|fstep|RF frequency step|RFDIV = 1,<br>fxtal= 48.000000 MHz||0.98||Hz|
|BWmax|Synthesizer loop bandwidth maximum|The synthesizer loop band-<br>width and start−up time can<br>be programmed with regis-<br>ters PLLLOOP and PLLCPI.<br>For recommendations see<br>the AX5045 Programming<br>Manual.||350||kHz|
|BWmin|Synthesizer loop bandwidth minimum|||50||kHz|
|Tstart|Synthesizer start−up time if crystal<br>oscillator and reference are running||5||25|�s|
|PN915|Synthesizer phase noise 915 MHz<br>fREF= 48 MHz|10 kHz offset from carrier||−90||dBc/Hz|
|||1 MHz offset from carrier||−125|||



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**AX5045** 

**Table 8. TRANSMITTER** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|SBR_FSK|Signal bit rate|FSK|0.1||200|kbps|
|SBR_PSK|Signal bit rate|PSK|0.1||10|kbps|
|SBR_ASK|Signal bit rate|ASK|0.1||50|kbps|
|PTX|Max transmitter power @ 915 MHz|50�single ended measurement<br>at an SMA connector behind the<br>matching network (Note 8)||23||dBm|
||Min transmitter power @ 915 MHz|||−13|||
|PTXstep|Programming step size output power|Note 7|||0.5|dB|
|dTXtemp|Transmitter power variation vs.<br>temperature|−40°C to +85°C (Note 8)||±0.5||dB|
|dTXVdd|Transmitter power variation vs.<br>VDD_IO|3.0 to 3.6 V (Note 8)||±0.5||dB|
|Padj|Adjacent channel power<br>GFSK BT = 0.5, 500 Hz deviation,<br>1.2 kbps, 25 kHz channel spacing,<br>10 kHz channel BW|915 MHz||−57||dBc|
|PTX915−harm2|Emission @ 2nd harmonic|915 MHz (Note 8)||−50||dBm|
|PTX915−harm3|Emission @ 3rd harmonic|||−49|||



7. POUT = (TXPWRCOEFFB / 2[12] −1) × Pmax 8. 50 � measurement on 915 MHz DVK RF add−on board at 3 V. For recommended matching networks see section: Application Information. 

**Table 9. RECEIVER SENSITIVITIES** 

The table lists typical input sensitivities (without FEC) in dBm at the SMA connector with the complete combined RX/TX matching network for BER = 10[−3] at 915 MHz 

|**Data rate**<br>**[kbps]**||**FSK**<br>**h = 0.66**|**FSK**<br>**h = 1**|**FSK**<br>**h = 2**|**FSK**<br>**h = 4**|**FSK**<br>**h = 5**|**FSK**<br>**h = 8**|**FSK**<br>**h = 16**|**PSK**|
|---|---|---|---|---|---|---|---|---|---|
|0.1|Sensitivity [dBm]|−133.5|−132|−130|−129|−130|−128|−128|−130|
||RX Bandwidth [kHz]|0.2|0.2|0.3|0.5|0.6|0.9|2.1|0.2|
||Deviation [kHz]|0.033|0.05|0.1|0.2|0.25|0.4|0.8||
|1|Sensitivity [dBm]|−124.5|−123|−121|−120|−121.5|−119.5|−117|−127.5|
||RX Bandwidth [kHz]|1.5|2|3|6|7|11|21|2|
||Deviation [kHz]|0.33|0.5|1|2|2.5|4|8||
|10|Sensitivity [dBm]|−114|−113.5|−109.5|−110|−111.5|−108.5|−107|−117.5|
||RX Bandwidth [kHz]|15|20|30|55|60|110|220|20|
||Deviation [kHz]|3.3|5|10|20|25|40|80||
|100|Sensitivity [dBm]|−103.5|−102.5|−101||||||
||RX Bandwidth [kHz]|185|220|295||||||
||Deviation [kHz]|33|50|100||||||
|125|Sensitivity [dBm]|−100|−100|−96||||||
||RX Bandwidth [kHz]|225|250|380||||||
||Deviation [kHz]|42.3|62.5|125||||||
|200|Sensitivity [dBm]|−98|−97|||||||
||RX Bandwidth [kHz]|333|400|||||||
||Deviation [kHz]|66|100|||||||



9. Sensitivities are equivalent for 1010 data streams and PN9 whitened data streams. 

**Table 10. RECEIVER** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|SBR_FSK|Signal bit rate<br>|FSK|0.1||200|kbps|
|SBR_PSK|Signal bit rate<br>|PSK|0.1||10|kbps|
|SBR_ASK|Signal bit rate<br>|ASK|0.1||50|kbps|



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**AX5045** 

**Table 10. RECEIVER** (continued) 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISBER915|Input sensitivity at BER = 10−3 for<br>915 MHz operation, continuous<br>data, without FEC|FSK, h = 0.66, 100 kbps||−102||dBm|
|||FSK, h = 0.66, 10 kbps||−113|||
|||FSK, h = 0.66, 1 kbps||−123|||
|||PSK, 10 kbps||−116|||
|||PSK, 1 kbps||−124|||
|ISPER915FEC|Input sensitivity at PER = 1%, for<br>915 MHz operation, packet trans-<br>mission, with FEC|FSK, h = 0.66, 50 kbps||−105||dBm|
|||FSK, h = 0.66, 5 kbps||−117|||
|||FSK, h = 0.66, 0.5 kbps||−127|||
|ISPER915|Input sensitivity at PER = 1%, for<br>915 MHz operation, 144 bit pack-<br>et data, without FEC|FSK, h = 0.66, 100 kbps||−98||dBm|
|||FSK, h = 0.66, 10 kbps||−111|||
|||FSK, h = 0.66, 1.2 kbps||−120|||
|ISWOR915|Input sensitivity at PER = 1% for<br>915 MHz operation, 144 bit<br>packet data, WOR−mode, without<br>FEC|FSK, h = 0.5, 100 kpbs||−101||dBm|
|CP1dB|Input referred compression point|2 tones separated by 100 kHz||−32||dBm|
|RSSIRL|Lower RSSI control range.|Condition =  FSK, 500 Hz devia-<br>tion, 1.2 kbps.||−125||dBm|
|RSSIRU|Upper RSSI control range.|Condition = FSK, 500 Hz devia-<br>tion, 1.2 kbps.||−35||dBm|
|RSSIS1|RSSI step size|Before digital channel filter; calcu-<br>lated from register AGC-<br>COUNTER||0.75||dB|
|RSSIS2|RSSI step size|Behind digital channel filter;<br>calculated from registers AGC-<br>COUNTER, TRKAMPL||0.1||dB|
|RSSIS3|RSSI step size|Behind digital channel filter;<br>reading register RSSI||1||dB|
|SEL915|Adjacent channel suppression|±25 kHz channels (Note 10)||32||dB|
|||±100 kHz channels (Note 11)||34|||
|||±200 kHz channels (Note 11)||60|||
|BLK915|Blocking at offset|+1 MHz (Note 12)||64||dB|
|||+10 MHz (Note 12)||78|||
|RAFC|AFC pull−in range|The AFC pull−in range can be<br>programmed with the MAXR-<br>FOFFSET registers.<br>The AFC response time can be<br>programmed with the FRE-<br>QGAIND register. This is<br>a percentage of the RXBW.|15|||%|
|RDROFF|Bitrate offset pull−in range|The bitrate pull−in range can be<br>programmed with the<br>MAXDROFFSET registers. This<br>is a percentage of the RXBW.|10|||%|



10.Interferer/Channel @ BER = 10[−3] , channel level is +3 dB above the typical sensitivity, the interfering signal is CW; channel signal is FSK modulated at 1 kbps, modh = 0.66. 

11. Interferer/Channel @ BER = 10[−3] , channel level is +3 dB above the typical sensitivity, the interfering signal is CW; channel signal is FSK modulated at 10 kbps, modh = 0.66. 

12.Channel/Blocker @ BER = 10[−3] , channel level is +3 dB above the typical sensitivity, the blocker signal is CW; channel signal is FSK modulated at 10 kbps, modh = 0.66. 

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**AX5045** 

**Table 11. RECEIVER AND TRANSMITTER SETTLING TIMES** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Txtal|XTAL settling time|Powermodes: POWERDOWN to<br>STANDBY<br>Note that Txtaldepends on the<br>specific crystal used.||0.5||ms|
|Tsynth|Synthesizer settling time|Powermodes:<br>STANDBY to SYNTHTX or<br>SYNTHRX||40||�s|
|Ttx|TX settling time|Powermodes:<br>SYNTHTX to FULLTX<br>Ttxis the time used for power<br>ramping, this can be programmed<br>to be 1 x tbit, 2 x tbit,<br>4 x tbitor 8 x tbit.<br>(Notes 13, 14)|0|1 x tbit|8 x tbit|�s|
|Trx_init|RX initialization time|||150||�s|
|Trx_rssi|RX RSSI acquisition time (after<br>Trx_init)|Powermodes: SYNTHRX to<br>FULLRX<br>Modulation (G)FSK<br>(Notes 13, 14)||80 +<br>3 x tbit||�s|
|Trx_preamble|RX RSSI acquisition time to valid<br>data RX at full sensitivity/<br>selectivity (after Trx_init)|||80 +<br>3 x tbit||�s|



13.tbit depends on the datarate, e.g. fr 10 kbps tbit = 100 � s 

14. I n wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins. 

**Table 12. OVERALL STATE TRANSITION TIMES** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ttx_on|TX startup time|Powermodes: STANDBY to<br>FULLTX<br>(Notes 15, 16)|40|40 + 1 x tbit||�s|
|Trx_on|RX startup time|Powermodes: STANDBY to<br>FULLRX||190||�s|
|Trx_rssi|RX startup time to valid RSSI|Powermodes: STANDBY to<br>FULLRX<br>Modulation (G)FSK<br>(Notes 15, 16)||270 +<br>3 x tbit||�s|
|Trx_data|RX startup time to valid data at<br>full sensitivity/selectivity|||190 +<br>9 x tbit||�s|
|Trxtx|RX to TX switching|Powermodes: FULLRX to<br>FULLTX||62||�s|
|Ttxrx|TX to RX switching (to preamble<br>start)|Powermodes: FULLTX to FULL-<br>RX||200|||
|Thop|Frequency hop|Switch between frequency de-<br>fined in register FREQA and<br>FREQB||30||�s|



15.tbit depends on the datarate, e.g. fr 10 kbps tbit = 100 � s 

16. I n wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins. 

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**AX5045** 

## **Table 13. SPI TIMING** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Tss|SEL falling edge to CLK rising<br>edge||10|||ns|
|Tsh|CLK falling edge to SEL rising<br>edge||10|||ns|
|Tssd|SEL falling edge to MISO driving||0||10|ns|
|Tssz|SEL rising edge to MISO high−Z||0||10|ns|
|Ts|MOSI setup time||10|||ns|
|Th|MOSI hold time||10|||ns|
|Tco|CLK falling edge to MISO output||||10|ns|
|Tck|CLK period|(Note 17)|50|||ns|
|Tcl|CLK low duration||15|||ns|
|Tch|CLK high duration||15|||ns|



17.For SPI access during power−down mode the period should be relaxed to 100 ns 

18.For a figure showing the SPI timing parameters see section: Serial Peripheral Interface (SPI). 

## **Table 14. WIRE MODE INTERFACE TIMING** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Tdck|SEL falling edge to CLK rising<br>edge|Depends on bit rate programming|1.6||10.000|ms|
|Tdcl|DCLK low duration||25||75|%|
|Tdch|DCLK high duration||25||75|%|
|Tds|DATA setup time relative to active<br>DCLK edge||10|||ns|
|Tdh|DATA hold time relative to active<br>DCLK edge||10|||ns|
|Tdco|DATA output change relative to<br>active DCLK edge||||10|ns|



19.For a figure showing the wire mode interface timing parameters see section: Wire Mode Interface. 

**Table 15. GENERAL PURPOSE ADC (GPADC)** 

|**Symbol**|**Description**|**Condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Res|Nominal ADC resolution|||12||bit|
|Fconv|Conversion rate||0.03||1|MS/s|
|DR|Dynamic range|||72||dB|
|INL|Integral nonlinearity||−4||+4|LSB|
|DNL|Differential nonlinearity||−1|+1.5||LSB|
|Zin|Input impedance|Single−ended||25||k�|
|VDC−IN|Input DC level|||0.8||V|
|VIN−DIFF|Input signal range (differential)||−500||500|mV|
|VIN−SE|Input signal range (single−ended,<br>signal input at pin GPADC1,<br>pin GPADC2 open)||300||1300|mV|



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**AX5045** 

## **CIRCUIT DESCRIPTION** 

The AX5045 is a true single chip ultra−low power narrow−band CMOS RF transceiver for use in licensed and unlicensed bands from 60−525 and 700 to 1050 MHz. The on−chip transceiver consists of a fully integrated RF front−end with modulator, and demodulator. Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the SPI interface. 

AX5045 can be operated from a 3.0 V to 3.6 V power supply over a temperature range of −40°C to 85°C. It consumes 255 mA for transmitting at 915 MHz carrier frequency at 23 dBm. In receive operation AX5045 consumes 15 mA at 915 MHz carrier frequency. 

AX5045 supports any data rate from 0.1 kbps to 200 kbps for FSK, 4−FSK, GFSK, GMSK, and MSK. ASK supports datarates up to 50 kbps and PSK supports datarates up to 10 kbps. To achieve optimum performance for specific data rates and modulation schemes several register settings to configure the AX5045 are necessary, for details see the AX5045 Programming Manual. 

The AX5045 can be operated in two fundamentally different modes. 

In **frame mode** data is sent and received via the SPI port in frames. Pre−and post−ambles as well as checksums can be generated automatically. Interrupts can be used to control the data flow between a micro−controller and the AX5045. 

In **wire mode** the IC behaves as an extension of any wire. The internal communication controller is disabled and the modem data is directly available on a dedicated pin (DATA). The bit clock is also output on a dedicated pin (DCLK). In this mode the user can connect the data pin to any port of a micro−controller or to a UART, but has to control coding, checksums, pre and post ambles. The user can choose between synchronous and asynchronous wire mode, asynchronous wire mode performs RS232 start bit recognition and re−synchronization for transmit. 

Both modes can be used both for transmit and receive. In both cases the AX5045 behaves as a SPI slave interface. Configuration of the AX5045 is always done via the SPI interface. 

The receiver and the transmitter support multi−channel operation for all data rates and modulation schemes. 

## **Voltage Regulators** 

The AX5045 uses an on−chip voltage regulator system to create stable supply voltages for the internal circuitry from the primary supply VDD_IO. The I/O level of the digital pins is VDD_IO. 

The AX5045 power amplifier external choke inductors are powered by the regulated VCHOKE pin and not directly tied to the battery. This has the advantage that the current and output power do not vary much over supply voltage and allows for amplitude shaping. 

Pins VDD_ANA are supplied for external decoupling of the power supply used for the on−chip PA. 

The voltage regulator system must be set into the appropriate state before receive or transmit operations can be initiated. This is handled automatically when programming the device modes via the PWRMODE register. 

Register POWSTAT contains status bits that can be read to check if the regulated voltages are ready (bit SVIO) or if VDD_IO has dropped below the brown−out level of 1.3 V (bit SSUM). 

In power−down mode the core supply voltages for digital and analog functions are switched off to minimize leakage power. Most register contents are preserved but access to the FIFO is not possible and FIFO contents are lost. SPI access to registers is possible, but at lower speed. 

In deep−sleep mode all supply voltages are switched off. All digital and analog functions are disabled. All register contents are lost. To leave deep−sleep mode the pin SEL has to be pulled low. This will initiate startup and reset of the AX5045. Then the MISO line should be polled, as it will be held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation. 

## **Crystal Oscillator and TCXO Interface** 

The AX5045 is normally operated with an external TCXO, which is required by most narrow−band regulations with a tolerance of 0.5 ppm to 1.5 ppm depending on the regulatory requirements. The on−chip crystal oscillator allows the use of an inexpensive quartz crystal as the RF generation subsystem’s timing reference when possible from a regulatory point of view. 

A wide range of crystal frequencies can be handled by the crystal oscillator circuit. As the reference frequency impacts both the spectral performance of the transmitter as well as the current consumption of the receiver, the choice of reference frequency should be made according to the regulatory regime targeted by the application. 

The crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not near an integer multiple of the crystal or TCXO frequency. 

The oscillator circuit is enabled by programming the PWRMODE register. At power−up it is disabled. By default the oscillator circuit expects a TCXO to be connected to the CLKP pin, while CLKN has to be left unconnected. No special register settings are required. 

Alternatively a quartz crystal can be connected. The transconductance of the oscillator is automatically regulated, to allow for fastest start−up times together with lowest power operation during steady−state oscillation. 

To synchronize the receiver frequency to a carrier signal, the recommended method to implement frequency 

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**12** 

**AX5045** 

synchronization is to make use of the high resolution RF frequency generation sub−system together with the Automatic Frequency Control. 

## **Low Power Oscillator and Wake−on−Radio (WOR) Mode** 

The AX5045 features an internal ultra−low power oscillator. In default mode the frequency of oscillation is 640 Hz ±1.5%, in fast mode it is 10.2 kHz ±1.5%. These accuracies are reached after the internal hardware has been used to calibrate the low power oscillator versus the RF reference clock. This procedure can be run in the background during transmit or receive operations. 

The low power oscillator makes a WOR mode with a power consumption of 700 nA possible. 

If Wake on Radio Mode is enabled, the receiver wakes up periodically at a user selectable interval, and checks for a radio signal on the selected channel. If no signal is detected, the receiver shuts down again. If a radio signal is detected, and a valid packet is received, the microcontroller is alerted by asserting an interrupt. 

The AX5045 can thus autonomously poll for radio signals, while the external micro−controller can stay powered down, and only wakes up once a valid packet is received. This allows for very low average receiver power, at the expense of longer preambles at the transmitter. 

## _GPIO Pins_ 

Pins DATA, DCLK,SYSCLK, IRQ, ANTSEL, PWRAMP can be used as general purpose I/O pins by programming pin configuration registers PINFUNCSYSCLK, PINFUNCDCLK, PINFUNCDATA, PINFUNCIRQ, PINFUNCNANTSEL, PINFUNCPWRAMP. Pin input values can be read via register PINSTATE. Pull−ups are disabled if output data is programmed to the GPIO pin. 

**==> picture [222 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD_IO<br>enable weak pull−up<br>enable output<br>VDD_IO 65 k �<br>output data<br>input data<br>**----- End of picture text -----**<br>


**Figure 3. GPIO Pin** 

## **SYSCLK Output** 

The SYSCLK pin outputs either the reference clock signal divided by a programmable power of two or the low power oscillator clock. Division ratios from 1 to 1024 are possible. For divider ratios > 1 the duty cycle is 50%. Bits SYSCLK[4:0] in the PINFUNCSYSCLK register set the divider ratio. By default the SYSCLK output is disabled. 

## **Power−on−Reset (POR)** 

AX5045 has an integrated power−on−reset block. No external POR circuit is required. 

After POR the AX5045 can be reset by first setting the SPI SEL pin to high for at least 100 ns, then setting followed by resetting the bit RST in the PWRMODE register. 

After POR or reset all registers are set to their default values. 

## **RF Frequency Generation Subsystem** 

The RF frequency generation subsystem consists of a fully integrated synthesizer, which multiplies the reference frequency from the crystal oscillator to get the desired RF frequency. The advanced architecture of the synthesizer enables frequency resolutions of 1 Hz, as well as fast settling times of 5 – 50 �s depending on the settings (see section AC Characteristics). Fast settling times mean fast start−up and fast RX/TX switching, which enables low−power system design. 

For receive operation the RF frequency is fed to the mixer, for transmit operation to the power−amplifier. 

The frequency must be programmed to the desired carrier frequency. 

The synthesizer loop bandwidth can be programmed, this serves three purposes: 

1. Start−up time optimization, start−up is faster for higher synthesizer loop bandwidths. 

2. TX spectrum optimization, phase−noise at 300 kHz to 1 MHz distance from the carrier improves with lower synthesizer loop bandwidths. 

3. Adaptation of the bandwidth to the data−rate. For transmission of FSK and MSK it is required that the synthesizer bandwidth must be in the order of the data−rate. 

## _VCO_ 

An on−chip VCO converts the control voltage generated by the charge pump and loop filter into an output frequency. This frequency is used for transmit as well as for receive operation. The frequency can be programmed in 1 Hz steps in the FREQ registers. The RFDIV bits in the PLLVCODIV register must be programmed to the desired frequency band. 

The fully integrated VCO allows to operate the device in the frequency range 60 − 525 and 700 – 1050 MHz. 

## _VCO Auto−Ranging_ 

The AX5045 has an integrated auto−ranging function, which allows to set the correct VCO range for specific frequency generation subsystem settings automatically. 

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**AX5045** 

Typically it has to be executed after power−up. The function is initiated by setting the RNG_START bit in the PLLRANGINGA or PLLRANGINGB register. The bit is readable and a 0 indicates the end of the ranging process. Setting RNG_START in the PLLRANGINGA register ranges the frequency in FREQA, while setting RNG_START in the PLLRANGINGB register ranges the frequency in FREQB. The RNGERR bit indicates the correct execution of the auto−ranging. The AX5045 can also be configured to compensate for slow, time−varying changes in the optimal range setting. 

## _Loop Filter and Charge Pump_ 

The AX5045 internal loop filter configuration together with the charge pump current sets the synthesizer loop band width. The internal loop−filter has three configurations that can be programmed via the register bits FLT[1:0] in registers PLLLOOP or PLLLOOPBOOST the charge pump current can be programmed using register bits PLLCPI[7:0] in 

registers PLLCPI or PLLCPIBOOST. Synthesizer bandwidths are typically 50 – 350 kHz depending on the PLLLOOP or PLLLOOPBOOST settings, for details see the section: AC Characteristics. The AX5045 can be setup in such a way that when the synthesizer is started, the settings in the registers PLLLOOPBOOST and PLLCPIBOOST are applied first for a programmable duration before reverting to the settings in PLLLOOP and PLLCPI _**.**_ This feature enables automated fastest start−up. 

Setting bits FLT[1:0] = 00 bypasses the internal loop filter and the VCO control voltage is output to an external loop filter at pin FILT. This mode of operation is recommended for achieving lower bandwidths than with the internal loop filter. 

## _Registers_ 

See Table 16. 

**Table 16. RF FREQUENCY GENERATION REGISTERS** 

|**Register**|**Bits**|**Purpose**|
|---|---|---|
|PLLLOOP<br>PLLLOOPBOOST|FLT[1:0]|Synthesizer loop filter bandwidth and selection of external loop filter, recommended us-<br>age is to increase the bandwidth for faster settling time, bandwidth increases of factor 2<br>and 5 are possible.|
|PLLCPI<br>PLLCPIBOOST||Synthesizer charge pump current, recommended usage is to decrease the bandwidth<br>(and improve the phase−noise) for low data−rate transmissions.|
|PLLVCODIV|REFDIV|Sets the synthesizer reference divider ratio.|
||RFDIV|Sets the synthesizer output divider ratio.|
|FREQA, FREQB||Programming of the carrier frequency.|
|PLLRANGINGA, PLLRANGINGB||Initiate VCO auto−ranging and check results.|



## **RF Input and Output Stage (RX_N/RX_P/TX_N/TX_P)** 

RX uses differential pins RX_P and RX_N. TX uses the differential antenna pins TX_P and TX_N. RX/TX switching can be done either with an external RX/TX switch (Figure 10) or with a direct tie configuration (Figure 8). 

Pin PWRAMP can be used to control an external RX/TX switch. Pin ANTSEL can be used to control an external antenna switch when receiving with two antennas (Figure 10). 

When antenna diversity is enabled, the radio controller will, when not in the middle of receiving a packet, 

periodically probe both antennas and select the antenna with the highest signal strength. The radio controller can be instructed to periodically write both RSSI values into the FIFO. Antenna diversity mode is fully automatic. 

## _LNA_ 

The LNA amplifies the differential RF signal from the antenna and buffers it to drive the I/Q mixer. An external matching network is used to adapt the antenna impedance to the IC impedance. A DC feed to GND must be provided at the antenna pins (RX_P & RX_N). For recommendations see section: Application Information. 

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**AX5045** 

## _PA_ 

In TX mode the PA drives the signal generated by the frequency generation subsystem out to the differential antenna pins TX_P and TX_N. In register MODCFGA bit TXDIFF must be set high and bit TXSE must be set low. 

The output power of the PA is programmed via the register TXPWRCOEFFB. 

The PA can be digitally pre−distorted for high linearity. The output amplitude can be shaped (raised cosine), this mode is selected with bit AMPLSHAPE in register MODCFGA. PA ramping is programmable in increments of the bit time and can be set to 1 – 8 bit times via bits SLOWRAMP in register MODCFGA _**.**_ 

Output power and efficiency, as well as harmonic content will depend on the external impedance seen by the power amplifier (PA). Matching circuit recommendations are given in the section: Application Information. 

## **Digital IF Channel Filter and Demodulator** 

The digital IF channel filter and the demodulator extract the data bit−stream from the incoming IF signal. They must be programmed to match the modulation scheme as well as the data−rate. Inaccurate programming will lead to loss of sensitivity. 

The channel filter offers bandwidths of 119 Hz up to 221 kHz (with reference frequencies above 16 MHz higher bandwidths are possible). 

An overview of the registers involved is given in the following Table 17 as reference. The register setups typically must be done once at power−up of the device. 

## _Registers_ 

See Table 17. 

**Table 17. CHANNEL FILTER AND DEMODULATOR REGISTERS** 

|**Register**|**Remarks**|
|---|---|
|DECIMATION|This register programs the bandwidth of the digital channel filter.|
|RXDATARATE2…RXDATARATE0|These registers specify the receiver bit rate, relative to the channel filter bandwidth.|
|MAXDROFFSET2…MAXDROFFSET0|These registers specify the maximum possible data rate offset.|
|MAXRFOFFSET2…MAXRFOFFSET0|These registers specify the maximum possible RF frequency offset|
|TIMEGAIN, DRGAIN|These registers specify the aggressiveness of the receiver bit timing recovery. More<br>aggressive settings allow the receiver to synchronize with shorter preambles, at the<br>expense of more timing jitter and thus a higher bit error rate at a given signal−to−noise<br>ratio.|
|MODULATION|This register selects the modulation to be used by the transmitter and the receiver,<br>i.e. whether ASK, FSK, PSK should be used.|
|PHASEGAIN, FREQGAINA, FREQGAINB,<br>FREQGAINC, FREQGAIND, AMPLGAIN|These registers control the bandwidth of the phase, frequency offset and amplitude<br>tracking loops.|
|AGCINCREASE, AGCREDUCE|These register controls the AGC (automatic gain control) loop slopes, and thus the<br>speed of gain adjustments. The faster the bit−rate, the faster the AGC loop should be.|
|TXRATE|These registers control the bit rate of the transmitter.|
|FSKDEV|These registers control the frequency deviation of the transmitter in FSK mode. The<br>receiver does not explicitly need to know the frequency deviation, only the channel<br>filter bandwidth has to be set wide enough for the complete modulation to pass.|



## **Encoder** 

The encoder is located between the Framing Unit, the Demodulator and the Modulator. It can optionally transform the bit−stream in the following ways: 

- It can invert the bit stream. In 4−FSK mode, inversion for the LSB and MSB of a DiBit symbol can be set independently. 

- It can perform differential encoding. This means that a zero is transmitted as no change in the level, and a one is transmitted as a change in the level. 

- It can perform Manchester encoding. Manchester encoding ensures that the modulation has no DC content and enough transitions (changes from 0 to 1 and from 1 to 0) for the demodulator bit timing recovery to function correctly, but does so at a doubling of the data rate. 

- It can perform spectral shaping (also known as whitening). Spectral shaping removes DC content of the bit stream, ensures transitions for the demodulator bit timing recovery, and makes sure that the transmitted spectrum does not have discrete lines even if the transmitted data is cyclic. It does so without adding additional bits, i.e. without changing the data rate. Spectral Shaping uses a feedback shift register which can selectively implement the polynomials PN9, PN15 and PN17. Available options are both additive (synchronous) or multiplicative (self−synchronizing) scrambling. 

The encoder is programmed using the register ENCODING, details and recommendations on usage are given in the AX5045 Programming Manual. 

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**AX5045** 

## **Framing and FIFO** 

Most radio systems today group data into packets. The framing unit is responsible for converting these packets into a bit−stream suitable for the modulator, and to extract packets from the continuous bit−stream arriving from the demodulator. 

The Framing unit supports two different modes: 

- Packet modes 

- Raw modes 

The micro−controller communicates with the framing unit through a 256 byte FIFO. Data in the FIFO is organized in chunks. The chunk header encodes the length and what data is contained in the payload. Chunks may contain packet data, but also RSSI, Frequency offset, Timestamps, etc. 

The AX5045 contains one FIFO. Its direction is switched depending on whether transmit or receive mode is selected. 

The FIFO can be operated in polled or interrupt driven modes. In polled mode, the microcontroller must periodically read the FIFO status register or the FIFO count register to determine whether the FIFO needs servicing. 

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are provided. The AX5045 signals interrupts by asserting (driving high) its IRQ line. The interrupt line is level triggered, active high. 

Interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or filling the FIFO. 

Basic FIFO status (EMPTY, FULL, Overrun, Underrun, FIFO fill level above threshold, FIFO free space above threshold) are also provided during each SPI access on MISO while the micro−controller shifts out the register address on MOSI. See the SPI interface section for details. This feature significantly reduces the number of SPI accesses necessary during transmit and receive. 

## _Packet Modes_ 

The AX5045 offers different packet modes. For arbitrary packet sizes HDLC is recommended due to its automated flag and bit−stuffing mechanism. The AX5045 also offers packet modes with fixed packet length with up to 12 bits indicating the length of the packet. 

In packet modes a cyclic redundancy check (CRC) can be computed automatically. 

HDLC Mode is the main framing mode of the AX5045. In this mode, the AX5045 performs automatic packet delimiting, and optional packet correctness check by inserting and checking a CRC field. 

NOTE: HDLC mode follows High−Level Data Link Control (HDLC, ISO 13239) protocol. The packet structure is given in the following Table 18. 

**Table 18. HDLC PACKET STRUCTURE** 

|**Flag**|**Address**|**Control**|**Information**|**FCS**|**Flag**|
|---|---|---|---|---|---|
|8 bit|8 bit|8 or 16 bit|Variable length, 0 or more bits in multiples of 8|16/32 bit|8 bit|



20.The end flag of one frame can be used as the start flag of the next frame. 

HDLC packets are delimited with flag sequences of content 0x7E. 

In AX5045 the meaning of address and control is user defined. The Frame Check Sequence (FCS) can be programmed to be CRC−CCITT, CRC−16 or CRC−32. 

Another standardized mode supported by AX5045 is Wireless M−Bus, the packet structure is given in the following Table 19. 

NOTE: Wireless M−Bus mode follows EN13757−4. 

The receiver checks the CRC, the result can be retrieved from the FIFO. In HDLC mode the CRC is always appended to the received data. 

**Table 19. WIRELESS M−BUS PACKET STRUCTURE** 

|**Preamble**|**L**|**C**|**M**|**A**|**FCS**|**Optional Data Block**<br>**(optionally repeated with FCS)**|**FCS**|
|---|---|---|---|---|---|---|---|
|variable|8 bit|8 bit|16 bit|48 bit|16 bit|8 − 96 bit|16 bit|



For details on implementing an HDLC communication as well as Wireless M−Bus please see the AX5045 Programming Manual. 

## _Raw Modes_ 

In Raw mode, the AX5045 does not perform any packet delimiting or byte synchronization. It simply serializes transmit bytes and de−serializes the received bit−stream and groups it into bytes. This mode is ideal for implementing legacy protocols in software. 

Raw mode with preamble match is similar to raw mode. _In this mode, however, the receiver does not receive anything until it detects a user programmable bit pattern (called the preamble) in the receive bit−stream._ When it detects the preamble, it aligns the de−serialization to it. 

AX5045 can search for up to two different preambles. Each preamble can be between 4 and 32 bits long. 

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**AX5045** 

## **RX AGC and RSSI** 

AX5045 features three receiver signal strength indicators (RSSI): 

1. RSSI before the digital IF channel filter. The gain of the receiver is adjusted in order to keep the analog IF filter output level inside the working range of the ADC and demodulator. The register AGCCOUNTER contains the current value of the AGC and can be used as an RSSI. The step size of this RSSI is 0.75 dB. The value can be used as soon as the RF frequency generation sub−system has been programmed. 

2. RSSI behind the digital IF channel filter. The register RSSI contains the current value of the RSSI behind the digital IF channel filter. The step size of this RSSI is 1 dB. It is possible to set an 

interrupt getting asserted when the RSSI exceeds or falls below a defined threshold value. 

3. RSSI behind the digital IF channel filter – high accuracy. 

   - The demodulator also provides amplitude information in the TRK_AMPLITUDE register. By combining both the AGCCOUNTER and the TRK_AMPLITUDE registers, a high resolution (better than 0.1 dB) RSSI value can be computed at the expense of a few arithmetic operations on the micro−controller. More details can be found in the AX5045 Programming Manual. 

## **Modulator** 

Depending on the transmitter settings the modulator generates various inputs for the PA (see Table 20): 

**Table 20. MODULATIONS** 

|**Modulation**|**Bit = 0**|**Bit = 1**|**Main Lobe Bandwidth**|**Max. Bitrate**|
|---|---|---|---|---|
|ASK|PA off|PA on|BW = BITRATE|50 kBit/s|
|FSK/MSK/GFSK/GMSK|�f = −fdeviation|�f = +fdeviation|BW = (1+h)×BITRATE|200 kBit/s|
|PSK|��= 0°|��= 180°|BW = BITRATE|10 kBit/s|



NOTE: h = modulation index. It is the ratio of the deviation compared to the bit−rate; fdeviation = 0.5VhVBITRATE, AX5045 can demodulate signals with h < 32 ASK = amplitude shift keying FSK = frequency shift keying MSK = minimum shift keying; MSK is a special case of FSK, where h = 0.5, and therefore fdeviation = 0.25 BITRATE; the advantage of MSK over FSK is that it can be demodulated more robustly PSK = phase shift keying 

All modulation schemes, except 4−FSK, are binary. Amplitude can be shaped using a raised cosine waveform. Amplitude shaping will also be performed for constant amplitude modulation ((G)FSK, (G)MSK) when ramping up and down the PA. Amplitude shaping should always be enabled. 

Frequency shaping can either be hard (FSK, MSK), or Gaussian (GMSK, GFSK), with selectable BT = 0.3 or BT = 0.5. 

## **Table 21. 4−FSK MODULATION** 

|**Modulation**|**DiBit = 00**|**DiBit = 01**|**DiBit = 11**|**DiBit = 10**|**DiBit = 10**|**Main Lobe**<br>**Bandwidth**|**Max. Bitrate**|
|---|---|---|---|---|---|---|---|
|4−FSK|�f = −3fdeviation|�f = −fdeviation|�f = +fdeviation|�f = +3fdeviation||BW = (1 + 3 h)<br>×BITRATE|200 kBit/s|
|4−FSK Frequency shaping is always hard.<br>**Automatic Frequency Control (AFC)**<br>The AX5045 features an automatic frequency tra|||cking|�f�|TRKRFFREQ<br>224<br>�fXTAL<br>(eq. 1)|||



The AX5045 features an automatic frequency tracking loop which is capable of tracking the transmitter frequency within the RX filter band width. On top of that the AX5045 has a frequency tracking register TRKRFFREQ to synchronize the receiver frequency to a carrier signal. For AFC adjustment, the frequency offset can be computed with the following formula: 

The pull−in range of the AFC can be programmed with the MAXRFOFFSET Registers. 

## **PWRMODE Register** 

The PWRMODE register controls, which parts of the chip are operating. 

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**AX5045** 

## **Table 22. PWRMODE REGISTER** 

|**PWRMODE Register**|**Name**|**Description**|
|---|---|---|
|0000|POWERDOWN|All digital and analog functions, except the register file, are disabled. The core<br>supply voltages are switched off to conserve leakage power. Register contents<br>are preserved and accessible registers via SPI, but at a slower speed.<br>Access to the FIFO is not possible and the contents are not preserved. POW-<br>ERDOWN mode is only entered once the FIFO is empty.|
|0001|DEEPSLEEP|AX5045 is fully turned off. All digital and analog functions are disabled. All reg-<br>ister contents are lost.<br>To leave DEEPSLEEP mode the pin SEL has to be pulled low. This will initiate<br>startup and reset of the AX5045. Then the MISO line should be polled, as it will<br>be held low during initialization and will rise to high at the end of the initializa-<br>tion, when the chip becomes ready for operation.|
|0101|STANDBY|The crystal oscillator and the reference are powered on; receiver and transmit-<br>ter are off. Register contents are preserved and accessible registers via SPI.<br>Access to the FIFO is not possible and the contents are not preserved.<br>STANDBY is only entered once the FIFO is empty|
|0111|FIFO|The reference is powered on. Register contents are preserved and accessible<br>registers via SPI.<br>Access to the FIFO is possible and the contents are preserved.|
|1000|SYNTHRX|The synthesizer is running on the receive frequency. Transmitter and receiver<br>are still off. This mode is used to let the synthesizer settle on the correct fre-<br>quency for receive.|
|1001|FULLRX|Synthesizer and receiver are running.|
|1011|WOR|Receiver wakeup−on−radio mode.<br>The mode the same as POWERDOWN, but the 640 Hz internal low power<br>oscillator is running.|
|1100|SYNTHTX|The synthesizer is running on the transmit frequency. Transmitter and receiver<br>are still off. This mode is used to let the synthesizer settle on the correct fre-<br>quency for transmit.|
|1101|FULLTX|Synthesizer and transmitter are running. Do not switch into this mode before<br>the synthesizer has completely settled on the transmit frequency (in SYNTHTX<br>mode), otherwise spurious spectral transmissions will occur.|



For the corresponding currents see Table 3. 

**Table 23. A TYPICAL PWRMODE SEQUENCE FOR A TRANSMIT SESSION** 

|**Step**|**PWRMODE**|**Remarks**|
|---|---|---|
|1|POWERDOWN||
|2|STANDBY|The settling time is dominated by the crystal used, typical value 3ms.|
|3|FULLTX|Data transmission.|
|4|POWERDOWN||



## **Table 24. A TYPICAL PWRMODE SEQUENCE FOR A RECEIVE SESSION** 

|**Step**|**PWRMODE [3:0]**|**Remarks**|
|---|---|---|
|1|POWERDOWN||
|2|STANDBY|The settling time is dominated by the crystal used, typical value 3ms.|
|3|FULLTX|Data reception.|
|4|POWERDOWN||



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**18** 

**AX5045** 

## **Serial Peripheral Interface** 

The AX5045 can be programmed via a four wire serial interface according SPI using the pins CLK, MOSI, MISO and SEL. Registers for setting up the AX5045 are programmed via the serial peripheral interface in all device modes. 

When the interface signal SEL is pulled low, a configuration data stream is expected on the input signal pin MOSI, which is interpreted as D0...Dx, A0...Ax, R_N/W. Data read from the interface appears on MISO. 

Figure 4 shows a write/read access to the interface. The data stream is built of an address byte including read/write information and a data byte. Depending on the R_N/W bit and address bits A[6..0], data D[7..0] can be written via MOSI or read at the pin MISO. R_N/W = 0 means read mode, R_N/W = 1 means write mode. 

registers are at the beginning of the address space, i.e. at addresses less than 0x70. These registers can be accessed more efficiently using the short address form, which is detailed in Figure 4. 

Some registers are longer than 8 bits. These registers can be accessed more quickly than by reading and writing individual 8 bit parts. This is illustrated in Figure 6. Accesses are not limited by 16 bits either, reading and writing data bytes can be continued as long as desired. After each byte, the address counter is incremented by one. This access form works with both, short and long addresses. 

During the address phase of the access, the AX5045 outputs the most important status bits. This feature is designed to speed up the software decision on what to do in an interrupt handler. 

The status bits contain the following information: 

Most registers are 8 bits wide and accessed using the waveforms as detailed in Figure 5. The most important 

**Table 25. SPI STATUS BITS** 

|**SPI Bit Cell**|**Status**|**Meaning/Register Bit**|
|---|---|---|
|0|−|1 (when transitioning out of deep sleep mode, this bit transitions from 0→ 1 when the power<br>becomes ready)|
|1|S14|PLL LOCK|
|2|S13|FIFO OVER|
|3|S12|FIFO OVER|
|4|S11|THRESHOLD FREE (FIFOFREE > FIFOTHRESH)|
|5|S10|THRESHOLD COUNT (FIFOCOUNT > FIFOTHRESH)|
|6|S9|FIFO FULL|
|7|S8|FIFO EMPTY|
|8|S7|PWRGOOD (not BROWNOUT)|
|9|S6|PWR INTERRUPT PENDING|
|10|S5|RADIO EVENT PENDING|
|11|S4|XTAL OSCILLATOR RUNNING|
|12|S3|WAKEUP INTERRUPT PENDING|
|13|S2|LPOSC INTERRUPT PENDING|
|14|S1|GPADC INTERRUPT PENDING|
|15|S0|internal|



21.Bit cells 8 −15 (S7 … S0) are only available in two address byte SPI access formats. 

_SPI Timing_ 

**==> picture [476 x 112] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tss Tck TchTcl Ts Th Tsh<br>SEL<br>CLK<br>MOSI R/ W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0<br>MISO S14 S13 S12 S11 S10 S9 S8 D7 D6 D5 D4 D3 D2 D1 D0<br>Tssd Tco Tssz<br>**----- End of picture text -----**<br>


**Figure 4. SPI 8 Bit Read/Write Access with Timing** 

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**19** 

**AX5045** 

**==> picture [462 x 48] intentionally omitted <==**

**----- Start of picture text -----**<br>
SEL<br>CLK<br>MOSI R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6     D5      D4      D3      D2      D1 D0<br>MISO S14     S13    S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 D7      D6      D5      D4 D3 D2 D1 D0<br>**----- End of picture text -----**<br>


**Figure 5. SPI 8 Bit Long Address Read/Write Access** 

**==> picture [463 x 48] intentionally omitted <==**

**----- Start of picture text -----**<br>
SEL<br>CLK<br>MOSI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6      D5 D4 D3 D2      D1 D0 D7 D6     D5      D4      D3      D2       D1 D0<br>MISO S14    S13    S12 S11 S10 S9 S8      D7 D6 D5 D4      D3      D2 D1 D0 D7      D6      D5      D4 D3 D2 D1 D0<br>**----- End of picture text -----**<br>


**Figure 6. SPI 16 Bit Long Read/Write Access** 

## **Wire Mode Interface** 

In wire mode the transmitted or received data are transferred from and to the AX5045 using the pins DATA and DCLK. DATA is an input when transmitting and an output when receiving. 

The direction (i.e. transmit or receive) can be chosen by programming the PWRMODE register. 

Wire mode offers two variants: synchronous or asynchronous. 

In synchronous wire mode the, the AX5045 always drives DCLK. Transmit data must be applied to DATA synchronously to DCLK, and receive data must be sampled synchronously to DCLK. Timing is given in Figure 7. In asynchronous wire mode, a low voltage RS232 type UART can be connected to DATA. DCLK is optional in this mode. The UART must be programmed to send two stop bits, but 

must be able to accept only one stop bit. Both the UART data rate and the AX5045 transmit and receive bit rate must match. The AX5045 synchronizes the RS232 signal to its internal transmission clock, by inserting or deleting a stop bit. 

Wiremode is also available in 4−FSK mode. The two bits that encode one symbol are serialized on the DATA pin. The PWRAMP pin can be used as a synchronization pin to allow symbol (dibit) boundaries to be reconstructed. Gray coding is used to reduce the number of bit errors in case of a wrong decision. Details can be found in the AX5045 Programming Manual. 

Registers for setting up the AX5045 are programmed via the serial peripheral interface (SPI). 

## _Wire Mode Timing_ 

See Figure 7. 

**==> picture [245 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tdck Tdch Tdcl Tds Tdh<br>DCLK (DCLKI=0)<br>DCLK (DCLKI=1)<br>DATA (TX)<br>DATA (RX)<br>Tdco<br>**----- End of picture text -----**<br>


**Figure 7. SPI 8 Bit Long Address Read/Write Access** 

## **General Purpose ADC (GPADC)** 

The AX5045 features a general purpose ADC. The ADC input pins are GPADC1 and GPADC2. The ADC converts the voltage difference applied between pins GPADC1 and GPADC2. If pin GPADC2 is left floating, the ADC converts the difference between an internally generated value of 800 mV and the voltage applied at pin GPADC1. 

The GPADC can only be used if the receiver is disabled. To enable the GPADC write 1 to the ENA bit in the GPADCCTRL register. To start a single conversion, write 1 to the BUSY bit in the GPADCCTRL register. Then wait for the BUSY bit to clear, or the GPADC Interrupt to be asserted. 

The GPADC Interrupt is cleared by reading the result register GPADCVALUE. 

If continuous sampling is desired, set the CONT bit in register GPADCCTRL. The desired sampling rate can be specified in the GPADCPERIOD register. 

## **�� DAC** 

One digital Pin (ANTSEL or PWRAMP) may be used as a �� Digital−to−Analog Converter (DAC). A simple RC lowpass filter is needed to smooth the output. The DAC may be used to output RSSI, many demodulator variables, or a constant value under software control. 

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**20** 

**AX5045** 

## **REGISTER BANK DESCRIPTION** 

This section describes the bits of the register bank as reference. The registers are grouped by functional block to facilitate programming. Register details can be found in the AX5045 Programming Manual. 

An R in the retention column means that this register’s contents are not lost during power−down mode. 

_No checks are made whether the programmed combination of bits makes sense! Bit 0 is always the LSB._ NOTES: Whole registers or register bits marked as reserved should be kept at their default values. 

All addresses not documented here must not be accessed, neither in reading nor in writing. 

**Table 26. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**REVISION & INTERFACE PROBING**||||||||||||||
|000|REVISION|R|R|01000110||||SILICON|REV(7:0)||||Silicon Revision|
|001|SCRATCH|RW|R|11000101||||SCRAT|CH(7:0)||||Scratch Register|
|**OPER**|**ATING MODE**|||||||||||||
|002|PWRMODE|RW|R|011–0000|RST|XOEN|REFEN|WDS||PWRMO|DE(3:0)||Power Mode|
|**VOLTA**|**GE REGULATOR**|||||||||||||
|003|POWSTAT|R|R|––––––––|SSUM|SREF|SVREF|SVANA|SVMODEM|SBEVANA|SBEV<br>MODEM|SVIO|Power Management<br>Status|
|004|POWSTICKYSTAT|R|R|––––––––|SSSUM|SREF|SSVREF|SSVANA|SSVMODEM|SSBEVANA|SSBEV<br>MODEM|SSVIO|Power Management<br>Sticky Status|
|005|POWIRQMASK|RW|R|00000000|MPWRGOOD|MSREF|MSVREF|MSVANA|MSVMODEM|MSBEVANA|MSBEV<br>MODEM|MSVIO|Power Management<br>Interrupt Mask|
|**INTER**|**RUPT CONTROL**|||||||||||||
|006|IRQMASK1|RW|R|––000000|–|||I|RQMASK(14:8)||||IRQ Mask|
|007|IRQMASK0|RW|R|00000000||||IRQMA|SK(7:0)||||IRQ Mask|
|008|RADIO EVENT<br>MASK1|RW|R|–––––––0|–|–|–|–|–|–|–|RADIO<br>EVENT<br>MASK(8)|Radio Event Mask|
|009|RADIO EVENT<br>MASK0|RW|R|00000000||||RADIO EVEN|T MASK(7:0)||||Radio Event Mask|
|00A|IRQINVERSION1|RW|R|––000000|–|||IRQ|INVERSION(14|:8)|||IRQ Inversion|
|00B|IRQINVERSION0|RW|R|00000000||||IRQINVER|SION(7:0)||||IRQ Inversion|
|00C|IRQREQUEST1|R|R|––––––––|–|||IR|QREQUEST(14|:8)|||IRQ Request|
|00D|IRQREQUEST0|R|R|––––––––||||IRQREQU|EST(7:0)||||IRQ Request|
|00E|RADIO EVENT<br>REQ1|R||––––––––|–|–|–|–|–|–|–|RADIO<br>EVENT<br>REQ(8)|Radio Event Request|
|00F|RADIO EVENT<br>REQ0|R||––––––––||||RADIO EVE|NT REQ(7:0)||||Radio Event Request|
|**MODU**|**LATION & FRAMI**|**NG**||||||||||||
|010|MODULATION|RW|R|–––01000|–|–|–|RX HALF<br>SPEED||MODULAT|ION (3:0)||Modulation|
|011|ENCODING1|RW|R|–––−−−−0|–|–|–|–|–|–|–|ENC<br>NOSYNC|Encoder/Decoder<br>Settings|
|012|ENCODING0|RW|R|00000100|TI<br>WHITENING|ENC<br>SCRMODE|ENC SCR|POLY(1:0>|ENC MANCH|ENC SCRAM|ENC IN|V(1:0)|Encoder/Decoder<br>Settings|
|013|FRAMING|RW|R|–––−0000|FRMRX|–|–|–||FRMMODE (2:0|)|FABORT|Framing settings|
|014|CRCCFG|RW|R|–––−0000|–|–|–|–||CRCMODE (2:0|)|CRCNOIN|CRC settings|
|015|CRCINIT3|RW|R|11111111||||CRCINIT|(31:24)||||CRC Initialisation Data|
|016|CRCINIT2|RW|R|11111111||||CRCINIT|(23:16)||||CRC Initialisation Data|
|017|CRCINIT1|RW|R|11111111||||CRCINI|T (15:3)||||CRC Initialisation Data|
|018|CRCINIT0|RW|R|11111111||||CRCIN|IT (7:0)||||CRC Initialisation Data|



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**21** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**FORW**|**ARD ERROR CO**|**RRECTIO**|**N**|||||||||||
|019|FEC|RW|R|00000000|SHORT<br>MEM|RSTVI<br>TERBI|FEC NEG|FEC POS|FE|CINPSHIFT (2:|0)|FEC ENA|FEC (Viterbi)<br>Configuration|
|01A|FECSYNC|RW|R|01100010||||FECSY|NC (7:0)||||Interleaver<br>Synchronization<br>Threshold|
|01B|FECSTATUS|R|R|−−−−−−−−|FEC INV|||M|AXMETRIC (6:0|)|||FEC Status|
|**STATU**|**S**|||||||||||||
|01C|RADIOSTATE|R|−|––––0000|–|–|–|–||RADIOST|ATE (3:0)||Radio<br>Controller State|
|01D|XTALSTATUS|R|R|––––––––|–|–|–|–|–|–|–|XTAL RUN|Crystal Oscillator Status|
|**PIN CO**|**NFIGURATION**|||||||||||||
|020|PINSTATE|R|R|––––––––|–|–|PS PWR AMP|PS ANT SEL|PS IRQ|PS DATA|PS DCLK|PS SYS CLK|Pinstate|
|021|PINFUNCSYSC LK|RW|R|0––01000|PU SYSCLK|–|–|||PFSYSCLK(4:0)|||SYSCLK Pin Function|
|022|PINFUNCDCLK|RW|R|00–––100|PU DCLK|PI DCLK|–|–|–||PFDCLK(2:0)||DCLK Pin Function|
|023|PINFUNCDATA|RW|R|10–––111|PU DATA|PI DATA|–|–|–||PFDATA(2:0)||DATA Pin Function|
|024|PINFUNCIRQ|RW|R|00–––011|PU IRQ|PI IRQ|–|–|–||PFIRQ(2:0)||IRQ Pin Function|
|025|PINFUNCANTS EL|RW|R|00–––110|PU ANTSEL|PI ANTSEL|–|–|–||PFANTSEL(2:0)||ANTSEL Pin Function|
|026|PINFUNCPWR<br>AMP|RW|R|00––0110|PU PWRAMP|PI PWRAMP|–|–||PFPWRA|MP(3:0)||PWRAMP Pin Function|
|027|PWRAMP|RW|R|–––––––0|–|–|–|–|–|–|–|PWRAMP|PWRAMP Control|
|**FIFO**||||||||||||||
|028|FIFOSTAT|R|R|0–––––––|FIFO AUTO<br>COMMIT|–|FIFO FREE<br>THR|FIFO CNT<br>THR|FIFO OVER|FIFO UNDER|FIFO FULL|FIFO EMPTY|FIFO Control|
|||W|R||||||FIFOC|MD(5:0)||||
|029|FIFODATA|RW||––––––––||||FIFODA|TA(7:0)||||FIFO Data|
|02A|FIFOCOUNT1|R|R|–––––––0|–|–|–|–|–|–|–|FIFO<br>COUNT(8)|Number of Words<br>currently in FIFO|
|02B|FIFOCOUNT0|R|R|00000000||||FIFOCO|UNT(7:0)||||Number of Words<br>currently in FIFO|
|02C|FIFOFREE1|R|R|–––––––1|–|–|–|–|–|–|–|FIFO<br>FREE(8)|Number of Words that<br>can be written to FIFO|
|02D|FIFOFREE0|R|R|00000000||||FIFOFR|EE(7:0)||||Number of Words that<br>can be written to FIFO|
|02E|FIFOTHRESH1|RW|R|–––––––0|–|–|–|–|–|–|–|FIFO<br>THRESH(8)|FIFO Threshold|
|02F|FIFOTHRESH0|RW|R|00000000||||FIFOTHR|ESH(7:0)||||FIFO Threshold|
|**SYNTH**|**ESIZER**|||||||||||||
|030|PLLLOOP|RW|R|0–––1001|FREQB|–|–|–|DIRECT|FILT EN|FLT(|1:0)|PLL Loop Filter Settings|
|031|PLLCPI|RW|R|00001000||||PLL|CPI||||PLL Charge Pump<br>Current (Boosted)|
|032|PLLRANGINGA1|RW|R|00000001|STICKY<br>LOCK|PLL LOCK|RNGERR|RNG START|–|–|–|VCORA(8)|PLL Autoranging|
|033|PLLRANGINGA0|RW|R|00000000||||VCOR|A(7:0)||||PLL Autoranging|
|034|FREQA3|RW|R|00111001||||FREQA|(31:24)||||Synthesizer<br>Frequency|
|035|FREQA2|RW|R|00110100||||FREQA|(23:16)||||Synthesizer<br>Frequency|
|036|FREQA1|RW|R|11001100||||FREQ|A(15:8)||||Synthesizer<br>Frequency|
|037|FREQA0|RW|R|11001101||||FREQ|A(7:0)||||Synthesizer<br>Frequency|
|038|PLLLOOPBOOST|RW|R|0–––1011|FREQB|–|–|–|DIRECT|FILT EN|FLT(|1:0)|PLL Loop Filter<br>Settings (Boosted)|
|039|PLLCPIBOOST|RW|R|11001000||||PLL|CPI||||PLL Charge Pump<br>Current|



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**22** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**SYNTH**|**ESIZER**|||||||||||||
|03A|PLLRANGINGB1|RW|R|00000001|STICKY<br>LOCK|PLL LOCK|RNGERR|RNG START|–|–|–|VCORB(8)|PLL Autoranging|
|03B|PLLRANGINGB0|RW|R|00000000||||VCOR|B(7:0)||||PLL Autoranging|
|03C|FREQB3|RW|R|00111001||||FREQB|(31:24)||||Synthesizer<br>Frequency|
|03D|FREQB2|RW|R|00110100||||FREQB|(23:16)||||Synthesizer<br>Frequency|
|03E|FREQB1|RW|R|11001100||||FREQ|B(15:8)||||Synthesizer<br>Frequency|
|03F|FREQB0|RW|R|11001101||||FREQ|B(7:0)||||Synthesizer<br>Frequency|
|040|PLLVCODIV|RW|R|–––0000|–|–|–||RFDIV||REFDI|V(1:0)|PLL Divider Settings|
|**SIGNA**|**L STRENGTH**|||||||||||||
|041|RSSI|R|R|––––––––||||RSSI|(7:0)||||Received Signal Strength<br>Indicator|
|042|BGNDRSSI|RW|R|00000000||||BGNDR|SSI(7:0)||||Background RSSI|
|043|DIVERSITY|RW|R|––––––00|–|–|–|–|–|–|ANT SEL|DIV ENA|Antenna Diversity<br>Configuration|
|043|AGCCOUNTER|RW|R|−−−−−−−−||||AGCCOUN|TER (7:0)||||AGC Current Value|
|**RECEI**|**VER TRACKING**|||||||||||||
|045|TRKDATARATE 2|R|R|––––––––||||TRKDATAR|ATE(23:16)||||Datarate Tracking|
|046|TRKDATARATE 1|R|R|––––––––||||TRKDATAR|ATE(15:8)||||Datarate Tracking|
|047|TRKDATARATE 0|R|R|––––––––||||TRKDATA|RATE(7:0)||||Datarate Tracking|
|048|TRKAMPL1|R|R|––––––––||||TRKAMP|L (15:8)||||Amplitude Tracking|
|049|TRKAMPL0|R|R|––––––––||||TRKAM|PL (7:0)||||Amplitude Tracking|
|04A|TRKPHASE1|R|R|––––––––|–|–|–|–||TRKPHA|SE(11:8)||Phase Tracking|
|04B|TRKPHASE0|R|R|––––––––||||TRKPHA|SE (7:0)||||Phase Tracking|
|04D|TRKRFFREQ2|RW|R|––––––––|–|–|–|–||TRRFKFR|EQ(19:16)||RF Frequency Tracking|
|04E|TRKRFFREQ1|RW|R|––––––––||||TRRFKFR|EQ(15:8)||||RF Frequency Tracking|
|04F|TRKRFFREQ0|RW|R|––––––––||||TRRFKF|REQ(7:0)||||RF Frequency Tracking|
|050|TRKFREQ1|RW|R|––––––––||||TRKFRE|Q(15:8)||||Frequency Tracking|
|051|TRKFREQ0|RW|R|––––––––||||TRKFR|EQ(7:0)||||Frequency Tracking|
|052|TRKFSKDEMOD1|R|R|––––––––|–|–|||TRKFSKDE|MOD(13:8)|||FSK Demodulator<br>Tracking|
|053|TRKFSKDEMOD0|R|R|––––––––||||TRKFSKD|EMOD(7:0)||||FSK Demodulator<br>Tracking|
|054|TRKAFSKDE<br>MOD1|R|R|––––––––||||TRKAFSKD|EMOD(15:8)||||AFSK Demodulator<br>Tracking|
|055|TRKAFSKDE<br>MOD0|R|R|––––––––||||TRKAFSKD|EMOD(7:0)||||AFSK Demodulator<br>Tracking|
|**TIMER**||||||||||||||
|059|TIMER2|R|–|––––––––||||TIMER|(23:16)||||1MHz Timer|
|05A|TIMER1|R|–|––––––––||||TIMER|(15:8)||||1MHz Timer|
|05B|TIMER0|R|–|––––––––||||TIME|R(7:0)||||1MHz Timer|
|**WAKE**|**UP TIMER**|||||||||||||
|068|WAKEUPTIMER 1|R|R|––––––––||||WAKEUPTI|MER(15:8)||||Wakeup Timer|
|069|WAKEUPTIMER 0|R|R|––––––––||||WAKEUPT|IMER(7:0)||||Wakeup Timer|
|06A|WAKEUP1|RW|R|00000000||||WAKEU|P(15:8)||||Wakeup Time|
|06B|WAKEUP0|RW|R|00000000||||WAKE|UP(7:0)||||Wakeup Time|
|06C|WAKEUPFREQ 1|RW|R|00000000||||WAKEUPF|REQ(15:8)||||Wakeup Frequency|
|06D|WAKEUPFREQ 0|RW|R|00000000||||WAKEUPF|REQ(7:0)||||Wakeup Frequency|



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**23** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**WAKE**|**UP TIMER**|||||||||||||
|06E|WAKEUPXO<br>EARLY|RW|R|00000000||||WAKEUP|XOEARLY||||Wakeup Crystal<br>Oscillator Early|
|**DSPm**|**ode2**|||||||||||||
|06F|DSPMODESHREG|RW||––––––––||||DSPMOD|ESHREG||||DSPmode SPI Shift<br>Register Access|
|**PHYSICAL LAYER PARAMETERS**<br>**RECEIVER PARAMETERS**||||||||||||||
|100|IFFREQ1|RW|R|00010001||||IFFRE|Q(15:8)||||2ndLO / IF Frequency|
|101|IFFREQ0|RW|R|00100111||||IFFRE|Q(7:0)||||2ndLO / IF Frequency|
|102|DECIMATION1|RW|R|––––––00|–|–|–|–|–|–|DECIMA|TION(9:8)|Decimation Factor|
|103|DECIMATION0|RW|R|00001101||||DECIMAT|ION(7:0)||||Decimation Factor|
|104|RXDATARATE2|RW|R|00000000||||RXDATAR|ATE(23:16)||||Receiver Datarate|
|105|RXDATARATE1|RW|R|00111101||||RXDATAR|ATE(15:8)||||Receiver Datarate|
|106|RXDATARATE0|RW|R|10001010||||RXDATAR|ATE(7:0)||||Receiver Datarate|
|107|MAXDROFFSET2|RW|R|00000000||||MAXDROFF|SET(23:16)||||Maximum Receiver<br>Datarate Offset|
|108|MAXDROFFSET1|RW|R|00000000||||MAXDROF|FSET(15:8)||||Maximum Receiver<br>Datarate Offset|
|109|MAXDROFFSET0|RW|R|10011110||||MAXDROF|FSET(7:0)||||Maximum Receiver<br>Datarate Offset|
|10A|MAXRFOFFSET2|RW|R|0–––0000|FREQ<br>OESS|–|–|–||MAXRFOFF|SET(19:16)||Maximum Receiver RF<br>Offset|
|10B|MAXRFOFFSET1|RW|R|00010110||||MAXRFOF|FSET(15:8)||||Maximum Receiver RF<br>Offset|
|10C|MAXRFOFFSET0|RW|R|10000111||||MAXRFOF|FSET(7:0)||||Maximum Receiver RF<br>Offset|
|10D|FSKDMAX1|RW|R|00000000||||FSKDEVM|AX(15:8)||||Four FSK Rx<br>Deviation|
|10E|FSKDMAX0|RW|R|10000000||||FSKDEV|MAX(7:0)||||Four FSK Rx<br>Deviation|
|10F|FSKDMIN1|RW|R|11111111||||FSKDEV|MIN(15:8)||||Four FSK Rx<br>Deviation|
|110|FSKDMIN0|RW|R|10000000||||FSKDEV|MIN(7:0)||||Four FSK Rx<br>Deviation|
|111|AFSKSPACE1|RW|R|––––0000|–|–|–|–||AFSKSPA|CE(11:8)||AFSK Space (0)<br>Frequency|
|112|AFSKSPACE0|RW|R|01000000||||AFSKSP|ACE(7:0)||||AFSK Space (0)<br>Frequency|
|113|AFSKMARK1|RW|R|––––0000|–|–|–|–||AFSKMA|RK(11:8)||AFSK Mark (1)<br>Frequency|
|114|AFSKMARK0|RW|R|01110101||||AFSKMA|RK(7:0)||||AFSK Mark (1)<br>Frequency|
|115|AFSKCTRL|RW|R|–––00100|–|–|–||A|FSKSHIFT0(4:|0)||AFSK Control|
|116|AMPLFILTER|RW|R|––––0000|–|–|–|–||AMPLFIL|TER(3:0)||Amplitude Filter|
|117|RFZIGZAGAMPL|RW|R|0000000||ZIGZAGAM|PLEXP(3:0)|||ZIGZAGAMP|LMANT(3:0)||RF Zigzag Scanner<br>Amplitude Exponent and<br>Mantissa|
|118|RFZIGZAGFREQ|RW|R|0000000||||ZIGZAGF|REQ(7:0)||||RF Zigzag Scanner<br>Amplitude Exponent and<br>Mantissa|
|119|RFFREQUENCY<br>LEAK|RW|R|–––00000|–|–|–||RFFR|EQUENCYLEA|K[4:0]||RF Frequency Recovery<br>Loop Leakiness|
|11A|FREQUENCY<br>LEAK|RW|R|0–––0000|PH<br>HALF<br>ACC|–|–|–||||FREQUENCY<br>LEAK[3:0]|Baseband Frequency<br>Recovery Loop<br>Leakiness|
|11B|RXPARAMSETS|RW|R|00000000|RXPS|3(1:0)|RXPS|2(1:0)|RXPS|1(1:0)|RXPS|0(1:0)|Receiver Parameter Set<br>Indirection|



**www.onsemi.com** 

**24** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**RECEI**|**VER PARAMETE**|**RS**||||||||||||
|11C|RXPARAMCUR<br>SET|R|R|––––––––|–|–|–|RXSI(2)|RXSN|(1:0)|RXS|I(1:0)|Receiver Parameter<br>Current Set|
|11D|RSSIIRQTHRESH|RW|R|0000000||||RSSIIRQTH|RESH(7:0)||||RSSI Interrupt Threshold|
|11E|RSSIIRQDIR|RW|R|–––––––0|–|–|–|–|–|–|–|RSSIIRQDIR|RSSI Interrupt Threshold<br>Direction|
|**RECEI**|**VER PARAMETE**|**R SET 0**||||||||||||
|120|AGCTARGET0|RW|R|01110110||||AGCTAR|GET0(7:0)||||AGC Target|
|121|AGCINCREASE0|RW|R|10110100||A|GCDECAY0(4:0|)||A|GCMINDA0(2:|0)|AGC Gain Increase<br>Settings|
|122|AGCREDUCE0|RW|R|00100000||A|GCATTACK0(4:|0)||A|GCMAXDA0(2:|0)|AGC Gain Reduce<br>Settings|
|123|AGCAHYST0|RW|R|–––––000|−|−|−|−|−|A|GCAHYST0(2:|0)|AGC Digital Threshold<br>Range|
|124|TIMEGAIN0|RW|R|11111000||TIMEG|AIN0M|||TIMEG|AIN0E||Timing Gain|
|125|DRGAIN0|RW|R|11110010||DRGA|IN0M|||DRG|AIN0E||Data Rate Gain|
|126|PHASEGAIN0|RW|R|11––0011|FILTERI|DX0(1:0)|–|–||PHASEG|AIN0(3:0)||Filter Index, Phase Gain|
|127|FREQGAINA0|RW|R|00001111|FREQ LIM0|FREQ<br>MODULO0|FREQ<br>HALFMOD0|FREQ AMPL<br>GATE0||FREQGA|INA0(3:0)||Frequency Gain A|
|128|FREQGAINB0|RW|R|00–11111|FREQ<br>FREEZE0|FREQ AVG0|–||F|REQGAINB0(4:|0)||Frequency Gain B|
|129|FREQGAINC0|RW|R|–––01010|–|–|–||F|REQGAINC0(4:|0)||Frequency Gain C|
|12A|FREQGAIND0|RW|R|0––01010|RFFREQ<br>FREEZE0|–|–||F|REQGAIND0(4:|0)||Frequency Gain D|
|12B|AMPLGAIN0|RW|R|01––0110|AMPL AVG|AMPL AGC|–|–||AMPLG|AIN0(3:0)||Amplitude Gain|
|12C|FREQDEV10|RW|R|––––0000|–|–|–|–||FREQDE|V0(11:8)||Receiver Frequency<br>Deviation|
|12D|FREQDEV00|RW|R|00100000||||FREQD|EV0(7:0)||||Receiver Frequency<br>Deviation|
|12E|FOURFSK0|RW|R|–––10110|–|–|–|DEV<br>UPDATE0||DEVDEC|AY0(3:0)||Four FSK Control|
|12F|BBOFFSRES0|RW|R|10001000||RESINT|B0(3:0)|||RESINT|A0(3:0)||Baseband Offset<br>Compensation Resistors|
|**RECEI**|**VER PARAMETE**|**R SET 1**||||||||||||
|130|AGCTARGET1|RW|R|01110110||||AGCTAR|GET1(7:0)||||AGC Target|
|131|AGCINCREASE1|RW|R|10110100||A|GCDECAY1(4:0|)||A|GCMINDA1(2:|0)|AGC Gain Increase<br>Settings|
|132|AGCREDUCE1|RW|R|00100000||A|GCATTACK1(4:|0)||A|GCMAXDA1(2:|0)|AGC Gain Reduce<br>Settings|
|133|AGCAHYST1|RW|R|–––––000|–|–|–|–|–|A|GCAHYST1(2:|0)|AGC Digital Threshold<br>Range|
|134|TIMEGAIN1|RW|R|11110110||TIMEG|AIN1M|||TIMEG|AIN1E||Timing Gain|
|135|DRGAIN1|RW|R|11110001||DRGA|IN1M|||DRG|AIN1E||Data Rate Gain|
|136|PHASEGAIN1|RW|R|11––0011|FILTERI|DX1(1:0)|–|–||PHASEG|AIN1(3:0)||Filter Index, Phase Gain|
|137|FREQGAINA1|RW|R|00001111|FREQ LIM1|FREQ<br>MODULO1|FREQ<br>HALFMOD1|FREQ AMPL<br>GATE1||FREQGA|INA1(3:0)||Frequency Gain A|
|138|FREQGAINB1|RW|R|00–11111|FREQ<br>FREEZE1|FREQ AVG1|–||F|REQGAINB1(4:|0)||Frequency Gain B|
|139|FREQGAINC1|RW|R|–––01011|–|–|–||F|REQGAINC1(4:|0)||Frequency Gain C|
|13A|FREQGAIND1|RW|R|0––01011|RFFREQ<br>FREEZE1|–|–||F|REQGAIND1(4:|0)||Frequency Gain D|
|13B|AMPLGAIN1|RW|R|01––0110|AMPL AVG1|AMPL1 AGC1|–|–||AMPLG|AIN1(3:0)||Amplitude Gain|
|13C|FREQDEV11|RW|R|––––0000|–|–|–|–||FREQDE|V1(11:8)||Receiver Frequency<br>Deviation|
|13D|FREQDEV01|RW|R|00100000||||FREQD|EV1(7:0)||||Receiver Frequency<br>Deviation|



**www.onsemi.com** 

**25** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**RECEI**|**VER PARAMETE**|**R SET 1**||||||||||||
|13E|FOURFSK1|RW|R|–––11000|–|–|–|DEV<br>UPDATE1||DEVDEC|AY1(3:0)||Four FSK Control|
|13F|BBOFFSRES1|RW|R|10001000||RESINT|B1(3:0)|||RESINT|A1(3:0)||Baseband Offset<br>Compensation Resistors|
|**RECEI**|**VER PARAMETE**|**R SET 2**||||||||||||
|140|AGCTARGET2|RW|R|01110110||||AGCTAR|GET2(7:0)||||AGC Target|
|141|AGCINCREASE2|RW|R|10110100||A|GCDECAY2(4:0|)||A|GCMINDA2(2:0|)|AGC Gain Increase<br>Settings|
|142|AGCREDUCE2|RW|R|00100000||A|GCATTACK2(4:|0)||A|GCMAXDA2(2:|0)|AGC Gain Reduce<br>Settings|
|143|AGCAHYST2|RW|R|–––––000|−|−|−|−|−|A|GCAHYST2(2:|0)|AGC Digital<br>Threshold Range|
|144|TIMEGAIN2|RW|R|11110101||TIMEG|AIN2M|||TIMEG|AIN2E||Timing Gain|
|145|DRGAIN2|RW|R|11110000||DRGA|IN2M|||DRG|AIN2E||Data Rate Gain|
|146|PHASEGAIN2|RW|R|11––0011|FILTERI|DX2(1:0)|–|–||PHASEG|AIN2(3:0)||Filter Index, Phase Gain|
|147|FREQGAINA2|RW|R|00001111|FREQ LIM2|FREQ<br>MODULO2|FREQ<br>HALFMOD2|FREQ AMPL<br>GATE2||FREQGA|INA2(3:0)||Frequency Gain A|
|148|FREQGAINB2|RW|R|00–11111|FREQ<br>FREEZE2|FREQ AVG2|–||F|REQGAINB2(4:|0)||Frequency Gain B|
|149|FREQGAINC2|RW|R|–––01101|–|–|–||F|REQGAINC2(4:|0)||Frequency Gain C|
|14A|FREQGAIND2|RW|R|0––01101|RFFREQ<br>FREEZE2|–|–||F|REQGAIND2(4:|0)||Frequency Gain D|
|14B|AMPLGAIN2|RW|R|01––0110|AMPL AVG2|AMPL AGC2|–|–||AMPLGA|IN2(3:0)||Amplitude Gain|
|14C|FREQDEV12|RW|R|––––0000|–|–|–|–||FREQDE|V2(11:8)||Receiver Frequency<br>Deviation|
|14D|FREQDEV02|RW|R|00100000||||FREQD|EV2(7:0)||||Receiver Frequency<br>Deviation|
|14E|FOURFSK2|RW|R|–––11010|–|–|–|DEV<br>UPDATE2||DEVDEC|AY2(3:0)||Four FSK Control|
|14F|BBOFFSRES2|RW|R|10001000||RESINT|B2(3:0)|||RESINT|A2(3:0)||Baseband Offset<br>Compensation Resistors|
|**RECEI**|**VER PARAMETE**|**R SET 3**||||||||||||
|160|MODCFGF|RW|R|–––––000|–|–|–|–|–|F|REQ SHAPE(2:|0)|Modulator<br>Configuration F|
|161|FSKDEV2|RW|R|00000000||||FSKDE|V(23:16)||||FSK Frequency<br>Deviation|
|162|FSKDEV1|RW|R|00001010||||FSKDE|V(15:8)||||FSK Frequency<br>Deviation|
|163|FSKDEV0|RW|R|00111101||||FSKDE|V(7:0)||||FSK Frequency<br>Deviation|
|164|MODCFGA|RW|R|0000–101|BROWN<br>GATE|PTTLCK<br>GATE|SLOW|RAMP|–|AMPL SHAPE|TX SE|TX DIFF|Modulator<br>Configuration A|
|165|TXRATE2|RW|R|00000000||||TXRATE|(23:16)||||Transmitter Bitrate|
|166|TXRATE1|RW|R|00101000||||TXRAT|E(15:8)||||Transmitter Bitrate|
|167|TXRATE0|RW|R|11110110||||TXRAT|E(7:0)||||Transmitter Bitrate|
|168|TXPWRCOEFF A1|RW|R|00000000||||TXPWRCO|EFFA(15:8)||||Transmitter Predistortion<br>Coefficient A|
|169|TXPWRCOEFF A0|RW|R|00000000||||TXPWRCO|EFFA(7:0)||||Transmitter Predistortion<br>Coefficient A|
|16A|TXPWRCOEFF B1|RW|R|00001111||||TXPWRCO|EFFB(15:8)||||Transmitter Predistortion<br>Coefficient B|
|16B|TXPWRCOEFF B0|RW|R|11111111||||TXPWRCO|EFFB(7:0)||||Transmitter Predistortion<br>Coefficient B|
|16C|TXPWRCOEFF C1|RW|R|00000000||||TXPWRCO|EFFC(15:8)||||Transmitter Predistortion<br>Coefficient C|
|16D|TXPWRCOEFF C0|RW|R|00000000||||TXPWRCO|EFFC(7:0)||||Transmitter Predistortion<br>Coefficient C|



**www.onsemi.com** 

**26** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**RECEI**|**VER PARAMETE**|**R SET 3**||||||||||||
|16E|TXPWRCOEFFD1|RW|R|00000000||||TXPWRCO|EFFD(15:8)||||Transmitter Predistortion<br>Coefficient D|
|16F|TXPWRCOEFFD0|RW|R|00000000||||TXPWRCO|EFFD(7:0)||||Transmitter Predistortion<br>Coefficient D|
|170|TXPWRCOEFFE1|RW|R|00000000||||TXPWRCO|EFFE(15:8)||||Transmitter Predistortion<br>Coefficient E|
|171|TXPWRCOEFFE0|RW|R|00000000||||TXPWRCO|EFFE(7:0)||||Transmitter Predistortion<br>Coefficient E|
|172|TXCLKDIV|RW|R|–––00000|–|–|–|TXHALF<br>SPEED|TXIN|TERP|TXCL|KDIV|Transmitter Clock<br>Divider|
|173|TXCLKDIV|RW|R|–––00000|–|–|–|–|–|–|MSH|APE|Transmitter Amplitude<br>Shaping|
|175|TXCONTROL|||||||unu|sed|||||
|176|TXMISC|RW|R|00000000|–|TXREGSNK|TXSTG2|TXSTG3|DACDISABLE|DACTESTEN|DACTR|IM (2:0)||
|**PLL PA**|**RAMETERS**|||||||||||||
|180|PLLVCOI|RW|R|–––––011|–|–|–|–|–||VCOI(2:0)||VCO Current|
|182|PLLLOCKDET|RW|R|–––––011|LOCKDET|DLYR(1:0)|–|–|–|LOCK DET<br>DLYM|LOCKDE|TDLY(1:0)|PLL Lock Detect<br>Delay|
|183|PLLRNGCFG|RW|R|––000011|–|–|PL|LRNGMODE(2:|0)|P|LLRNGCLK(2:0|)|PLL Ranging<br>Configuration|
|184|PLLDITHER|RW|R|00–10111|DTX|DRX|–||M|AGNITUDE(4:0|)||PLL Dither|
|**BASEB**|**AND**|||||||||||||
|188|BBTUNE|RW|R|–––01001|–|–|–|BB TUNE<br>RUN||BBTUN|E(3:0)||Baseband Tuning|
|189|BBOFFSCAP|RW|R|–111–111|–||CAP INT B(2:0)||–||CAP INT A(2:0)||Baseband Offset<br>Compensation<br>Capacitors|
|190|ADCCLK|RW|R|–0111100||||CLKFREQ(4:0)|||CLKM|UX(1:0)|SAR ADC Clock Settings|
|191|ADCMISC|RW|R|–––––––0|–|–|–|–|–|–|–|SKIP CALIB|SAR ADC Miscellaneous<br>Settings|
|192|ADCSPARE|RW|R|––––––00|–|–|–|–|–|–|ADCSPA|RE(1:0)|SAR ADC Spare Bits for<br>Analog Settings|
|**MAC**<br>**PACKE**|**LAYER PARAMETERS**<br>**T FORMAT**|||||||||||||
|200|PKTADDRCFG|RW|R|001–0000|MSB FIRST|CRC SKIP<br>FIRST|FEC SYNC<br>DIS|–||ADDR P|OS(3:0)||Packet Address Config|
|201|PKTLENPOS|RW|R|00000000||LEN MSB|POS(3:0)|||LEN LSB|POS(3:0)||Packet Length Byte<br>Position|
|202|PKTLENBITS|RW|R|––––0000|–|–|–|–||LEN BI|TS(3:0)||Packet Length Significant<br>Bits|
|203|PKTLENOFFSET1|RW|R|–––00000|–|–|–||L|EN OFFSET(12:|8)||Packet Length Offset 1|
|204|PKTLENOFFSET0|RW|R|00000000||||LEN OFF|SET(7:0)||||Packet Length Offset 0|
|205|PKTMAXLEN|RW|R|––––0000|–|–|–|–||MAX LE|N(11:8)||Packet Maximum<br>Length 1|
|206|PKTMAXLEN0|RW|R|00000000||||MAX L|EN(7:0)||||Packet Maximum<br>Length 0|
|207|PKTADDR3|RW|R|00000000||||ADDR(|31:24)||||Packet Address 3|
|208|PKTADDR2|RW|R|00000000||||ADDR(|23:16)||||Packet Address 2|
|209|PKTADDR1|RW|R|00000000||||ADDR|(15:8)||||Packet Address 1|
|20A|PKTADDR0|RW|R|00000000||||ADDR|(7:0)||||Packet Address 0|
|20B|PKTADDRMASK3|RW|R|00000000||||ADDRMA|SK(31:24)||||Packet Address Mask 1|
|20C|PKTADDRMASK2|RW|R|00000000||||ADDRMA|SK(23:16)||||Packet Address Mask 0|
|20D|PKTADDRMASK1|RW|R|00000000||||ADDRMA|SK(15:8)||||Packet Address Mask 1|
|20E|PKTADDRMASK0|RW|R|00000000||||ADDRM|ASK(7:0)||||Packet Address Mask 0|



**www.onsemi.com** 

**27** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**PATTE**|**RN MATCH**|||||||||||||
|210|MATCH0APAT3|RW|R|00000000||||MATCH0A|PAT(31:24)||||Pattern Match Unit 0a,<br>Pattern|
|211|MATCH0APAT2|RW|R|00000000||||MATCH0A|PAT(23:16)||||Pattern Match Unit 0a,<br>Pattern|
|212|MATCH0APAT1|RW|R|00000000||||MATCH0A|PAT(15:8)||||Pattern Match Unit 0a,<br>Pattern|
|213|MATCH0APAT0|RW|R|00000000||||MATCH0|APAT(7:0)||||Pattern Match Unit 0a,<br>Pattern|
|214|MATCH0ALEN|RW|R|0––00000|MATCH0<br>RAW|–|–|||||MATCH0ALE<br>N(4:0)|Pattern Match Unit 0a,<br>Pattern Length|
|215|MATCH0AMIN|RW|R|–––00000|–|–|–|||||MATCH0AMI<br>N(4:0)|Pattern Match Unit 0a,<br>Minimum Match|
|216|MATCH0AMAX|RW|R|–––11111|–|–|–|||||MATCH0AMA<br>X(4:0)|Pattern Match Unit 0a,<br>Maximum Match|
|217|MATCH0BPAT3|RW|R|00000000||||MATCH0B|PAT(31:24)||||Pattern Match Unit 0b,<br>Pattern|
|218|MATCH0BPAT2|RW|R|00000000||||MATCH0B|PAT(23:16)||||Pattern Match Unit 0b,<br>Pattern|
|219|MATCH0BPAT1|RW|R|00000000||||MATCH0B|PAT(15:8)||||Pattern Match Unit 0b,<br>Pattern|
|21A|MATCH0BPAT0|RW|R|00000000||||MATCH0|BPAT(7:0)||||Pattern Match Unit 0b,<br>Pattern|
|21B|MATCH0BLEN|RW|R|–––00000|–|–|–|||||MATCH0BLE<br>N(4:0)|Pattern Match Unit 0b,<br>Pattern Length|
|21C|MATCH0BMIN|RW|R|–––00000|–|–|–|||||MATCH0BMI<br>N(4:0)|Pattern Match Unit 0b,<br>Minimum Match|
|21D|MATCH0BMAX|RW|R|–––11111|–|–|–|||||MATCH0BMA<br>X(4:0)|Pattern Match Unit 0b,<br>Maximum Match|
|220|MATCH1PAT1|RW|R|00000000||||MATCH1|PAT(15:8)||||Pattern Match Unit 1,<br>Pattern|
|221|MATCH1PAT0|RW|R|00000000||||MATCH1|PAT(7:0)||||Pattern Match Unit 1,<br>Pattern|
|222|MATCH1LEN|RW|R|0–––0000|MATCH1<br>RAW|–|–|–||MATCH1|LEN(3:0)||Pattern Match Unit 1,<br>Pattern Length|
|223|MATCH1MIN|RW|R|––––0000|–|–|–|–||MATCH1|MIN(3:0)||Pattern Match Unit 1,<br>Minimum Match|
|224|MATCH1MAX|RW|R|––––1111|–|–|–|–||MATCH1|MAX(3:0)||Pattern Match Unit 1,<br>Maximum Match|
|**PACKE**|**T CONTROLLER**|||||||||||||
|230|TMGTXBOOST|RW|R|00110010|TM|GTXBOOSTE(2|:0)||TM|GTXBOOSTM(4|:0)||Transmit PLL Boost Time|
|231|TMGTXSETTLE|RW|R|00001010|TM|GTXSETTLEE(|2:0)||TM|GTXSETTLEM(|4:0)||Transmit PLL (post<br>Boost) Settling Time|
|232|TMGRXBOOST|RW|R|00110010|TM|GRXBOOSTE(2|:0)||TM|GRXBOOSTM(|4:0)||Receive PLL Boost Time|
|233|TMGRXSETTLE|RW|R|00010100|TM|GRXSETTLEE(|2:0)||TM|GRXSETTLEM(|4:0)||Receive PLL (post<br>Boost) Settling Time|
|234|TMGRXOFFSA CQ|RW|R|01110011|TMG|RXOFFSACQE|(2:0)||TMG|RXOFFSACQM|(4:0)||Receive Baseband DC<br>Offset<br>Acquisition Time|
|235|TMGRXCOARS<br>EAGC|RW|R|00111001|TMGR|XCOARSEAGC|E(2:0)||TMGR|XCOARSEAGC|M(4:0)||Receive Coarse AGC<br>Time|
|236|TMGRXAGC|RW|R|00000000|T|MGRXAGCE(2:|0)||T|MGRXAGCM(4:|0)||Receiver AGC Settling<br>Time|
|237|TMGRXRSSI|RW|R|00000000|T|MGRXRSSIE(2:|0)||T|MGRXRSSIM(4:|0)||Receiver RSSI Settling<br>Time|
|238|TMGRXPREAM<br>BLE1|RW|R|00000000|TMGR|XPREAMBLE1|E(2:0)||TMGR|XPREAMBLE1|M(4:0)||Receiver Preamble 1<br>Timeout|
|239|TMGRXPREAM<br>BLE2|RW|R|00000000|TMGR|XPREAMBLE2|E(2:0)||TMGR|XPREAMBLE2|M(4:0)||Receiver Preamble 2<br>Timeout|
|23A|TMGRXPREAM<br>BLE3|RW|R|00000000|TMGR|XPREAMBLE3|E(2:0)||TMGR|XPREAMBLE3|M(4:0)||Receiver Preamble 3<br>Timeout|



**www.onsemi.com** 

**28** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**PACKE**|**T CONTROLLER**|||||||||||||
|23B|RSSIREFERENCE|RW|R|00000000||||RSSIREF|ERENCE||||RSSI Offset|
|23C|RSSIABSTHR|RW|R|00000000||||RSSIA|BSTHR||||RSSI Absolute Threshold|
|23D|BGNDRSSIGAIN|RW|R|––––0000|–|–|–|–||BGNDRSS|IGAIN(3:0)||Background RSSI<br>Averaging Time Constant|
|23E|BGNDRSSITHR|RW|R|––000000|–|–|||BGNDRSS|ITHR(5:0)|||Background RSSI<br>Relative Threshold|
|240|PKTCHUNKSIZE|RW|R|00000000||||PKTCHUN|KSIZE(7:0)||||Packet Chunk Size|
|241|PKTMISCFLAGS|RW|R|––000000|–|–|ADDL FEC<br>SYNCFLG|WOR MULTI<br>PKT|AGC SETTL<br>DET|BGND RSSI|RXAGC CLK|RXRSSI CLK|Packet Controller<br>Miscellaneous Flags|
|242|PKTSTOREFLAGS|RW|R|–0000000|–|ST ANT RSSI|ST CRCB|ST RSSI|ST DR|ST RFOFFS|ST FOFFS|ST TIMER|Packet Controller Store<br>Flags|
|243|PKTACCEPT<br>FLAGS|RW|R|––000000|–|–|ACCPT LRGP|ACCPT SZF|ACCPT<br>ADDRF|ACCPT CRCF|ACCPT ABRT|ACCPT<br>RESIDUE|Packet Controller Accept<br>Flags|
|**SPECIAL FUNCTIONS**<br>**GENERAL PURPOSE ADC**||||||||||||||
|300|GPADCCTRL|RW|R|––000000|BUSY|–|GPADC3|GPADC2|GPADC1|GPADC13|CONT|CH ISOL|General Purpose ADC<br>Control|
|301|GPADCPERIOD|RW|R|00111111||||GPADCPE|RIOD(7:0)||||GPADC Sampling Period|
|308|GPADC13VALUE1|R||––––––––|–|–|–|–|–|–|GPADC13V|ALUE(9:8)|GPADC13 Value|
|309|GPADC13VALUE0|R||––––––––||||GPADC13V|ALUE(7:0)||||GPADC13 Value|
|30A|GPADC1VALUE1|R||––––––––|–|–|–|–|–|–|GPADC1V|ALUE(9:8)|GPADC1 Value|
|30B|GPADC1VALUE0|R||––––––––||||GPADC1V|ALUE(7:0)||||GPADC1 Value|
|30C|GPADC2VALUE1|R||––––––––|–|–|–|–|–|–|GPADC2V|ALUE(9:8)|GPADC2 Value|
|30D|GPADC2VALUE0|R||––––––––||||GPADC2V|ALUE(7:0)||||GPADC2 Value|
|30E|GPADC3VALUE1|R||––––––––|–|–|–|–|–|–|GPADC3V|ALUE(9:8)|GPADC3 Value|
|30F|GPADC3VALUE0|R||––––––––||||GPADC3V|ALUE(7:0)||||GPADC3 Value|
|**LOW P**|**OWER OSCILLA**|**TOR CA**|**LIBRATIO**|**N**||||||||||
|310|LPOSCCONFIG|RW|R|00000000|LPOC OSC<br>IVERT|−|LPOSC<br>CALIBR|LPOSC<br>CALIBF|LPOSC IRQR|LPOSC IRQF|LPOSC FAST|LPOSC ENA|Low Power Oscillator<br>Configuration|
|311|LPOSCSTATUS|R|R|––––––––|–|–|–|–|–|–|LPOSC IRQ|LPOSC EDGE|Low Power Oscillator<br>Status|
|312|LPOSCCLKMUX|RW|R|––––––00|–|–|–|–|–|–|LPOSCCL|KMUX(1:0)|LPOSC Reference<br>Frequency Divider|
|313|LPOSCKFILT1|RW|R|00100000||||LPOSCKF|ILT(15:8)||||Low Power Oscillator<br>Calibration Filter<br>Constant|
|314|LPOSCKFILT0|RW|R|11000100||||LPOSCK|FILT(7:0)||||Low Power Oscillator<br>Calibration<br>Filter Constant|
|315|LPOSCREF1|RW|R|01100001||||LPOSCR|EF(15:8)||||Low Power Oscillator<br>Calibration<br>Reference|
|316|LPOSCREF0|RW|R|10101000||||LPOSCR|EF(7:0)||||Low Power Oscillator<br>Calibration<br>Reference|
|317|LPOSCFREQ1|RW|R|00000000||||LPOSCF|REQ(9:2)||||Low Power Oscillator<br>Calibration<br>Frequency|
|318|LPOSCFREQ0|RW|R|0000––––||LPOSCFR|EQ(1:−2)||–|–|–|–|Low Power Oscillator<br>Calibration<br>Frequency|
|319|LPOSCPER1|RW||––––––––||||LPOSCP|ER(15:8)||||Low Power Oscillator<br>Calibration<br>Period|
|31A|LPOSCPER0|RW||––––––––||||LPOSCP|ER(7:0)||||Low Power Oscillator<br>Calibration<br>Period|



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**29** 

**AX5045** 

**Table 26. CONTROL REGISTER MAP** (continued) 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**DSP M**|**ODE INTERFACE**|||||||||||||
|320|DSPMODECFG|RW|R|00––––00|FSYNC DLY|DSP SPI|–|–|–|–|SYNC SO|URCE(1:0)|DSP Mode Setting|
|321|DSPMODESKIP1|RW|R|–0000000|–|SKIP AGC|SKIP RSSI|SKIP AFSK<br>DEMOD|SKIP FSK<br>DEMOD|SKIP<br>DATARATE|SKIP PHASE|SKIP FREQ|DSP Mode Skip 1|
|322|DSPMODESKIP0|RW|R|00000000|SKIP RF<br>FREQ|SKIP AMPL|SKIP SAMP<br>PHASE|SKIP SAMP<br>MAG|SKIP SAMP<br>ROTIQ|SKIP SAMP<br>IQ|SKIP BASE<br>BANDIQ|SKIP SOFT<br>SAMP|DSP Mode Skip 0|
|**DAC**||||||||||||||
|330|DACVALUE1|RW|R|––––0000|–|–|–|–||DACVAL|UE(11:8)||DAC Value|
|331|DACVALUE2|RW|R|00000000||||DACVA|LUE(7:0)||||DAC Value|
|332|DACCONFIG|RW|R|00––0000|DAC PW M|DAC CLK X2|–|–||DACINP|UT(3:0)||DAC Configuration|
|**RX CO**|**NTROL**|||||||||||||
|F00|SPAREOUT|RW|R|00000000|–|–|–|–||LNA|BIAS||LNA Bias|



## **APPLICATION INFORMATION** 

## **Certification** 

Customers using AX5045, as with any product containing a radio, have the responsibility to ensure, at a product level, that their usage of this product complies with regulatory requirements where it’s operated. 

ON Semiconductor makes an effort to create pre−compliant reference designs that customers can use or copy directly, however ON Semiconductor is not liable for customer’s failure to comply with regulatory obligations. 

## **Typical Application Diagrams** 

components have non−ideal effects, PCBs and soldering introduce additional parasitics, and variations in ground planes, antennas, etc, all influence the RF matching and RF performance and cannot be guaranteed or predicted in advance. 

To help lower risk, ON Semiconductor creates reference designs that customers can use as a starting point. However the customer should anticipate some fine tuning of the RF matching network for their system. All RF transceiver products are subject to these fundamental sensitivities. 

The following diagrams and any resulting component values or equations are provided as a starting point. Real 

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**30** 

**AX5045** 

_Using Separate RX/TX Connections_ 

**==> picture [473 x 307] intentionally omitted <==**

**----- Start of picture text -----**<br>
C1_TCXO<br>TCXO<br>C2_TCXO<br>Cchoke<br>Lchoke<br>CM 1 Lchoke<br>CSD LSD LM 1+L2 C2 C1<br>VDD_IO ANTSEL<br>VCHOKE PWRAMP<br>CSD<br>LSD CM 1LM 1+L2 C2 C1 TX_PTX_N AX5045 IRQNC<br>RX_P MOSI<br>CR2<br>RX_N MISO<br>VDD_ANA CLK<br>LR1<br>LR2<br>Ccm<br>Lshnt Lshnt<br>CR1<br>Cana<br>CLK16P<br>CLK16N GPADC2 GPADC1 NC VDD_IO NC<br>FILT NC NC DATA DCLK SYSCLK SEL<br>Microcontroller<br>**----- End of picture text -----**<br>


**Figure 8. Typical Application Diagram with Separate RX/TX Antennas without RX/TX Switch** 

Several external components are needed for the PA including the tuning components which are determined using the following equations for the load or antenna. 

The equations are used to determine the ideal values of C1, C2 and L2. The values of Lchoke and Cchoke are chosen. Vchoke, the regulator output or supply to the choke inductor, 

should be large for efficiency. Vchoke is designed to be a maximum of 2.8V. Lchoke is generally chosen to be large enough that it looks like a high impedence at the carrier frequency. 

The equations are: 

**==> picture [418 x 73] intentionally omitted <==**

**==> picture [436 x 27] intentionally omitted <==**

**==> picture [276 x 22] intentionally omitted <==**

Where: Pout = half the desired total output power in watts to account for the differential to single−ended combining Vsat = the saturation voltage of the switch transistor, ∼0.7 V. This can be adjusted to achieve the desired power QL = loaded quality factor of the series L2C2 (in the range 2−3) 

Vchoke = supply voltage on the choke inductor 

C1 = total cap at the PA output pin (The external C1 is reduced by the value of Cpa such that the total capacitance is the calculated value for C1) 

fo = center operation frequency 

Lchoke = RF choke inductor 

RL = load impedance needed to achieve desired output power 

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**31** 

**AX5045** 

To achieve higher output powers the RL valued tends to be lower. When this value is lower than the actual load (antenna) impedence, Rant, the matching network shown in Figure 8 can be used and the values are calculated as shown here. 

**==> picture [197 x 62] intentionally omitted <==**

In practice L2 and Lmatch could be combined into one inductor. The differential to single−ended conversion of the TX output is achieved via the Lsd and Csd components according to the following equations. 

**==> picture [183 x 24] intentionally omitted <==**

**==> picture [183 x 22] intentionally omitted <==**

where Rs is the single−ended impedence and Rd is the differential impedence ( 50 � and 100 � respectively). The differential impedence is 100 � due to each side of the output presenting 50 � to gnd, and thus 100 differentially. In practice the initial component values are determined using these equations, but are then adjusted slightly for optimal performance and to account for board parasitics. Adding additional filtering components between the antenna and the single−ended output may be necessary to reduce harmonic content. 

## **LNA Antenna Match** 

A single−ended to differential match for the LNA input shown above can be achieved using the following equations: 

**==> picture [168 x 58] intentionally omitted <==**

**==> picture [162 x 91] intentionally omitted <==**

**==> picture [174 x 23] intentionally omitted <==**

Where: RPLNA = the parallel input resistance of the LNA (not the series) ∼ 100 � 

- CPLNA = the parallel input capacitance of the LNA ∼ 

- (not the series) 1 pF 

- Re(ZL) = real part of load or antenna impedance 

- �m(ZL) = imaginary part of load or antenna impedance 

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**32** 

**AX5045** 

**==> picture [492 x 333] intentionally omitted <==**

**----- Start of picture text -----**<br>
Using Direct RX/TX Connection<br>See Figure 9.<br>C1_TCXO<br>TCXO<br>C2_TCXO<br>Cchoke<br>Lchoke<br>CM 1 Lchoke<br>CSD LSD LM 1+L2 C2 C1<br>VDD_IO ANTSEL<br>VCHOKE PWRAMP<br>CSD<br>LSD CM 1LM 1+L2 C2 C1 TX_PTX_N AX5045 IRQNC<br>RX_P MOSI<br>Ccm CR2<br>RX_N MISO<br>VDD_ANA CLK<br>LR1<br>LR2<br>Lshnt Lshnt<br>CR1<br>Cana<br>CLK16P<br>CLK16N GPADC2 GPADC1 NC VDD_IO NC<br>FILT NC NC DATA DCLK SYSCLK SEL<br>Microcontroller<br>**----- End of picture text -----**<br>


**Figure 9. Typical Application Diagram with Single−ended Antenna, Differential Internal PA, without RX/TX Switch** 

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**33** 

**AX5045** 

## **PA/LNA Co−match** 

A co−match for the PA and LNA is possible with some compromise to performance as shown in Figure 9. A large coupling capacitor Ccm is used to connect them together. The initial values of the PA and LNA input matching components are calculated using the previous equations. However, these are just the starting values as they will 

actually put a null right at the resonant frequency for the PA output. A compromise must then be made between the PA and LNA performance by tweaking the PA and LNA component values. Typically this can be done by adjusting L2 and C1, but adjusting C2, CM1, LR1, and CR1 may also be necessary to acheive best performance. 

## _Using Direct RX/TX Connection_ 

See Figure 10. 

**==> picture [416 x 279] intentionally omitted <==**

**----- Start of picture text -----**<br>
C1_TCXO<br>TCXO<br>C2_TCXO<br>Cchoke<br>Lchoke<br>CM1 Lchoke<br>CSD LSD LM1+L2 C2 C1<br>VDD_IO ANTSEL<br>VCHOKE PWRAMP<br>CSD<br>LSD CM1LM1+L2 C2 C1 TX_PTX_N AX5045 IRNC Q<br>RX_P MOSI<br>CR2<br>RX_N MIS O<br>VDD_ANA CLK<br>LR1<br>LR2<br>Ccm<br>Lshnt Lshnt<br>CR1<br>Cana<br>CLK16P<br>CLK16N GPADC2 GPADC1 NC VDD_IO NC<br>FILT NC NC DATA DCLK SYSCLK SEL<br>Microcontroller<br>**----- End of picture text -----**<br>


**Figure 10. Typical Application Diagram with RX/TX Switch** 

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**34** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [482 x 541] intentionally omitted <==**

**----- Start of picture text -----**<br>
QFN28 5x5, 0.5P<br>CASE 485EH<br>ISSUE A<br>BZ DATE 25 NOV 2015<br>1 28<br>SCALE 2:1<br>D A L L NOTES:<br>B 1. DIMENSIONS AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>PIN ONE<br>REFERENCE L1 3. DIMENSION b APPLIES TO PLATED<br>TERMINAL AND IS MEASURED BETWEEN<br>ÉÉ DETAIL A 0.15 AND 0.30MM FROM THE TERMINAL TIP.<br>at i a t U 4. COPLANARITY APPLIES TO THE EXPOSED<br>ALTERNATE TERMINAL<br>ÉÉ E CONSTRUCTIONS PAD AS WELL AS THE TERMINALS.<br>MILLIMETERS<br>DIM MIN MAX<br>0.05 C A 0.80 1.00<br>A1 0.00 0.05<br>of ct A3 0.20 REF<br>0.05 C TOP VIEW EXPOSED Cu MOLD CMPD b 0.20 0.30<br>D 5.00 BSC<br>ÉÉ D2 3.40 3.50<br>A E 5.00 BSC<br>0.10 C DETAIL B (A3) ÇÇ E2 3.40 3.50<br>A1 DETAIL B e 0.50 BSC<br>L y S ALTERNATE L 0.44 0.54<br>0.08 C CONSTRUCTION L1 −−− 0.15<br>NOTE 4 SIDE VIEW C SEATINGPLANE GENERIC<br>MARKING DIAGRAM*<br>DETAIL A<br>D2 1<br>8<br>XXXXXXXX<br>15 XXXXXXXX<br>28X L<br>AWLYYWW<br>E2<br>1<br>XXXXX = Specific Device Code<br>28 22 28X b A = Assembly Location<br>e WL = Wafer Lot<br>0.10 M C A B<br>ciel L eo | Ol fT YY = Year<br>BOTTOM VIEW 0.05 M C NOTE 3 WW = Work Week<br>| = Pb−Free Package<br>RECOMMENDED<br>SOLDERING FOOTPRINT* *This information is generic. Please refer<br>5.30 to device data sheet for actual part<br>28X marking.<br>3.60 0.69 Pb−Free indicator, “G” or microdot “ ”,<br>may or may not be present.<br>1<br>3.60 5.30<br>0.50 28X<br>PITCH te 0.32<br>DIMENSION: MILLIMETERS<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

## **DOCUMENT NUMBER: 98AON04198G** 

**DESCRIPTION: QFN28 5X5, 0.5P** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

## **PAGE 1 OF 1** 

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