AX-SIP-SFEU-API-1-01-TX30

## AX-SIP-SFEU, AX-SIP-SFEU-API 

## Ultra-Low Power, Ultra Compact, AT Command / API Controlled, Sigfox Verified Transceiver SiP for Up-Link and Down-Link 

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## **OVERVIEW** 

## **Circuit Description** 

AX−SIP−SFEU and AX−SIP−SFEU−API are ultra−low power, ultra compact System−in−Package (SiP) solutions for a node on the Sigfox network with both up− and down−link functionality. 

With a footprint of just 7 mm × 9 mm and conformal shielding, the AX−SIP−SFEU SiP, contains all the necessary components and firmware for transmit and receive operation on the European Sigfox network. No additional passive components or reference frequency providing parts are required on the customer’s PCB. A single−ended 50 Q antenna port is provided. 

The AX−SIP−SFEU connects to the customer product using a logic level RS232 UART. AT commands are used to send frames and configure radio parameters. 

The AX−SIP−SFEU−API variant is intended for customers wishing to write their own application software based on the AX−SIP−SF−LIB−1−GEVK library. 

## **Features** 

## Functionality and Ecosystem 

- Single package, zero external components, full Sigfox up−link and down−link functionality controlled by AT commands or API 

- The AX−SIP−SFEU and AX−SIP−SFEU−API SiPs are part of a whole development and product ecosystem available from ON Semiconductor for any Sigfox requirement. Other parts of the ecosystem include 

   - ♦ Ready to go development kit DVK−SIP−SFEU−[API]−1−GEVK including a 2 year Sigfox subscription 

- Sigfox[®] Verified 

## General Features 

- SIP38 9 mm × 7 mm package 

- Conformal shielding 

- Supply range 2.1 V − 3.6 V 

- −30°C to 85°C 

- Temperature sensor 

- Supply voltage measurements 

- 15 GPIO pins 

   - ♦ 6 GPIO pins with selectable voltage measure functionality, differential (1 V or 10 V range) or single ended (1 V range) with 10 bit resolution 

   - ♦ 2 GPIO pins with selectable sigma delta DAC output functionality 

   - ♦ 2 GPIO pins with selectable output clock 

   - ♦ 3 GPIO pins selectable as SPI master interface 

   - ♦ Integrated RX/TX switching with single−ended 50  antenna pin Q 

## Power Consumption 

- Ultra−low Power Consumption: 

   - ♦ Charge required to send a Sigfox OOB packet at nominal transmitter power (13 dBm typical at nominal temperature): 0.24 C 

   - ♦ Deep Sleep mode current: 180 nA 

   - ♦ Sleep mode current: 1.2 mM A 

   - ♦ Standby mode current: 0.55 mA 

## **Features** (Continued) 

- ♦ Continuous radio RX−mode at 869.525 MHz: 14 mA 

- ♦ Continuous radio TX−mode at 868.130 MHz: 45 mA @ nominal transmitter power (13 dBm) 

High Performance Narrow−band Sigfox RF Transceiver 

- Receiver 

   - ♦ Carrier frequency 869.525 MHz 

   - ♦ Data−rate 600 bps FSK 

   - ♦ Sensitivity 

      - −125 dBm @ 600 bps, 869.525 MHz, GFSK 

   - ♦ 0 dBm maximum input power 

- Transmitter 

   - ♦ Carrier frequency 868.13 MHz 

   - ♦ Data−rate 100 bps PSK 

   - ♦ High efficiency, high linearity integrated power amplifier 

   - ♦ Maximum output power 13 dBm 

   - ♦ Power level programmable in 1 dBm steps 

## **Applications** 

- Sigfox networks up−link and down−link 

Publication Order Number: **AX−SIP−SFEU/D** 

**1** 

© Semiconductor Components Industries, LLC, 2017 **October, 2018 − Rev. 2** 

**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **BLOCK DIAGRAM** 

**==> picture [406 x 533] intentionally omitted <==**

**----- Start of picture text -----**<br>
AX−SIP−SFEU / AX−SIP−SFEU−API<br>RF Synthesis<br>Receive<br>RX/TX<br>Switch and Communication<br>ANT<br>Antenna Controller<br>Interface<br>Transmit<br>UARTRX<br>UART<br>UARTTX<br>DAC<br>GPIO[14:0] GPIO<br>ADC CPU<br>RADIO_LED<br>Dedicated<br>CPU_LED<br>Status<br>TX_LED<br>Outputs<br>RX_LED<br>Program<br>Memory<br>Power Mode (FLASH)<br>RAM<br>Control<br>Sigfox identity (ID, PAC)<br>Sigfox compliant<br>application<br>(AX−SFEU only)<br>GND VDD_IO RESET_N<br>**----- End of picture text -----**<br>


**Figure 1. Functional Block Diagram of the AX−SIP−SFEU / AX−SIP−SFEU−API** 

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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **Table 1. PIN FUNCTION DESCRIPTIONS** 

|**Symbol**|**Pin(s)**|**Type**|**Description**|
|---|---|---|---|
|GND|1|P|Ground|
|GND|2|P|Ground|
|ANT|3|A|Single−ended 50�antenna input/output|
|GND|4|P|Ground|
|NC|5|N|Do not connect|
|GND|6|P|Ground|
|NC|7|N|Do not connect|
|NC|8|N|Do not connect|
|NC|9|N|Do not connect|
|GPIO11|10|I/O/PU|General purpose IO|
|GPIO10|11|I/O/PU|General purpose IO|
|GPIO8|12|I/O/PU|General purpose IO|
|GPIO7|13|I/O/PU|General purpose IO, selectable SPI functionality (MISO)|
|GPIO6|14|I/O/PU|General purpose IO, selectable SPI functionality (MOSI)|
|GPIO5|15|I/O/PU|General purpose IO, selectable SPI functionality (SCK)|
|GPIO4|16|I/O/PU|General purpose IO, selectable�� DAC functionality, selectable clock functionality|
|CPU_LED|17|O|CPU activity indicator|
|RADIO_LED|18|O|Radio activity indicator|
|GPIO9|19|I/O/PU|General purpose IO, wakeup from deep sleep|
|UARTTX|20|O|UART transmit|
|UARTRX|21|I/PU|UART receive|
|RX_LED/<br>DBG_DATA|22|O<br>I/O|Receive activity indicator in AX−SIP−SFEU.<br>Debugger data line in AX−SIP−SFEU−API.|
|TX_LED/<br>DBG_CLK|23|O<br>I|Transmit activity indicator in AX−SIP−SFEU.<br>Debugger clock line in AX−SIP−SFEU−API.|
|NC/<br>DBG_EN|24|PD<br>PD|Do not connect in AX−SIP−SFEU.<br>Debugger enable line in AX−SIP−SFEU−API.|
|RESET_N|25|I/PU|Optional reset pin. Internal pull−up resistor is permanently enabled, nevertheless<br>it is recommended to connect this pin to VDD_IO if it is not used.|
|GND|26|P|Ground|
|VDD_IO|27|P|Unregulated power supply|
|GPIO0|28|I/O/A/PU|General purpose IO, selectable ADC functionality, selectable�� DAC functionality,<br>selectable clock functionality|
|GPIO1|29|I/O/A/PU|General purpose IO, selectable ADC functionality|
|GPIO2|30|I/O/A/PU|General purpose IO, selectable ADC functionality|
|NC|31|N|Do not connect|
|NC|32|N|Do not connect|
|GPIO3|33|I/O/A/PU|General purpose IO, selectable ADC functionality|
|GPIO12|34|I/O/A/PU|General purpose IO, selectable ADC functionality|
|GPIO13|35|I/O/A/PU|General purpose IO, selectable ADC functionality|
|GPIO14|36|I/O/PU|General purpose IO|
|NC|37|N|Do not connect|
|NC|38|N|Do not connect|
|GND|Center pads|P|Ground on 6 center pads of SIP38, must be connected|



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## **AX−SIP−SFEU, AX−SIP−SFEU−API** 

A = analog input or input/output I = digital input signal O = digital output signal PU = pull−up I/O = digital input/output signal N = not to be connected P = power or ground PD = pull−down 

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible. Pins GPIO[3:0] and GPIO[13:12] must not be driven above VDD_IO, all other digital inputs are 5 V tolerant. All GPIO pins and UARTRX start up as input with pull−up. For explanations on how to use the GPIO pins, see chapter “AT Commands”. 

0 = pin drives low 1 = pin drives high Z = pin is high impedance input U = pin is input with pull−up A = pin is analog input T = pin is driven by clock or DAC 

**Table 2.** 

|**Table 2.**||
|---|---|
|**Pin**|**Possible GPIO Modes**|
|GPIO0|0, 1, Z, U, A, T|
|GPIO1|0, 1, Z, U, A|
|GPIO2|0, 1, Z, U, A|
|GPIO3|0, 1, Z, U, A|
|GPIO4|0, 1, Z, U, T|
|GPIO5|0, 1, Z, U|
|GPIO6|0, 1, Z, U|
|GPIO7|0, 1, Z, U|
|GPIO8|0, 1, Z, U|
|GPIO9|0, 1, Z, U|
|GPIO10|0, 1, Z, U|
|GPIO11|0, 1, Z, U|
|GPIO12|0, 1, Z, U, A|
|GPIO13|0, 1, Z, U, A|
|GPIO14|0, 1, Z, U|



## **Pinout Drawing** 

**==> picture [342 x 268] intentionally omitted <==**

**----- Start of picture text -----**<br>
38 37 36 35 34 33 32 31 30 29 28<br>GND 1 27 VIO<br>GND 2 26 GND<br>ANT 3 25 RESET_N<br>GND 4 24 NC/DBG_EN<br>AX−SIP−SFEU / AX−SIP−SFEU−API<br>NC 5 23 TXLED/DBG_CLK<br>GND 6 22 RXLED/DBG_DATA<br>NC 7 21 UARTRX<br>NC 8 20 UARTTX<br>9 10 11 12 13 14 15 16 17 18 19<br>NC NC GPIO14 GPIO13 GPIO12 GPIO3 NC NC GPIO2 GPIO1 GPIO0<br>NC GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 CPULED RADIOLED GPIO9<br>**----- End of picture text -----**<br>


Pins 22−24 have different functionalities in AT command and API versions, so for these pins AX−SIP−SFEU/AX−SIP−SFEU−API explanations are shown respectively. 

**Figure 2. Pinout Drawing (Top View)** 

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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **SPECIFICATIONS** 

## **Table 3. ABSOLUTE MAXIMUM RATINGS** 

|**Symbol**|**Description**|**Condition**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDD_IO|Supply voltage||−0.5|3.8|V|
|IDD|Supply current|||200|mA|
|Ptot|Total power consumption|||800|mW|
|Pi|Absolute maximum input power at receiver input|ANT pin in RX mode||10|dBm|
|II1|DC current into any pin except ANT||−10|10|mA|
|II2|DC current into pin ANT||−100|100|mA|
|IO|Output Current|||40|mA|
|Via|Input voltage ANT pin||−0.5|3.8|V|
||Input voltage digital pins||−0.5|5.5|V|
|Ves|Electrostatic handling|HBM|−2000|2000|V|
|Tamb|Operating temperature||−30|85|°C|
|Tstg|Storage temperature||−30|85|°C|
|Tj|Junction Temperature|||150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 

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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **DC Characteristics** 

## **Table 4. SUPPLIES** 

(Conditions for all current and charge values unless otherwise specified are for the DVK−SIP−SFEU−1−GEVK hardware configuration.) 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TAMB|Operational ambient temperature||−30|27|85|°C|
|VDDIO|I/O and voltage regulator supply<br>voltage||2.1|3.0|3.6|V|
|VDDIO R1|I/O voltage ramp for reset activation<br>(Note 2)|Ramp starts at VDD IO≤0.1 V|0.1|||V/ms|
|VDDIO R2|I/O voltage ramp for reset activation<br>(Note 2)|Ramp starts at 0.1 V<VDD IO<0.7 V|3.3|||V/ms|
|IDS|Deep sleep mode current|AT$P = 2||180||nA|
|ISLP|Sleep mode current|AT$P = 1||1.2||�A|
|ISTDBY|Standby mode current (Note 3)|||0.55||mA|
|IRX_CONT|Current consumption continuous RX|AT$SE||14||mA|
|QSFX_OOB_14|Charge to send a Sigfox out of band<br>message, nominal transmitter power<br>(Note 4)|AT$SO||0.24||C|
|QSFX_BIT_14|Charge to send a bit, nominal<br>transmitter power (Note 4)|AT$SB = 0||0.16||C|
|QSFX_BITDL_14|Charge to send a bit with downlink<br>receive, nominal transmitter power<br>(Note 4)|AT$SB = 0,1||0.44||C|
|QSFX_LFR_14|Charge to send the longest possible<br>Sigfox frame (12 byte), nominal<br>transmitter power (Note 4)|AT$SF = 00112233445566778899aabb||0.29||C|
|QSFX_LFRDL_14|Charge to send the longest possible<br>Sigfox frame (12 byte) with downlink<br>receive, nominal transmitter power<br>(Note 4)|AT$SF = 00112233445566778899aabb,1||0.57||C|
|ITXMOD14AVG|Modulated Transmitter Current<br>(Note 5)|Pout= 13 dBm; average||45||mA|



2. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset. 

3. 20 MHz Fast RC oscillator, voltage conditioning and supervisory circuit running. 

4. Power setting 14, which gives 13 dBm typical power at nominal temperature. 

5. Current consumption value is given for a matching network that is optimized for maximum power (setting 14, also nominal setting). 

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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **Typical Current Waveform** 

**Figure 3. Typical Current Waveform for a Maximum Length Frame with Downlink Receive at Nominal Transmitter Power** 

## **Battery Life Example** 

- 2 AAA Alkaline batteries in series 

- One OOB frame transmitter per day at nominal transmitter power (Pout = 13 dBm typical) 

      - Device in Sleep 

      - Neglecting battery self−discharge 

- Four maximum length frames with downlink receive per day at nominal transmitter power 

   - (Pout = 13 dBm typical) 

|2 AAA alkaline capacity|1500 mAh×3600 s/h|5400 C|
|---|---|---|
|Sleep charge per day|1.2µA×86400 s|0.10 C/day|
|OOB frame transmission||0.24 C/day|
|Frame transmission with downlink|4×0.57 C/day|2.28 C/day|
|Total Charge consumption||2.62 C/day|
|Battery life||5.6 Years|



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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **Table 5. LOGIC** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**DIGITAL INPUTS**|||||||
|VT+|Schmitt trigger low to high threshold point|VDD_IO = 3.3 V||1.55||V|
|VT−|Schmitt trigger high to low threshold point|||1.25||V|
|VIL|Input  voltage, low||||0.8|V|
|VIH|Input voltage, high||2.0|||V|
|VIPA|Input voltage range, GPIO[3:0] and GPIO[13:12]||−0.5||VDD_IO|V|
|VIPBC|Input voltage range, GPIO[9:4], UARTRX||−0.5||5.5|V|
|IL|Input leakage current||−10||10|�A|
|RPU|Programmable Pull−Up Resistance|||65||k�|
|**DIGITAL OUTPUTS**|||||||
|IOH|Output Current, high<br>GPIO[14:0], UARTTX, TXLED, RXLED, TXLED,<br>CPULED|VOH = 2.4 V|8|||mA|
|IOL|Output Current, low<br>GPIO[14:0], UARTTX, TXLED, RXLED, TXLED,<br>CPULED|VOL = 0.4 V|8|||mA|
|IOZ|Tri−state output leakage current||−10||10|�A|



## **AC Characteristics** 

## **Table 6. TRANSMITTER** 

(Conditions for transmitter specifications unless otherwise specified are for DVK−SIP−SFEU−1−GVK hardware configuration and at 868.130 MHz frequency.) 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|SBR|Signal bit rate|||100||bps|
|PTXmin|Lowest Transmitter output power (Note 6)|AT$CW=868130000,1,0||−1||dBm|
|PTXmax|Highest Transmitter output power (Note 6)|AT$CW=868130000,1,14||13||dBm|
|PTXstep|Programming step size output power|||1||dB|
|dTXtemp|Transmitter power variation vs. temperature|−30°C to +85°C||±0.8||dB|
|dTXVdd|Transmitter power variation vs. VDD_IO|2.1 to 3.6 V||±0.03||dB|
|PTXharm2|Emission @ 2nd harmonic|||−58||dBc|
|PTXharm3|Emission @ 3rd harmonic|||−80|||
|PTXharm4|Emission @ 4th harmonic|||−86|||



6. The output power of the AX−SIP−SFEU / AX−SIP−SFEU−API can be programmed in 1 dB steps, by changing transmitter power setting from 0 − 14. The lowest power setting is 0, which gives −1 dBm typical power at nominal temperature. The highest power setting is 14, which gives 13 dBm typical power at nominal temperature and close to 14 dBm typical power at minimum temperature. 

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**8** 

## **AX−SIP−SFEU, AX−SIP−SFEU−API** 

**Figure 4. Typical Spectrum with Harmonics at Nominal Output Power** 

## **Table 7. RECEIVER** 

(Conditions for receiver specifications unless otherwise specified are for DVK−SIP−SFEU−1−GEVK hardware configuration and at 869.525 MHz frequency.) 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|SBR|Signal bit rate|||600||bps|
|ISBER868|Sensitivity|Evaluated at BER > 10−3. AT command used:<br>AT$PN=4,5||−125||dBm|
|BLK2M−868|Blocking level at<br> ±2 MHz offset|Evaluated at BER > 10−3. Wanted signal is +3 dB above<br>the typical sensitivity, the blocker signal is CW.<br>AT command used: AT$PN=4,5.||−53||dBm|
|BLK10M−868|Blocking level at<br> ±10 MHz offset|Evaluated at BER > 10−3. Wanted signal is +3 dB above<br>the typical sensitivity, the blocker signal is CW.<br>AT command used: AT$PN=4,5.||−32||dBm|



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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **Table 8. ADC/TEMPERATURE SENSOR** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|ADCRES|ADC resolution|||10||Bits|
|VADCREF|ADC reference voltage||0.95|1|1.05|V|
|ZADC00|Input capacitance||||2.5|pF|
|DNL|Differential nonlinearity|||±1||LSB|
|INL|Integral nonlinearity|||±1||LSB|
|OFF|Offset|||3||LSB|
|GAIN_ERR|Gain error|||0.8||%|
|**ADC IN DIFFERENTIAL MODE**|||||||
|VABS_DIFF|Absolute voltages & common mode voltage in||0||VDD_IO|V|
||differential mode at each input||||||
|VFS_DIFF01|Full swing input for differential signals|Gain×1|−500||500|mV|
|VFS_DIFF10||Gain×10|−50||50|mV|
|**ADC IN SINGLE ENDED MODE**|||||||
|VMID_SE|Mid code input voltage in single ended mode|||0.5||V|
|VIN_SE00|Input voltage in single ended mode||0||VDD_IO|V|
|VFS_SE01|Full swing input for single ended signals|Gain×1|0||1|V|
|**TEMPERATURE SENSOR**|||||||
|TRNG|Temperature range|AT$T?|−30||85|°C|



## **COMMAND INTERFACE** 

## **Power Modes** 

## **General Information** 

The chapter “Command Interface” is a documentation of the AT−Command set for devices which do not have an API−interface. To see whether the device is capable of receiving AT−Commands, please refer to the table “Device Versions”. If the device has been shipped with the API−Interface, please refer to the SW manual and “apiexample” code delivered with AX−SIP−SF−LIB−1−GEVK for an introduction on how to setup a project and how to use the API−Interface. 

## **Serial Parameters: 9600, 8, N, 1** 

The AX−SIP−SFEU uses the UART (pins UARTTX, UARTRX) to communicate with a host and uses a bitrate of **9600 baud** , no parity, 8 data bits and one stop bit. 

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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## _Standby_ 

After Power−Up and after finishing a Sigfox transmission, AX−SIP−SFEU enters Standby mode. In Standby mode, AX−SIP−SFEU listens on the UART for commands from the host. Also, OOB frames are transmitted whenever the OOB timer fires. To conserve power, the AX−SIP−SFEU can be put into Sleep or turned off (Deep Sleep) completely. 

## _Sleep_ 

The command **AT$P=1** is used to put the AX−SIP−SFEU into Sleep mode. In this mode, only the wakeup timer for out−of−band messages is still running. To wake the AX−SIP−SFEU up from Sleep mode toggle the serial UARTRX pin, e.g. by sending a break (break is an RS232 framing violation, i.e. at least 10 bit durations low). When an Out of Band (OOB) message is due, AX−SIP−SFEU automatically wakes up to transmit the message, and then returns to Sleep mode. 

## _Deep Sleep_ 

In Deep Sleep mode, the AX−SIP−SFEU is completely turned off and only draws negligible leakage current. 

Deep Sleep mode can be activated with **AT$P=2** . To wake−up from Deep Sleep mode, GPIO9 is pulled to GND. 

When using Deep Sleep mode, keep two things in mind: Everything is turned off, timers are not running at all and all settings will be lost (use **AT$WR** to save settings to flash before entering Deep Sleep mode). Out−of−band messages will therefore not be sent. The pins states are frozen in Deep Sleep mode. The user must ensure that this will not result in condition which would draw a lot of current. 

## **AT Commands** 

## _Numerical Syntax_ 

hexdigit ::= [0−9A−Fa−f] Hexnum ::= “0x” hexdigit+ decnum ::= “0” | [1−9] [0−9]* octnum ::= “0” [0−7]+ binnum ::= “0b” [01]+ bit ::= [01] optnum ::= “−1” Frame ::= (hexdigit hexdigit)+ uint ::= hexnum | decnum | octnum | binnum uint_opt  ::= uint | optnum 

## _Command Syntax_ 

A command starts with ‘AT’ (everything is case sensitive!), continues with the actual command followed by parameters (if any) and ends with any kind of whitespace (space, tab, newline etc.) 

If incorrect syntax is detected (“parsing error”) all input is ignored up until the next whitespace character. 

Also note that any number can be entered in any format (Hexadecimal, Decimal, Octal and binary) by adding the corresponding prefix (‘0x’, ‘0’, ‘0b’). The only exception is the ‘Send Frame’ command (AT$SF) which expects a list of hexadecimal digits without any prefix. 

## _Return Codes_ 

A successful command execution is indicated by sending ‘OK’. If a command returns a value (e.g. by querying a register) only the value is returned. 

## _Examples_ 

Bold text is sent to AX−SIP−SFEU. 

## **AT$I=0** 

AX−SF 1.1−RC1 

Here, we execute command ‘I’ to query some general information. 

## **AT$SF=aabb1234** 

OK 

This sends a Sigfox frame containing {0xAA : 0xBB : 0x12 : 0x34} without waiting for a response telegram. 

## **AT$SF=0011223344,1** 

OK 

RX=AA BB CC DD 

This sends a Sigfox frame containing {0x00 : 0x11 : 0x22 : 0x33 : 0x44}, then waits for a downlink response telegram, which in this example contains {0xAA : 0xBB : 0xCC : 0xDD}. 

**AT$CB=0xAA,1** 

OK 

The ‘CB’ command sends out a continuous pattern of bits, in this case 0xAA = 0b10101010. 

## **AT$P=1** 

OK 

This transitions the device into sleep mode. Out−of−band transmissions will still be triggered. The UART is powered down. The device can be woken up by a low level on the UART signal, i.e. by sending break. 

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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

**Table 9. COMMANDS** 

|**Table 9. COMMANDS**|||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT|Dummy Command|Just returns ‘OK’ and does nothing else. Can be used to check<br>communication.|
|AT$SB=bit[,bit]|Send Bit|Send a bit status (0 or 1). Optional bit flag indicates if AX−SIP−SFEU<br>should receive a downlink frame.|
|AT$SF=frame[,bit]|Send Frame|Send payload data, 1 to 12 bytes. Optional bit flag indicates if<br>AX−SIP−SFEU should receive a downlink frame.|
|AT$SO|Manually send out of band<br>message|Send the out−of−band message.|
|AT$TR?|Get the transmit repeat|Returns the number of transmit repeats. Default: 2|
|AT$TR=?|Get transmit repeat range|Returns the allowed range of transmit repeats.|
|AT$TR=uint|Set transmit repeat|Sets the transmit repeat, sets only for transmit with downlink frame.|
|ATSuint?|Get Register|Query a specific configuration register’s value. See Table 10 “Registers”<br>for a list of registers.|
|ATSuint=int|Set Register|Change a configuration register.|
|ATSuint=?|Get Register Range|Returns the allowed range of the register values.|
|AT$IF=uint|Set TX Frequency|Set the output carrier macro channel for Sigfox frames.|
|AT$IF?|Get TX Frequency|Get the currently chosen TX frequency.|
|AT$DR=uint|Set RX Frequency|Set the reception carrier macro channel for Sigfox frames.|
|AT$DR?|Get RX Frequency|Get the currently chosen RX frequency.|
|AT$CW=uint,bit[,uint_opt]|Continuous Wave|To run emission tests for Sigfox certification it is necessary to send a<br>continuous wave, i.e. just the base frequency without any modulation.<br>Parameters:<br> **Name**<br>**Range**<br>**Description**<br>Frequency<br>800000000−<br>Continuous wave frequency in Hz.<br>999999999, 0<br>Use 868130000 for Sigfox or 0 to<br>keep previous frequency.<br>Mode<br>0, 1<br>Enable or disable carrier wave.<br>Power<br>0−14<br>Signal power setting | Default: 14|
|AT$CB=uint_opt,bit|Test Mode: TX constant byte|For emission testing it is useful to send a specific bit pattern. The first<br>parameter specifies the byte to send. Use ‘−1’ for a (pseudo−)random<br>pattern. Parameters:<br> **Name**<br>**Range**<br>**Description**<br>Pattern<br>0−255,−1<br>Byte to send. Use ‘−1’ for a<br>(pseudo−)random pattern.<br>Mode<br>0, 1<br>Enable or disable pattern test<br>mode.|
|AT$T?|Get Temperature|Measure internal temperature and return it in 1/10th of a degree Celsius.|
|AT$V?|Get Voltages|Return current voltage and voltage measured during the last<br>transmission in mV.|



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**12** 

**AX−SIP−SFEU, AX−SIP−SFEU−API** 

**Table 9. COMMANDS** (continued) 

|**Table 9. COMMANDS**(con|tinued)||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT$I=uint|Information|Display various product information:<br>0:<br>Software Name & Version<br>Example Response: AX−SF 1.1−RC1<br>1:<br>Contact Details<br>Example Response: onhelp@onsemi.com<br>2:<br>Silicon revision lower byte<br>Example Response: 90<br>3:<br>Silicon revision upper byte<br>Example Response: 51<br>4:<br>Major Firmware Version<br>Example Response: 1<br>5:<br>Minor Firmware Version<br>Example Response: 1<br>7:<br>Firmware Variant (Frequency Band etc. (EU/US))<br>Example Response: RC1<br>8:<br>Firmware VCS Version<br>Example Response:0<br>9:<br>Sigfox Library Version<br>Example Response: UDL1−1.8.9<br>10: Device ID<br>Example Response: 00012345<br>11: PAC<br>Example Response: 0123456789ABCDEF|
|AT$P=uint|Set Power Mode|To conserve power, the AX−SIP−SFEU can be put to sleep manually.<br>Depending on power mode, you will be responsible for waking up the<br>AX−SIP−SFEU again!<br>0:<br>software reset (settings will be reset to values in flash)<br>1:<br>sleep (send a break to wake up)<br>2:<br>deep sleep (toggle GPIO9 or RESET_N pin to wake up;<br>the AX−SIP−SFEU is not running and all settings will be reset!)|
|AT$WR|Save Config|Write all settings to flash (RX/TX frequencies, registers) so they survive<br>reset/deep sleep or loss of power.<br>Use AT$P=0 to reset the AX−SIP−SFEU and load settings from flash.|
|AT:Pn?|Get GPIO Pin|Return the setting of the GPIO Pin_n_;_n_can range from 0 to 14.<br>A character string is returned describing the mode of the pin, followed<br>by the actual value. If the pin is configured as analog pin, then the<br>voltage (range 0…1 V) is returned. The mode characters have the<br>following meaning:<br> **Mode**<br>**Description**<br> 0<br>Pin drives low<br>1<br>Pin drives high<br>Z<br>Pin is high impedance input<br>U<br>Pin is input with pull−up<br>A<br>Pin is analog input (GPIO pin 0…3 and 12…13 only)<br>T<br>Pin is driven by clock or DAC (GPIO pin0and 4 only)<br>The default mode after exiting reset is U on all GPIO pins.|



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**13** 

**AX−SIP−SFEU, AX−SIP−SFEU−API** 

**Table 9. COMMANDS** (continued) 

|**Table 9. COMMANDS**(con|tinued)||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT:Pn=?|Get GPIO Pin Range|Print a list of possible modes for a pin. The table below lists the<br>response.<br> **Pin**<br>**Modes**<br>P0<br>0, 1, Z, U, A, T<br>P1<br>0, 1, Z, U, A<br>P2<br>0, 1, Z, U, A<br>P3<br>0, 1, Z, U, A<br>P4<br>0, 1, Z, U, T<br>P5<br>0, 1, Z, U<br>P6<br>0, 1, Z, U<br>P7<br>0, 1, Z, U<br>P8<br>0, 1, Z, U<br>P9<br>0, 1, Z, U<br>P10<br>0, 1, Z, U<br>P11<br>0, 1, Z, U<br>P12<br>0, 1, Z, U, A<br>P13<br>0, 1, Z, U, A<br>P14<br>0, 1, Z, U|
|AT:Pn=mode|Set GPIO Pin|Set the GPIO pin mode.<br>For a list of the modes see the command AT:Pn?|
|AT:ADC Pn[−Pn[ (1V|10V)]]?|Get GPIO Pin Analog Voltage|Measure the voltage applied to a GPIO pin. The command also allows<br>measurement of the voltage difference across two GPIO pins. In<br>differential mode, the full scale range may also be specified as 1 V or<br>10 V. Note however that the pin input voltages must not exceed the<br>range 0…VDD_IO. The command returns the result as fraction of the<br>full scale range (1 V if none is specified). The GPIO pins referenced<br>should be initialized to analog mode before issuing this command.|
|AT:SPI[(A|B|C|D)]=bytes|SPI Transaction|This command clocks out_bytes_on the SPI port. The clock frequency is<br>312.5 kHz. The command returns the bytes read on MISO during output.<br>Optionally the clocking mode may be specified (default is A):<br> **Mode**<br>**Clock Inversion**<br>**Clock Phase**<br>A<br>normal<br>normal<br>B<br>normal<br>alternate<br>C<br>inverted<br>normal<br>D<br>inverted<br>alternate<br>D7<br>D7<br>D6<br>D6<br>D5<br>D5<br>D4<br>D4<br>D3<br>D3<br>D2<br>D2<br>D1<br>D1<br>D0<br>D0<br>SEL(GPIOx)<br>MOSI<br>MISO<br>SCK<br>A<br>B<br>C<br>D<br>Note that SEL, if needed, is not generated by this command, and must<br>instead be driven using standard GPIO commands (AT:Pn=0|1).|
|AT:CLK=freq,reffreq|Set Clock Generator|Output a square wave on the pin(s) set to T mode. The frequency of<br>the square wave is (freq / 216)× reffreq. Possible values for reffreq are<br>20000000, 10000000, 5000000, 2500000, 1250000, 625000, 312500,<br>156250. Possible values for freq are 0…65535.|
|AT:CLK=OFF|Turn off Clock Generator|Switch off the clock generator|
|AT:CLK?|Get Clock Generator|Return the settings of the clock generator. Two numbers are returned,<br>freq and reffreq.|
|AT:DAC=value|Set�� DAC|Output a�� DAC value on the pin(s) set to T mode. Parameter value<br>may be in the range−32768…32767. The average output voltage is<br>(1/2 + value / 217)× VDD.<br>An external low pass filter is needed to get smooth output voltages.<br>The modulation frequency is 20 MHz. A possible low pass filter choice<br>is a simple RC low pass filter with R = 10 k� and C = 1�F.|



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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

**Table 9. COMMANDS** (continued) 

|**Table 9. COMMANDS**(con|tinued)||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT:DAC=OFF|Turn off�� DAC|Switch off the DAC|
|AT:DAC?|Get�� DAC|Return the DAC value|
|AT$TM=mode,config|Activates the Sigfox Testmode|Available test modes:<br>0.<br>TX BPSK<br>Send only BPSK with Synchro Bit + Synchro frame +<br>PN sequence: No hopping centered on the TX_frequency. Config<br>bits 0 to 6 define the number of repetitions. Bit 7 of config defines if<br>a delay is applied or not between the frames in the loop (1 means no<br>delay).<br>1.<br>TX Protocol:<br>Tx mode with full protocol with Sigfox key: Send Sigfox protocol<br>frames with initiate downlink flag = True. Config defines the number<br>of repetitions.<br>2.<br>RX Protocol:<br>This mode tests the complete downlink protocol in Downlink only.<br>Config defines the RX on time in seconds.<br>3.<br>RX GFSK:<br>RX mode with known pattern with SB + SF + Pattern on<br>RX_frequency (internal comparison with received frame⇔ known<br>pattern = AA AA B2 27 1F 20 41 84 32 68 C5 BA AE 79 E7 F6 DD<br>9B. Config defines the number of repetitions.<br>4.<br>RX Sensitivity:<br>Does uplink + downlink frame with Sigfox key and specific timings.<br>This test is specific to Sigfox’s test equipment & software.<br>5.<br>TX Synthesis:<br>Does one uplink frame on each Sigfox channel to measure<br>frequency synthesis step.|
|AT$SE|Starts<br>AT$TM=3,255 indefinitely|Convenience command for sensitivity tests|
|AT$SL[=frame]|Send local loop|Sends a local loop frame with optional payload of 1 to 12 bytes.<br>Default payload: 0x84, 0x32, 0x68, 0xC5, 0xBA, 0x53, 0xAE, 0x79,<br>0xE7, 0xF6, 0xDD, 0x9B.|
|AT$RL|Receive local loop|Starts listening for a local loop.|
|AT$TP=repetitions|Transient power<br>measurements mode|Used for transmitter transient power measurements. The command<br>switches the transmitter ON and OFF. During ON state (pseudo)<br>random bit pattern is send. Repetitions is the number of performed<br>measurements, acceptable range is 1−255.|
|AT$PN=mode,repetitions|Send & Receive PN9<br>bitstream for BER<br>measurements|Available modes:<br>0:<br>send PN9 bit stream. Repetitions = 1 is required to start sending.<br>Repetitions = 0 stops sending<br>3:<br>receive PN9 bit stream, calculate BER with 3 digits precision<br>4:<br>receive PN9 bit stream, calculate BER with 4 digits precision<br>5:<br>receive PN9 bit stream, calculate BER with 5 digits precision<br>Mode = 3−5 receives the PN9 bitstream and decodes it into an actual<br>BER measurement. Reports the BER for each repetition.<br>Repetitions is the number of performed measurements, acceptable<br>range is 1−255. Higher precision result takes longer time to compute.<br>PN9 is 9−bit pseudo random binary sequence.|



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**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **Table 10. REGISTERS** 

|**Number**|**Name**|**Description**|**Default**|**Range**|**Units**|
|---|---|---|---|---|---|
|300|Out Of Band<br>Period|AX−SIP−SFEU sends periodic static<br>messages to indicate that it is alive.<br>Set to 0 to disable.|24|0−24|hours|
|302|Power Level|The output power of the radio. Note: this set-<br>ting is used for all TX modes except AT$CW.|14|0−14|0: −1dBm<br>14: 13 dBm|
|410|Encryption Key<br>Configuration|Set to zero for normal operation.<br>Set to one for use with the Sigfox Network<br>Emulator Kit (SNEK).|0|0−1|0: private key<br>1: public key|
|411|Specific ID and Key for<br>certification|Set to zero for use of regular device ID and<br>key.<br>Set to one to use specific ID and key for test<br>sample devices for Sigfox certification.|0|0−1|0: regular<br>sample<br>1: test<br>sample|
|500|RSSI Offset|RSSI offset value can be applied to fine tune<br>the RSSI level that the device reports.|0|−128…127|dB|



## **APPLICATION INFORMATION** 

## **Typical Application Diagrams** 

_Typical AX−SIP−SFEU / AX−SIP−SFEU−API Application Diagram_ 

**Figure 5. Typical Application Diagram** 

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**16** 

**AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **SIP38 RECOMMENDED PAD LAYOUT** 

1. PCB land and solder masking recommendations are shown in Figure 6. 

**==> picture [194 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
F A B<br>Solder Mask<br>PCB<br>Thermal Pad<br>PCB Land<br>Solder Mask<br>Opening<br>E<br>C D<br>**----- End of picture text -----**<br>


- A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum 

- B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum 

- C = Clearance from PCB land edge to solder mask opening to be as tight as possible to ensure that some solder mask remains between PCB pads 

- D = PCB land length = SIP solder pad length + 0.1 mm 

- E = PCB land width = SIP solder pad width + 0.1 mm 

- F = Clearance from solder mask opening to the edge of the package, 0.1 mm minimum to avoid shorts to the package metal shielding 

## **Figure 6. PCB Land and Solder Mask Recommendations** 

2. Thermal vias should be used around the PCB thermal pads (middle ground pads) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. The number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 

3. Increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. In general, adding more metal through the PC board under the SiP will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. 

## **Assembly Process** 

_Stencil Design & Solder Paste Application_ 

1. Stainless steel stencils are recommended for solder paste application. 

2. A stencil thickness of 0.125–0.150 mm (5–6 mils) is recommended for screening. 

3. For the PCB thermal pads, solder paste should be printed on the PCB by designing a stencil with an array of 6 openings for each of the 6 thermal/GND pads. 

4. The aperture opening for the signal pads should be between 50−80% of the SIP pad area as shown in Figure 7. 

5. Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. 

6. The fine pitch of the SiP leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 

7. No−clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water−soluble flux is used. 

Minimum 50% Coverage 

**==> picture [64 x 147] intentionally omitted <==**

62% Coverage 

**==> picture [63 x 147] intentionally omitted <==**

Maximum 80% Coverage 

**==> picture [63 x 147] intentionally omitted <==**

**Figure 7. Solder Paste Application on Pins** 

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**17** 

## **AX−SIP−SFEU, AX−SIP−SFEU−API** 

## **Life Support Applications** 

This product is not designed for use in life support appliances, devices or in systems where malfunction of this product can reasonably be expected to result in personal injury. ON Semiconductor customers using or selling this product for use in such applications do so at their own risk and agree to fully indemnify ON Semiconductor for any damages resulting from such improper use or sale. 

## **Device Information** 

The following device information can be queried using the AT−Commands AT$I=4, AT$I=5 for the APP version and AT$I=2, AT$I=3 for the chip version. 

**Table 11. DEVICE VERSIONS** 

|**Product**|**Part Number**|**APP Version**|**APP Version**|**SiP Version**|**SiP Version**|
|---|---|---|---|---|---|
|||**[0]**|**[1]**|**[0]**|**[1]**|
|AX−SIP−SFEU|AX−SIP−SFEU−1−01−TX30|0x01|0x01|0x90|0x51|
|AX−SIP−SFEU−API|AX−SIP−SFEU−API−1−01−TX30|0x01|0x01|0x90|0x51|



Sigfox is a registered trademark of Sigfox SARL. 

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**18** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **SIP38 9x7** CASE 127EU ISSUE A 

## DATE 14 MAR 2018 

**==> picture [411 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
GENERIC 0 . 65 38 X 0 . 50<br>MARKING DIAGRAM* PITCH 38X 0 . 35<br>XXXXXXXXXXX RECOMMENDED<br>XXXXXXXXXXX MOUNTING FOOTPRINT<br>AWLWLYYWW<br>*This information is generic. Please refer to<br>A = Assembly Location device data sheet for actual part marking.<br>WL = Wafer Lot Pb−Free indicator, “G” or microdot “ ”,<br>YY = Year may or may not be present. Some products<br>WW = Work Week may not follow the Generic Marking.<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>98AON77413G Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>**----- End of picture text -----**<br>


## **DOCUMENT NUMBER:** 

## **SIP38 9x7** 

**PAGE 1 OF 1** 

## **DESCRIPTION:** 

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www.onsemi.com 

© Semiconductor Components Industries, LLC, 2018 

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